Sorry I didn't get the point completely. Do you mean the settings are not compatible with FSP code? Or do you mean the settings might be conflicting themselves.

Since the above settings were read from SPD and the chip vendor must have definitely set them correctly, I assume you meant first sentence.

Please correct me.

Regards,

Naveen

Get Outlook for Android

---

From: Wim Vervoorn <wvervoorn@eltan.com>
Sent: Tuesday, October 29, 2019 3:47:34 PM
To: Naveen Chaudhary <naveenchaudhary2010@hotmail.com>; Nico Huber <nico.h@gmx.de>; David Hendricks <david.hendricks@gmail.com>
Cc: coreboot@coreboot.org <coreboot@coreboot.org>
Subject: RE: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table"

 

Hello Naveen,

 

This is the important part. This indicates the what you selected is not supported.

 

Please review your settings carefully. This isn't a single check. The code validates the SPD settings against the other settings you made.

So please make sure you are passing in a DDR4 SPD when you select DDR4 mode. Also please make sure the SPD settings are in

The list of supported configuration for the chip.

 

Check POR Compatibility -- Started

primaryWidthDDR4: 1, rowBitsDDR4: 16, columnBitsDDR4: 10, bankGroupsDDR4: 4

primaryWidthDDR4: 1, rowBitsDDR4: 16, columnBitsDDR4: 10, bankGroupsDDR4: 4

Unknown DIMM population *****

Check POR Compatibility - 17ms

Initialize DDR Clocks -- Started

Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000

Configuration not in POR table!  *** (This basically indicates you are trying to do something that is not supported by the chipset).

 

Best regards,

Wim

 

From: Naveen Chaudhary [mailto:naveenchaudhary2010@hotmail.com]
Sent: Tuesday, October 29, 2019 10:44 AM
To: Wim Vervoorn <wvervoorn@eltan.com>; Nico Huber <nico.h@gmx.de>; David Hendricks <david.hendricks@gmail.com>
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table"

 

Thanks Wim.

I will give a try and pass a 512 byte hex block corresponding to the SPD data and if it works, I can play with the hex values to find out the right configuration.

BTW, any idea which field can impact the ddrfreq which was reported as error in the initial logs?

Regards,

Naveen

Get Outlook for Android

 

---

From: Wim Vervoorn <wvervoorn@eltan.com>
Sent: Tuesday, October 29, 2019 3:07:44 PM
To: Nico Huber <nico.h@gmx.de>; Naveen Chaudhary <naveenchaudhary2010@hotmail.com>; David Hendricks <david.hendricks@gmail.com>
Cc: coreboot@coreboot.org <coreboot@coreboot.org>
Subject: RE: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table"

 

Hello Naveen,

You should use the "MemDownCh0Dimm0SpdPtr" to point to a buffer containing the SPD data and set MemDownEnable" to 1.

Best Regards,
Wim Vervoorn



-----Original Message-----
From: Nico Huber [mailto:nico.h@gmx.de]
Sent: Sunday, October 27, 2019 11:33 AM
To: Naveen Chaudhary <naveenchaudhary2010@hotmail.com>; David Hendricks <david.hendricks@gmail.com>
Cc: coreboot@coreboot.org
Subject: [coreboot] Re: Coreboot FSP fails to initialize RAM - "Configuration not in POR table"

Hello Naveen,

On 27.10.19 05:02, Naveen Chaudhary wrote:
> Does this mean that there is a way in FSP to define custom settings(configs) for DIMMs? In the FSP integration guide for BroadwellDE (https://github.com/IntelFsp/FSP/tree/master/BroadwellDEFspBinPkg/Docs) I don't see any relevant data member where we could define pointer to custom SPD settings or pass individual DIMMs configurations.

there is the memory-down option. It seems undocumented if that does more than switching from on-DIMM SPDs to SPD files. Maybe it's worth a try.
If that doesn't work out, you can always overwrite the SPDs on your DIMM's EEPROMs. Always keep a backup, though.

Hope that helps,
Nico
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