Index: src/northbridge/amd/gx2/northbridgeinit.c
===================================================================
--- src/northbridge/amd/gx2/northbridgeinit.c	(revision 6225)
+++ src/northbridge/amd/gx2/northbridgeinit.c	(working copy)
@@ -13,8 +13,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/cache.h>
 
-/* put this here for now, we are not sure where it belongs */
-
 struct gliutable
 {
 	unsigned long desc_name;
@@ -23,29 +21,29 @@
 };
 
 struct gliutable gliu0table[] = {
-	{.desc_name=GLIU0_P2D_BM_0,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=  0x0FFF80},			/* 0-7FFFF to MC */
-	{.desc_name=GLIU0_P2D_BM_1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},	/* 80000-9ffff to Mc */
-	{.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=  0x03},		/* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
-	{.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=GLIU0_P2D_BMO_1,    .desc_type= BMO_DMM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=GLIU0_P2D_BMO_0,    .desc_type= BMO_SMM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
-	{.desc_name=GL_END,           .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+	{.desc_name=GLIU0_P2D_BM_0,	.desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80},		/* 0-7FFFF to MC */
+	{.desc_name=GLIU0_P2D_BM_1,	.desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},	/* 80000-9ffff to Mc */
+	{.desc_name=GLIU0_P2D_SC_0,	.desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03},		/* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
+	{.desc_name=GLIU0_P2D_R_0,	.desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU0_P2D_BMO_1,	.desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU0_P2D_BMO_0,	.desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU0_GLD_MSR_COH,	.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
+	{.desc_name=GL_END,		.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };
 
 struct gliutable gliu1table[] = {
-	{.desc_name=GLIU1_P2D_BM_0,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},		/* 0-7FFFF to MC */
-	{.desc_name=GLIU1_P2D_BM_1,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},	/* 80000-9ffff to Mc */
-	{.desc_name=GLIU1_P2D_SC_0,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03},		/* C0000-Fffff split to MC and PCI (sub decode) */
-	{.desc_name=GLIU1_P2D_R_0,.desc_type=  R_SYSMEM,.hi=  MSR_GL0,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=GLIU1_P2D_BM_4,.desc_type=  BM_DMM,.hi=  MSR_GL0,.lo=  0x0},				/* Catch and fix dynamicly. */
-	{.desc_name=GLIU1_P2D_BM_3,.desc_type=  BM_SMM,.hi=  MSR_GL0,.lo=  0x0},				/* Catch and fix dynamicly. */
-	{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
-	{.desc_name=GLIU1_IOD_SC_0,.desc_type=  SCIO,.hi=  (GL1_GLCP << 29) + 0x0,.lo=  0x033000F0}, /* FooGlue FPU 0xF0 */
-	{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
+	{.desc_name=GLIU1_P2D_BM_0,	.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80},		/* 0-7FFFF to MC */
+	{.desc_name=GLIU1_P2D_BM_1,	.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
+	{.desc_name=GLIU1_P2D_SC_0,	.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03},		/* C0000-Fffff split to MC and PCI (sub decode) */
+	{.desc_name=GLIU1_P2D_R_0,	.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU1_P2D_BM_4,	.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU1_P2D_BM_3,	.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU1_GLD_MSR_COH,	.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
+	{.desc_name=GLIU1_IOD_SC_0,	.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0},	/* FooGlue FPU 0xF0 */
+	{.desc_name=GL_END,		.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };
 
-struct gliutable *gliutables[]  = {gliu0table, gliu1table, 0};
+struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
 
 struct msrinit
 {
@@ -53,7 +51,7 @@
 	msr_t msr;
 };
 
-struct msrinit ClockGatingDefault [] = {
+struct msrinit ClockGatingDefault[] = {
 	{GLIU0_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
 	/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */
 	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},
@@ -64,7 +62,7 @@
 	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
 	{GLPCI_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
 	{FG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},	/* Always on */
-	{0xffffffff, 				{0xffffffff, 0xffffffff}},
+	{0xFFFFFFFF, 				{0xFFFFFFFF, 0xFFFFFFFF}},
 };
 
 /* All On */
@@ -78,7 +76,7 @@
 	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
 	{GLPCI_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
 	{FG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},
- 	{0xffffffff, 				{0xffffffff, 0xffffffff}},
+ 	{0xFFFFFFFF, 				{0xFFFFFFFF, 0xFFFFFFFF}},
 };
 
 /* Performance */
@@ -87,11 +85,11 @@
 	{GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x0001}},
 	{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0155}},
 	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
-	{0xffffffff, 				{0xffffffff, 0xffffffff}},
+	{0xFFFFFFFF, 				{0xFFFFFFFF, 0xFFFFFFFF}},
 };
 
 /* SET GeodeLink PRIORITY */
-struct msrinit GeodeLinkPriorityTable [] = {
+struct msrinit GeodeLinkPriorityTable[] = {
 	{CPU_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0220}},		/* CPU Priority. */
 	{DF_GLD_MSR_MASTER_CONF,	{.hi=0x00,.lo=0x0000}},		/* DF Priority. */
 	{VG_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0720}},		/* VG Primary and Secondary Priority. */
@@ -99,7 +97,7 @@
 	{GLPCI_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0027}},		/* GLPCI Priority + PID */
 	{GLCP_GLD_MSR_CONF,		{.hi=0x00,.lo=0x0001}},		/* GLCP Priority + PID */
 	{FG_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0622}},		/* FG PID */
-	{0x0FFFFFFFF, 			{0x0FFFFFFFF, 0x0FFFFFFFF}},	/* END */
+	{0xFFFFFFFF, 			{0xFFFFFFFF, 0xFFFFFFFF}},	/* END */
 };
 
 /* do we have dmi or not? assume NO per AMD */
@@ -129,33 +127,30 @@
 	}
 }
 
-/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here.
- * CLEAN ME UP
- */
-/* yes, this duplicates later code, but it seems that is how they want it done. */
 static void SysmemInit(struct gliutable *gl)
 {
 	msr_t msr;
 	int sizembytes, sizebytes;
 
 	/* Figure out how much RAM is in the machine and alocate all to the
-	 * system. We will adjust for SMM and DMM now and Frame Buffer later.
+	 * system. We will adjust for SMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
-	printk(BIOS_DEBUG, "%s: enable for %dm bytes\n", __func__, sizembytes);
+	printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);
 	sizebytes = sizembytes << 20;
 
-	sizebytes -= SMM_SIZE*1024 +1;
+	sizebytes -= ((SMM_SIZE * 1024) + 1);
 
 	if (havedmi)
 		sizebytes -= DMM_SIZE * 1024 + 1;
 
+	/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
+	   The top 8 bits go into 0-7 of msr.hi. */
 	sizebytes -= 1;
 	msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
-	/* set up sizebytes to fit into msr.lo */
-	sizebytes <<= 8; /* what? well, we want bits 23:12 in bits 31:20. */
-	sizebytes &= 0xfff00000;
-	sizebytes |= 0x100;
+	sizebytes <<= 8;	/* move bits 23:12 in bits 31:20. */
+	sizebytes &= 0xFFF00000;
+	sizebytes |= 0x100;	/* start at 1MB */
 	msr.lo = sizebytes;
 	wrmsr(gl->desc_name, msr);	/* MSR - see table above */
 	msr = rdmsr(gl->desc_name);
@@ -216,10 +211,10 @@
 static void SMMGL0Init(struct gliutable *gl)
 {
 	msr_t msr;
-	int sizebytes = sizeram()<<20;
+	int sizebytes = sizeram() << 20;
 	long offset;
 
-	sizebytes -= SMM_SIZE*1024;
+	sizebytes -= (SMM_SIZE * 1024);
 
 	if (havedmi)
 		sizebytes -= DMM_SIZE * 1024;
@@ -231,10 +226,10 @@
 	offset >>= 12;
 
 	msr.hi = offset << 8;
-	msr.hi |= SMM_OFFSET>>24;
+	msr.hi |= SMM_OFFSET >> 24;
 
 	msr.lo = SMM_OFFSET << 8;
-	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
+	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xFFFFF;
 
 	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
 	msr = rdmsr(gl->desc_name);
@@ -244,14 +239,14 @@
 static void SMMGL1Init(struct gliutable *gl)
 {
 	msr_t msr;
-	printk(BIOS_DEBUG, "%s:\n", __func__ );
+	printk(BIOS_DEBUG, "%s:\n", __func__);
 
 	msr.hi = gl->hi;
 	/* I don't think this is needed */
-	msr.hi &= 0xffffff00;
+	msr.hi &= 0xFFFFFF00;
 	msr.hi |= (SMM_OFFSET >> 24);
 	msr.lo = SMM_OFFSET << 8;
-	msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
+	msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xFFFFF;
 
 	wrmsr(gl->desc_name, msr);	/* MSR - See table above */
 	msr = rdmsr(gl->desc_name);
@@ -260,8 +255,8 @@
 
 static void GLIUInit(struct gliutable *gl)
 {
-	while (gl->desc_type != GL_END){
-		switch(gl->desc_type){
+	while (gl->desc_type != GL_END) {
+		switch (gl->desc_type) {
 		default:
 			/* For Unknown types: Write then read MSR */
 			writeglmsr(gl);
@@ -277,15 +272,15 @@
 			DMMGL0Init(gl);
 			break;
 
-		case BM_DMM	: /* check for a DMM entry */
+		case BM_DMM: /* check for a DMM entry */
 			DMMGL1Init(gl);
 			break;
 
-		case BMO_SMM	: /* check for a SMM entry */
+		case BMO_SMM: /* check for a SMM entry */
 			SMMGL0Init(gl);
 			break;
 
-		case BM_SMM	: /* check for a SMM entry */
+		case BM_SMM: /* check for a SMM entry */
 			SMMGL1Init(gl);
 			break;
 		}
@@ -311,13 +306,13 @@
 	/* R0 - GLPCI settings for Conventional Memory space. */
 	msr.hi =  (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;	/* 640 */
 	msr.lo =  0;						/* 0 */
-	msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
+	msr.lo |= GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
 	msrnum = GLPCI_RC0;
 	wrmsr(msrnum, msr);
 
 	/* R1 - GLPCI settings for SysMem space. */
 	/* Get systop from GLIU0 SYSTOP Descriptor */
-	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
+	for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
 		if (gliu0table[i].desc_type == R_SYSMEM) {
 			gl = &gliu0table[i];
 			break;
@@ -328,38 +323,38 @@
 		msrnum = gl->desc_name;
 		msr = rdmsr(msrnum);
 		/* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00
-                 * translates to a base of 0x00100000 and top of 0xffbf0000
-                 * base of 1M and top of around 256M
+		 * translates to a base of 0x00100000 and top of 0xffbf0000
+		 * base of 1M and top of around 256M
 		 */
 		/* we have to create a page-aligned (4KB page) address for base and top
 		 * so we need a high page aligned addresss (pah) and low page aligned address (pal)
 		 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
 		 */
 		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
-		pah = ((msr.hi &0xff) << 12) | ((msr.lo >> 20) & 0xfff);
+		pah = ((msr.hi & 0xFF) << 12) | ((msr.lo >> 20) & 0xFFF);
 		/* we have the page address. Now make it a page-aligned address */
 		pah <<= 12;
 
 		pal = msr.lo << 12;
-		msr.hi =  pah;
-		msr.lo =  pal;
+		msr.hi = pah;
+		msr.lo = pal;
 		msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
-		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
+		printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
 		msrnum = GLPCI_RC1;
 		wrmsr(msrnum, msr);
 	}
 
 	/* R2 - GLPCI settings for SMM space. */
-	msr.hi =  ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
-	msr.lo =  (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
+	msr.hi = ((SMM_OFFSET + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
+	msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
 	msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
 	msrnum = GLPCI_RC2;
 	wrmsr(msrnum, msr);
 
 	/* this is done elsewhere already, but it does no harm to do it more than once */
-	/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */
-	msr.lo =  0x021212121;		/* cache disabled and write serialized */
-	msr.hi =  0x021212121;		/* cache disabled and write serialized */
+	/* write serialize memory hole to PCI. Need to unWS when something is shadowed regardless of cachablility. */
+	msr.lo = 0x021212121;	/* cache disabled and write serialized */
+	msr.hi = 0x021212121;	/* cache disabled and write serialized */
 
 	msrnum = CPU_RCONF_A0_BF;
 	wrmsr(msrnum, msr);
@@ -372,80 +367,82 @@
 
 	/* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */
 	msrnum = GLPCI_A0_BF;
-	msr.hi =  0x35353535;
-	msr.lo =  0x35353535;
+	msr.hi = 0x35353535;
+	msr.lo = 0x35353535;
 	wrmsr(msrnum, msr);
 
 	msrnum = GLPCI_C0_DF;
-	msr.hi =  0x35353535;
-	msr.lo =  0x35353535;
+	msr.hi = 0x35353535;
+	msr.lo = 0x35353535;
 	wrmsr(msrnum, msr);
 
 	msrnum = GLPCI_E0_FF;
-	msr.hi =  0x35353535;
-	msr.lo =  0x35353535;
+	msr.hi = 0x35353535;
+	msr.lo = 0x35353535;
 	wrmsr(msrnum, msr);
 
 	/* Set WSREQ */
 	msrnum = CPU_DM_CONFIG0;
 	msr = rdmsr(msrnum);
-	msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
+	msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
 	msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT	;	/* reduce to 1 for safe mode. */
 	wrmsr(msrnum, msr);
 
 	/* we are ignoring the 5530 case for now, and perhaps forever. */
 
-	/* 5535 NB Init */
+	/* 553X NB Init */
+
+	/* Arbiter setup */
 	msrnum = GLPCI_ARB;
 	msr = rdmsr(msrnum);
-	msr.hi |=  GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
-	msr.lo |=  GLPCI_ARB_LOWER_IIE_SET;
+	msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
+	msr.lo |= GLPCI_ARB_LOWER_IIE_SET;
 	wrmsr(msrnum, msr);
 
 	msrnum = GLPCI_CTRL;
 	msr = rdmsr(msrnum);
 
-	msr.lo |=  GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; 	/* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
-	msr.lo |=  GLPCI_CTRL_LOWER_LDE_SET;
+	msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; 	/* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
+	msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
 
-	msr.lo &=  ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
-	msr.lo |=  0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
+	msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
+	msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
 
-	msr.lo &=  ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
-	msr.lo |=  0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
+	msr.lo &= ~(0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
+	msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
 
-	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
-	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
+	msr.hi &= ~(0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT);
+	msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
 
-	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
-	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
+	msr.hi &= ~(0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT);
+	msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
 
-	msr.hi &=  ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
-	msr.hi |=  0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
+	msr.hi &= ~(0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
+	msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
 
-	msr.hi &=  ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
+	msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
 	msr.hi |=  0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
 
-	msr.hi &=  ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
+	msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
 	msr.hi |=  0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
 	wrmsr(msrnum, msr);
 
 	/* Set GLPCI Latency Timer. */
 	msrnum = GLPCI_CTRL;
 	msr = rdmsr(msrnum);
-	msr.hi |=  0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; 	/* Change once 1.x is gone. */
+	msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; 	/* Change once 1.x is gone. */
 	wrmsr(msrnum, msr);
 
 	/* GLPCI_SPARE */
 	msrnum = GLPCI_SPARE;
 	msr = rdmsr(msrnum);
-	msr.lo &=  ~ 0x7;
-	msr.lo |=  GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
+	msr.lo &= ~0x7;
+	msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
 	wrmsr(msrnum, msr);
 }
 
 /* Enable Clock Gating. */
-static void ClockGatingInit (void)
+static void ClockGatingInit(void)
 {
 	msr_t msr;
 	struct msrinit *gating = ClockGatingDefault;
@@ -471,7 +468,7 @@
 	lea	si, ClockGatingPerformance
 #endif
 
-	for(i = 0; gating->msrnum != 0xffffffff; i++) {
+	for (i = 0; gating->msrnum != 0xFFFFFFFF; i++) {
 		msr = rdmsr(gating->msrnum);
 		printk(BIOS_DEBUG, "%s: MSR 0x%08lx is 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo);
 		msr.hi |= gating->msr.hi;
@@ -479,26 +476,27 @@
 		printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to  0x%08x:0x%08x\n", __func__,
 			gating->msrnum, msr.hi, msr.lo);
 		wrmsr(gating->msrnum, msr);	/* MSR - See the table above */
-		gating +=1;
+		gating += 1;
 	}
 }
 
 static void GeodeLinkPriority(void)
 {
 	msr_t msr;
+	
 	struct msrinit *prio = GeodeLinkPriorityTable;
 	int i;
 
-	for(i = 0; prio->msrnum != 0xffffffff; i++) {
+	for (i = 0; prio->msrnum != 0xFFFFFFFF; i++) {
 		msr = rdmsr(prio->msrnum);
 		printk(BIOS_DEBUG, "%s: MSR 0x%08lx is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
 		msr.hi |= prio->msr.hi;
-		msr.lo &= ~0xfff;
+		msr.lo &= ~0xFFF;
 		msr.lo |= prio->msr.lo;
 		printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
 			prio->msrnum, msr.hi, msr.lo);
 		wrmsr(prio->msrnum, msr);	/* MSR - See the table above */
-		prio +=1;
+		prio += 1;
 	}
 }
 
@@ -510,6 +508,7 @@
 static uint64_t getShadow(void)
 {
 	msr_t msr;
+	
 	msr = rdmsr(GLIU0_P2D_SC_0);
 	return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
 }
@@ -538,7 +537,7 @@
 	}
 
 	/* load up C000 settings in eax. */
-	for ( ; bit; bit--) {
+	for (; bit; bit--) {
 		msr.lo <<= 8;
 		msr.lo |= 1;			/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
@@ -558,7 +557,7 @@
 	}
 
 	/* load up E000 settings in eax. */
-	for ( ; bit; bit--) {
+	for (; bit; bit--) {
 		msr.lo <<= 8;
 		msr.lo |= 1;			/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
@@ -579,7 +578,7 @@
 	/* Set the Enable Register. */
 	msr = rdmsr(GLPCI_REN);
 	msr.lo &= 0xFFFF00FF;
-	msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8);
+	msr.lo |= ((shadowLo & 0xFFFF0000) >> 8);
 	wrmsr(GLPCI_REN, msr);
 }
 
@@ -591,7 +590,7 @@
 {
 	int i;
 	msr_t msr;
-	struct gliutable* pTable;
+	struct gliutable *pTable;
 	uint32_t shadowLo, shadowHi;
 
 	shadowLo = (uint32_t) shadowSettings;
@@ -600,7 +599,7 @@
 	setShadowRCONF(shadowHi, shadowLo);
 	setShadowGLPCI(shadowHi, shadowLo);
 
-	for(i = 0; gliutables[i]; i++) {
+	for (i = 0; gliutables[i]; i++) {
 		for (pTable = gliutables[i]; pTable->desc_type != GL_END; pTable++) {
 			if (pTable->desc_type == SC_SHADOW) {
 
@@ -615,7 +614,6 @@
 	}
 }
 
-/* Set up a stack for ease of further testing. */
 static void shadowRom(void)
 {
 	uint64_t shadowSettings = getShadow();
@@ -646,7 +644,7 @@
 	uint8_t SysMemCacheProp;
 
 	/* Locate SYSMEM entry in GLIU0table */
-	for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
+	for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
 		if (gliu0table[i].desc_type == R_SYSMEM) {
 			gl = &gliu0table[i];
 			break;
@@ -658,7 +656,6 @@
 	}
 
 /* sysdescfound: */
-	/* found the descriptor... get its contents */
 	msr = rdmsr(gl->desc_name);
 
 	/* 20 bit address -  The bottom 12 bits go into bits 20-31 in eax, the
@@ -669,10 +666,10 @@
 	msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT;	/* 8 */
 
 	/* Set Default SYSMEM region properties */
-	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	/* 8 (or ~8) */
+	msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH;	/* NOT writethrough == writeback 8 (or ~8) */
 
 	/* Set PCI space cache properties */
-	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);	/* only need the bottom bits and lets clean the rest of edx */
+	msr.hi = (DEVRC_RCONF_DEFAULT >> 4);	/* setting is split betwwen hi and lo... */
 	msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
 
 	/* Set the ROMBASE. This is usually FFFC0000h */
@@ -684,7 +681,7 @@
 	/* now program RCONF_DEFAULT */
 	wrmsr(CPU_RCONF_DEFAULT, msr);
 
-	/* RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. */
+	/* RCONF_BYPASS: Cache tablewalk properties and SMM header access properties. */
 	/* Set to match system memory cache properties. */
 	msr = rdmsr(CPU_RCONF_DEFAULT);
 	SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
@@ -724,7 +721,7 @@
 	int i;
 	printk(BIOS_DEBUG, "Enter %s\n", __func__);
 
-	for(i = 0; gliutables[i]; i++)
+	for (i = 0; gliutables[i]; i++)
 		GLIUInit(gliutables[i]);
 
 	GeodeLinkPriority();
@@ -749,7 +746,6 @@
 	GLPCIInit();
 	ClockGatingInit();
 	__asm__("FINIT\n");
-	/* CPUBugsFix -- called elsewhere */
 	printk(BIOS_DEBUG, "Exit %s\n", __func__);
 }
 
