Re: [coreboot] Getting serial output from w83627hf?

[Alp Eren Köse]

> Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e
> Register dump:
> idx 02 20 21 22 23 24 25 26  28 29 2a 2b 2c 2e 2f
> val ff 52 41 ff fe c0 00 00  00 00 fe c0 ff 00 ff
> def 00 52 NA ff 00 MM 00 00  00 00 7c c0 00 00 00
>
> CR24 (idx 24, in the above output) means control register 24, here is a

link to the
> superio's datasheet: http://www.itox.com/pages/support/wdt/W83627HF.pdf

Ok, I got it, but doesn't CR24 is set inside the w83627hf_set_clksel_48()
function..
I still got no output from the serial unfortunately? :(

2011/10/18 Idwer Vollering
> 2011/10/18 Alp Eren Köse
> > Hi thanks all for your help,
> >
> > I have arranged the "devicetree.cb" as suggested, you can see it at the
> > attachment.
> > Put the superio chip under the LPC bridge section, but I didn't get how
> > did you know it?
> >
> > Added those to the romstage.c:
> > > #include "superio/winbond/w83627hf/early_serial.c"
> > > #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
> > > w83627hf_set_clksel_48(SERIAL_DEV);
> >
> > main() looks like this now:
> > ....... // omitted
> > sch_enable_lpc();
> > w83627hf_set_clksel_48(SERIAL_DEV);    // NEWLY ADDED
> > w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);    // NEWLY ADDED
> > uart_init();      // NEWLY ADDED
> > console_init();
> > printk(BIOS_DEBUG, "\n");      // NEWLY ADDED
> > ....... // omitted
> > > The bit that controls the clock speed is in CR24.
> >
> > But what about this, I don't know where CR24 is and how to set it? Sorry I
> > am just really new in such stuff :s
>
> Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e
> Register dump:
> idx 02 20 21 22 23 24 25 26  28 29 2a 2b 2c 2e 2f
> val ff 52 41 ff fe c0 00 00  00 00 fe c0 ff 00 ff
> def 00 52 NA ff 00 MM 00 00  00 00 7c c0 00 00 00
>
> CR24 (idx 24, in the above output) means control register 24, here is a
> link to the superio's datasheet:
> http://www.itox.com/pages/support/wdt/W83627HF.pdf
> > > SCH boards don't use the serial port but the EHCI debug port to show
> >
> > output on? See src/mainboard
> > > /iwave/iWRainbowG6/devicetree.cb, it doesn't have the superio included.
> >
> > So does it mean I won't be able to get output from the serial port on this
> > device for debugging?
> > > Can you show the output from "superiotool -deV"  too? Thanks.
> >
> > Sure you can find the output in the attachment.
> >
> > By the way all I get is \0x00 when I open the board and another \0x00 when
> > I close it..
> >
> > Thanks in advance,
> > Alp
> >
> > 2011/10/17 Idwer Vollering
> > > Comments inline:
> > >
> > > 2011/10/17 Idwer Vollering
> > > > 2011/10/17 Alp Eren Köse
> > > > > Hi all,
> > > > >
> > > > > I can't get serial output from the board I am trying to put coreboot
> > > > > on, so I am not able to go any further to see whats going on..
> > > > > The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e.
> > > >
> > > > It is likely that you need to set the serial port's speed in romstage.c:
> > > >
> > > > // omitting includes, license header
> > > > #include "superio/winbond/w83627hf/early_serial.c"
> > > > #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
> > > >
> > > > Add this line to main():
> > > > w83627hf_set_clksel_48(SERIAL_DEV);
> > >
> > > The bit that controls the clock speed is in CR24.
> > > > > I couldn't figure out where to put the "chip superio/winbond/w83627hf"
> > > > > section in the "devicetree.cb" file layout?
> > > >
> > > > SCH boards don't use the serial port but the EHCI debug port to show
> > > > output on? See src/mainboard/iwave/iWRainbowG6/devicetree.cb, it doesn't
> > > > have the superio included.
> > > >
> > > > What I would do is put it inside the LPC bridge section, note that I
> > > > don't know how the superio is actually attached and therefore could be
> > > > wrong.
> > > > So:
> > > >         chip southbridge/intel/i82801ex
> > >
> > > Replace i82801ex with sch, ofcourse.
> > > >          device pci 1f.0 on # lpc bridge
> > > >             chip superio/winbond/w83627hf
> > > >             end # superio
> > > >         end # 1f.0
> > > >
> > > >
> > > >
> > > > > Could someone please explain the devicetree.cb file structure? or
> > > > > point a way?
> > > > >
> > > > > The "lspci -tvnn" output and my modified "devicetree.cb" file are at
> > > > > the attachment.
> > >
> > > Can you show the output from "superiotool -deV"  too? Thanks.
> > > > > Thanks in advance,
> > > > > Alp