this is an initial commit for the PC Engines Alix 1C. It builds. It won't work. 
I want the initial code in the repo, not just on my laptop. 

It also includes some additional posts for geode setup which ought to be useful. 
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Index: mainboard/Kconfig
===================================================================
--- mainboard/Kconfig	(revision 518)
+++ mainboard/Kconfig	(working copy)
@@ -47,12 +47,18 @@
 	help
 	  Select this option for various system emulators, such as QEMU.
 
+config VENDOR_PCENGINES
+	bool "PC Engines"
+	help
+	  Select this option for PC Engines systems
+
 endchoice
 
 source "mainboard/adl/Kconfig"
 source "mainboard/amd/Kconfig"
 source "mainboard/artecgroup/Kconfig"
 source "mainboard/emulation/Kconfig"
+source "mainboard/pcengines/Kconfig"
 
 choice
 	prompt "ROM chip size"
Index: mainboard/pcengines/alix1c/Kconfig
===================================================================
--- mainboard/pcengines/alix1c/Kconfig	(revision 0)
+++ mainboard/pcengines/alix1c/Kconfig	(revision 0)
@@ -0,0 +1,46 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config MAINBOARD_NAME
+	string
+	default pcengines/alix1c
+	depends BOARD_PCENGINES_ALIX1C
+	help
+	  This is the default mainboard name.
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	# TODO: Fix PCI ID.
+	# PC Engines has no PCI vendor ID. Now what?
+	default 0x1022
+	depends BOARD_AMD_NORWICH
+	help
+	  Mainboard specific PCI subsystem vendor ID.
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	# TODO: Fix PCI ID.
+	# PC Engines has no PCI vendor ID. Now what?
+	default 0x2323
+	depends BOARD_AMD_NORWICH
+	help
+	  Mainboard specific PCI subsystem device ID.
+
Index: mainboard/pcengines/alix1c/initram.c
===================================================================
--- mainboard/pcengines/alix1c/initram.c	(revision 0)
+++ mainboard/pcengines/alix1c/initram.c	(revision 0)
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define _MAINOBJECT
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <amd_geodelx.h>
+#include <northbridge/amd/geodelx/raminit.h>
+
+#define MANUALCONF 0		/* Do automatic strapped PLL config */
+#define PLLMSRHI 0x00001490	/* manual settings for the PLL */
+#define PLLMSRLO 0x02000030
+#define DIMM0 ((u8) 0xA0)
+#define DIMM1 ((u8) 0xA2)
+
+
+/**
+  * Place holder in case we ever need it. Since this file is a
+  * template for other motherboards, we want this here and we want the
+  * call in the right place.
+  */
+
+static void mb_gpio_init(void)
+{
+	/* Early mainboard specific GPIO setup */
+}
+
+/** 
+  * main for initram for the PC Engines Alix 1C.  It might seem that you
+  * could somehow do these functions in, e.g., the cpu code, but the
+  * order of operations and what those operations are is VERY strongly
+  * mainboard dependent. It's best to leave it in the mainboard code.
+  */
+int main(void)
+{
+	u8 smb_devices[] =  {
+		DIMM0, DIMM1
+	};
+
+	post_code(POST_START_OF_MAIN);
+
+	system_preinit();
+
+	mb_gpio_init();
+
+	pll_reset(MANUALCONF, PLLMSRHI, PLLMSRLO);
+
+	cpu_reg_init(0, DIMM0, DIMM1);
+
+	sdram_set_registers();
+	sdram_set_spd_registers(DIMM0, DIMM1);
+	sdram_enable(DIMM0, DIMM1);
+	/* Check low memory */
+	/*ram_check(0x00000000, 640*1024); */
+
+	return 0;
+}
Index: mainboard/pcengines/alix1c/stage1.c
===================================================================
--- mainboard/pcengines/alix1c/stage1.c	(revision 0)
+++ mainboard/pcengines/alix1c/stage1.c	(revision 0)
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <amd_geodelx.h>
+#include <southbridge/amd/cs5536/cs5536.h>
+
+void hardware_stage1(void)
+{
+	post_code(POST_START_OF_MAIN);
+	geodelx_msr_init();
+
+	cs5536_stage1();
+
+	/* NOTE: must do this AFTER the early_setup!
+	 * it is counting on some early MSR setup
+	 * for cs5536.
+	 */
+	/* We do this early for debug. 
+	 * real setup should done in chipset init via config.lb 
+	 */
+	cs5536_setup_onchipuart();
+}
Index: mainboard/pcengines/alix1c/dts
===================================================================
--- mainboard/pcengines/alix1c/dts	(revision 0)
+++ mainboard/pcengines/alix1c/dts	(revision 0)
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/{
+	enabled;
+	mainboard-vendor = "PC Engines";
+	mainboard-name = "Alix 1C";
+	cpus {
+		enabled;
+	};
+	domain0 {
+		enabled;
+		pcidomain = "0";
+		device0,0 {
+			enabled;
+			pcipath = "1,0";
+		};
+		southbridge {
+			/config/("southbridge/amd/cs5536");
+			pcipath = "0xf,1";
+			enabled;
+		};
+	};
+};
Index: mainboard/pcengines/alix1c/cmos.layout
===================================================================
--- mainboard/pcengines/alix1c/cmos.layout	(revision 0)
+++ mainboard/pcengines/alix1c/cmos.layout	(revision 0)
@@ -0,0 +1,75 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+440	     1	     e	     0	      dcon_present
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
Index: mainboard/pcengines/alix1c/Makefile
===================================================================
--- mainboard/pcengines/alix1c/Makefile	(revision 0)
+++ mainboard/pcengines/alix1c/Makefile	(revision 0)
@@ -0,0 +1,45 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2006-2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
+
+INITRAM_OBJ =   $(obj)/mainboard/$(MAINBOARDDIR)/initram.o \
+		$(obj)/northbridge/amd/geodelx/raminit.o \
+		$(obj)/southbridge/amd/cs5536/smbus_initram.o \
+		$(obj)/arch/x86/geodelx/geodelx.o
+
+STAGE2_MAINBOARD_OBJ = 
+
+$(obj)/linuxbios.vpd:
+	$(Q)printf "  BUILD   DUMMY VPD\n"
+	$(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
+
+$(obj)/linuxbios.initram $(obj)/linuxbios.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(patsubst %.o,%_xip.o,$(INITRAM_OBJ))
+	$(Q)# initram links against stage0
+	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
+	$(Q)$(LD) --entry main -N -R $(obj)/stage0-prefixed.o \
+		$(patsubst %.o,%_xip.o,$(INITRAM_OBJ)) -o $(obj)/linuxbios.initram.o
+	$(Q)printf "  OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
+	$(Q)$(OBJCOPY) -O binary $(obj)/linuxbios.initram.o \
+		$(obj)/linuxbios.initram
+	$(Q)printf "  NM      $(subst $(shell pwd)/,,$(@))\n"
+	$(Q)$(NM) $(obj)/linuxbios.initram.o | sort -u > $(obj)/linuxbios.initram.map
+
Index: arch/x86/geodelx/stage0.S
===================================================================
--- arch/x86/geodelx/stage0.S	(revision 518)
+++ arch/x86/geodelx/stage0.S	(working copy)
@@ -183,6 +183,7 @@
 	movw	%ax, %fs
 	movw	%ax, %gs
 
+	port80_post(0x02)
 	/* Restore the BIST value to %eax. */
 	movl	%ebp, %eax
 
@@ -193,6 +194,7 @@
 	/* DCacheSetup: Setup data cache for use as RAM for a stack. */
 DCacheSetup:
 	invd
+	port80_post(0x03)
 
 	/* Set cache properties. */
 	movl	$CPU_RCONF_DEFAULT, %ecx
@@ -207,12 +209,14 @@
 	 */
 	movl	$CPU_DM_CONFIG0,%ecx
 	rdmsr
+	port80_post(0x04)
 
 	/* TODO: Make consistent with i$ init, either whole reg = 0, or just
 	 * this bit...
 	 */
 	andl	$(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax
 	wrmsr
+	port80_post(0x05)
 
 	/* Get cache timing params from BIOS config data locations and apply. */
 	/* Fix delay controls for DM and IM arrays. */
@@ -220,27 +224,32 @@
 	xorl	%edx, %edx
 	movl	$0x2814D352, %eax
 	wrmsr
+	port80_post(0x06)
 
 	movl	$CPU_BC_MSS_ARRAY_CTL1, %ecx
 	xorl	%edx, %edx
 	movl	$0x1068334D, %eax
 	wrmsr
+	port80_post(0x07)
 
 	movl	$CPU_BC_MSS_ARRAY_CTL2, %ecx
 	movl	$0x00000106, %edx
 	movl	$0x83104104, %eax
 	wrmsr
+	port80_post(0x08)
 
 	movl	$GLCP_FIFOCTL, %ecx
 	rdmsr
 	movl	$0x00000005, %edx
 	wrmsr
+	port80_post(0x09)
 
 	/* Enable setting. */
 	movl	$CPU_BC_MSS_ARRAY_CTL_ENA, %ecx
 	xorl	%edx, %edx
 	movl	$0x01, %eax
 	wrmsr
+	port80_post(0x0a)
 
 	/* Get cleaned up. */
 	xorl	%edi, %edi
@@ -257,6 +266,7 @@
 	xorl	%eax, %eax
 	movl	$CPU_DC_INDEX, %ecx
 	wrmsr
+	port80_post(0x0b)
 
 	/* Start address for tag of Way0: ebp will hold the incrementing
 	 * address. Don't destroy!
@@ -272,6 +282,7 @@
 	 * the line counter. Don't destroy!
 	 */
 	movl	$LX_NUM_CACHELINES, %edi
+	port80_post(0x0c)
 
 DCacheSetupFillWay:
 	/* Fill with dummy data: zero it so we can tell it from PCI memory
@@ -287,6 +298,7 @@
 	wrmsr
 	decw	%si
 	jnz	DCacheSetup_quadWordLoop
+	port80_post(0x0d)
 
 	/* Set the tag for this line, need to do this for every new cache
 	 * line to validate it!
@@ -298,6 +310,7 @@
 	movl	%ebp, %eax
 	movl	$CPU_DC_TAG, %ecx
 	wrmsr
+	port80_post(0x0e)
 
 	/* Switch to next line. Lines are in bits 10:4. */
 	/* When index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is
@@ -311,6 +324,7 @@
 	 */
 	addl	$0x010, %eax
 	wrmsr
+	port80_post(0x0f)
 
 	decl	%edi
 	jnz	DCacheSetupFillWay
@@ -331,6 +345,7 @@
 	/* Let's be sure: reset line index bits 10:4. */
 	andl	$0xFFFFF80F, %eax
 	wrmsr
+	port80_post(0x11)
 
 	jmp	DCacheSetupFillWay
 
@@ -364,6 +379,8 @@
 	outb	%al, $0x80
 
 DCacheSetupBad:
+        movb    $0xFF, %al
+        outb    %al, $0x80
 	hlt		/* Issues */
 	jmp DCacheSetupBad
 
