Dear coreboot folks,
looking at the coreboot CBMEM console messages board status repository,
you’ll find a lot of truncated preram CBMEM console messages.
Currently the buffer size is 0xc00 – 3 kB, right –, which is too small
for quite some boards. The mainboard *Kabylake LPDDR3 RVP3* overrides
it to 0xd00.
So I am thinking about increasing it , but it’s of course not that
simple, especially as I don’t understand all the implications.
Increasing this buffer reduces amount of available CAR
apparently DDR3 raminit already struggles with the amount of
cachelines available on fam10/15
My first question is, what other downsides are there of increasing the
buffer size? I assume it’s unrelated to resulting usable RAM size, as
RAM sizes nowadays are much, much bigger? So would one megabyte be
reasonable/possible as a goal on boards supporting that?
So if their is consensus that it should be increased, what would a way
be forward? I assume, overriding it per mainboard is not so useful, as
these messages are mostly from the chipset, so it should be chipset
Should that option be moved there?
"arch/x86: Increase preram CBMEM console buffer size"