Well, I'd like to see your code: which memcfg parameters you're using,

among other things. Could you please put it somewhere (e.g.

review.coreboot.org) so that I can take a look?

I have basically just taken the memcfg structure from the Intel Comet Lake reference platform and modified it to use READ_SPD_CBFS.  The structure is currently:

static const struct cnl_mb_cfg memcfg = {
        /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
        .spd[0] = {
                .read_type = READ_SPD_CBFS,
                .spd_spec = {.spd_index = 0},
        },
        .spd[1] = {
                .read_type = READ_SPD_CBFS,
                .spd_spec = {.spd_index = 0},
        },
        .spd[2] = {
                .read_type = READ_SPD_CBFS,
                .spd_spec = {.spd_index = 0},
        },
        .spd[] = {
                .read_type = READ_SPD_CBFS,
                .spd_spec = {.spd_index = 0},
        },

        /*
         * The dqs_map arrays map the ddr4 pins to the SoC pins
         * for both channels.
         *
         * the index = pin number on ddr4 part
         * the value = pin number on SoC
         */
        .dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7},
        .dqs_map[DDR_CH1] = {1, 0, 4, 5, 2, 3, 6, 7},

        /* Baseboard uses 121, 81 and 100 rcomp resistors */
        .rcomp_resistor = {121, 81, 100},

        /*
         * Baseboard Rcomp target values.
         */
        .rcomp_targets = {100, 40, 20, 20, 26},

        /* Baseboard is an interleaved design */
        .dq_pins_interleaved = 1,

        /* Baseboard is using config 2 for vref_ca */
        .vref_ca_config = 2,

        /* Disable Early Command Training */
        .ect = 0,
};

I have a query about the .dqs_map values as I don’t think this hardware matches the Intel reference design in this area.  The hardware has four devices for CH0 and four for CH1.  For CH0 the DQS signals appear to be paired as 0 & 6, 1 & 3, 5 & 2 and 7 & 4.  For CH1 they are paired as 7 & 5, 3 & 6, 2 & 4 and 0 & 1.

-Andy.