Index: src/southbridge/nvidia/ck804/Kconfig =================================================================== --- src/southbridge/nvidia/ck804/Kconfig (Revision 5911) +++ src/southbridge/nvidia/ck804/Kconfig (Arbeitskopie) @@ -16,3 +16,11 @@ hex default 0x98 if SOUTHBRIDGE_NVIDIA_CK804 +config CK804_USE_NIC + bool + default n if SOUTHBRIDGE_NVIDIA_CK804 + +config CK804_USE_ACI + bool + default n if SOUTHBRIDGE_NVIDIA_CK804 + Index: src/southbridge/nvidia/ck804/ck804_early_setup.c =================================================================== --- src/southbridge/nvidia/ck804/ck804_early_setup.c (Revision 5911) +++ src/southbridge/nvidia/ck804/ck804_early_setup.c (Arbeitskopie) @@ -63,14 +63,6 @@ #endif #endif -#ifndef CK804_USE_NIC -#define CK804_USE_NIC 0 -#endif - -#ifndef CK804_USE_ACI -#define CK804_USE_ACI 0 -#endif - #define CK804_CHIP_REV 3 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE @@ -258,7 +250,7 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if CK804_USE_NIC == 1 +#if CONFIG_CK804_USE_NIC RES_PCI_IO, PCI_ADDR(0, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), @@ -266,7 +258,7 @@ RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE + 1 , 0, 0xe4), ~(1 << 23), (1 << 23), #endif -#if CK804_USE_ACI == 1 +#if CONFIG_CK804_USE_ACI RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif @@ -276,7 +268,7 @@ #endif #if CK804_NUM > 1 -#if CK804_USE_NIC == 1 +#if CONFIG_CK804_USE_NIC RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804B_DEVN_BASE +0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), Index: src/southbridge/nvidia/ck804/ck804_early_setup_car.c =================================================================== --- src/southbridge/nvidia/ck804/ck804_early_setup_car.c (Revision 5911) +++ src/southbridge/nvidia/ck804/ck804_early_setup_car.c (Arbeitskopie) @@ -55,14 +55,6 @@ #define CK804B_PCI_E_X 4 #endif -#ifndef CK804_USE_NIC -#define CK804_USE_NIC 0 -#endif - -#ifndef CK804_USE_ACI -#define CK804_USE_ACI 0 -#endif - #define CK804_CHIP_REV 3 #if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE @@ -198,7 +190,7 @@ //SYSCTRL RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 9, ~(0xff), ((0 << 4) | (1 << 2) | (1 << 0)), -#if CK804_USE_NIC == 1 +#if CONFIG_CK804_USE_NIC RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), @@ -206,7 +198,7 @@ RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xe4), ~(1 << 23), (1 << 23), #endif -#if CK804_USE_ACI == 1 +#if CONFIG_CK804_USE_ACI RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x0d, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 0x1a, ~(0xff), ((0 << 4) | (2 << 2) | (0 << 0)), #endif @@ -271,7 +263,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), -#if CK804_USE_NIC == 1 +#if CONFIG_CK804_USE_NIC RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040, RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 19, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 3, ~(0xff), ((0 << 4) | (1 << 2) | (0 << 0)), Index: src/mainboard/tyan/s2895/romstage.c =================================================================== --- src/mainboard/tyan/s2895/romstage.c (Revision 5911) +++ src/mainboard/tyan/s2895/romstage.c (Arbeitskopie) @@ -72,9 +72,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define CK804_USE_NIC 1 -#define CK804_USE_ACI 1 - #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode Index: src/mainboard/msi/ms7135/Kconfig =================================================================== --- src/mainboard/msi/ms7135/Kconfig (Revision 5911) +++ src/mainboard/msi/ms7135/Kconfig (Arbeitskopie) @@ -15,6 +15,8 @@ select HAVE_MP_TABLE select CACHE_AS_RAM select BOARD_ROMSIZE_KB_512 + select CK804_USE_NIC + select CK804_USE_ACI config MAINBOARD_DIR string Index: src/mainboard/msi/ms7135/romstage.c =================================================================== --- src/mainboard/msi/ms7135/romstage.c (Revision 5911) +++ src/mainboard/msi/ms7135/romstage.c (Arbeitskopie) @@ -43,10 +43,6 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -/* Used by ck804_early_setup(). */ -#define CK804_USE_NIC 1 -#define CK804_USE_ACI 1 - #include #include #include "northbridge/amd/amdk8/incoherent_ht.c" Index: src/mainboard/sunw/ultra40/Kconfig =================================================================== --- src/mainboard/sunw/ultra40/Kconfig (Revision 5911) +++ src/mainboard/sunw/ultra40/Kconfig (Arbeitskopie) @@ -14,6 +14,8 @@ select HAVE_MP_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 + select CK804_USE_NIC + select CK804_USE_ACI config MAINBOARD_DIR string Index: src/mainboard/sunw/ultra40/romstage.c =================================================================== --- src/mainboard/sunw/ultra40/romstage.c (Revision 5911) +++ src/mainboard/sunw/ultra40/romstage.c (Arbeitskopie) @@ -78,9 +78,6 @@ #include "cpu/amd/dualcore/dualcore.c" -#define CK804_USE_NIC 1 -#define CK804_USE_ACI 1 - #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" //set GPIO to input mode