Signed-off-by: Oskar Enoksson <oskeno@foi.se>
Index: src/mainboard/hp/Kconfig
===================================================================
--- src/mainboard/hp/Kconfig	(revision 5719)
+++ src/mainboard/hp/Kconfig	(working copy)
@@ -2,6 +2,7 @@
 	prompt "Mainboard model"
 	depends on VENDOR_HP
 
+source "src/mainboard/hp/dl145_g1/Kconfig"
 source "src/mainboard/hp/dl145_g3/Kconfig"
 source "src/mainboard/hp/e_vectra_p2706t/Kconfig"
 
Index: src/mainboard/hp/dl145_g1/Kconfig
===================================================================
--- src/mainboard/hp/dl145_g1/Kconfig	(revision 5719)
+++ src/mainboard/hp/dl145_g1/Kconfig	(working copy)
@@ -1,5 +1,5 @@
-config BOARD_TYAN_S2881
-	bool "S2881 (Thunder K8SR)"
+config BOARD_HP_DL145_G1
+	bool "ProLiant DL145 G1"
 	select ARCH_X86
 	select CPU_AMD_SOCKET_940
 	select NORTHBRIDGE_AMD_AMDK8
@@ -13,65 +13,69 @@
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
-	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	select DRIVERS_SIL_3114
+#	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
 
 config MAINBOARD_DIR
 	string
-	default tyan/s2881
-	depends on BOARD_TYAN_S2881
+	default hp/dl145_g1
+	depends on BOARD_HP_DL145_G1
 
 config APIC_ID_OFFSET
 	hex
 	default 0x0
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config SB_HT_CHAIN_ON_BUS0
 	int
 	default 2
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "S2881"
-	depends on BOARD_TYAN_S2881
+	default "ProLiant DL145 G1"
+	depends on BOARD_HP_DL145_G1
 
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1022
+	depends on BOARD_HP_DL145_G1
+
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
 	hex
-	default 0x2881
-	depends on BOARD_TYAN_S2881
+	default 0x7460
+	depends on BOARD_HP_DL145_G1
 
 config HW_MEM_HOLE_SIZEK
 	hex
 	default 0x100000
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config MAX_CPUS
 	int
 	default 4
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config MAX_PHYSICAL_CPUS
 	int
 	default 2
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
 	bool
 	default n
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config HT_CHAIN_UNITID_BASE
 	hex
-	default 0xa
-	depends on BOARD_TYAN_S2881
+	default 0x1
+	depends on BOARD_HP_DL145_G1
 
 config HT_CHAIN_END_UNITID_BASE
 	hex
 	default 0x6
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
 
 config IRQ_SLOT_COUNT
 	int
 	default 9
-	depends on BOARD_TYAN_S2881
+	depends on BOARD_HP_DL145_G1
Index: src/mainboard/hp/dl145_g1/devicetree.cb
===================================================================
--- src/mainboard/hp/dl145_g1/devicetree.cb	(revision 5719)
+++ src/mainboard/hp/dl145_g1/devicetree.cb	(working copy)
@@ -11,30 +11,29 @@
       device pci 18.0 on     # link 2
         chip southbridge/amd/amd8131
           # the on/off keyword is mandatory
-          device pci 0.0 on
-            device pci 9.0 on end # Broadcom 5704
-            device pci 9.1 on end
-            device pci a.0 on end # Adaptic
-            device pci a.1 on end
-          end
+          device pci 0.0 on end
           device pci 0.1 on end
           device pci 1.0 on end
           device pci 1.1 on end
+          device pci 2.0 on end
+          device pci 2.1 on end
+          device pci 3.0 off end
         end
         chip southbridge/amd/amd8111
           # this "device pci 0.0" is the parent the next one
           # PCI bridge
           device pci 0.0 on
-            device pci 0.0 on end
-            device pci 0.1 on end
-            device pci 0.2 off end
+            device pci 0.0 on end # LPC
+            device pci 0.1 on end # IDE
+            device pci 0.2 on end # SMbus
+            device pci 0.3 on end # ACPI
             device pci 1.0 off end
-            device pci 5.0 on end # SiI
-            device pci 6.0 on end
+            #device pci 5.0 on end # SiI
+            #device pci 6.0 on end
           end
           device pci 1.0 on
             chip superio/winbond/w83627hf
-              device pnp 2e.0 on  # Floppy
+              device pnp 2e.0 off # Floppy
                 io  0x60 = 0x3f0
                 irq 0x70 = 6
                 drq 0x74 = 2
@@ -42,12 +41,13 @@
               device pnp 2e.1 off # Parallel Port
                 io  0x60 = 0x378
                 irq 0x70 = 7
+                drq 0x74 = 1
               end
               device pnp 2e.2 on  # Com1
                 io  0x60 = 0x3f8
                 irq 0x70 = 4
               end
-              device pnp 2e.3 off # Com2
+              device pnp 2e.3 on  # Com2
                 io  0x60 = 0x2f8
                 irq 0x70 = 3
               end
@@ -58,17 +58,19 @@
                 irq 0x72 = 12
               end
               device pnp 2e.6 off # CIR
-                io  0x60 = 0x100
               end
-              device pnp 2e.7 off # GAME_MIDI_GIPO1
-                io  0x60 = 0x220
-                io  0x62 = 0x300
+              device pnp 2e.7 off # GAM_MIDI_GIPO1
+                io  0x60 = 0x201
+                io  0x62 = 0x330
                 irq 0x70 = 9
               end
-              device pnp 2e.8 off end # GPIO2
-              device pnp 2e.9 off end # GPIO3
-              device pnp 2e.a off end # ACPI
-              device pnp 2e.b on      # HW Monitor
+              device pnp 2e.8 on  # GPIO2
+              end
+              device pnp 2e.9 on  # GPIO3
+              end
+              device pnp 2e.a on  # ACPI
+              end
+              device pnp 2e.b on  # HW Monitor
                 io  0x60 = 0x290
                 irq 0x70 = 5
               end
@@ -77,49 +79,76 @@
           device pci 1.1 on end
           device pci 1.2 on end
           device pci 1.3 on
-            chip drivers/generic/generic #dimm 0-0-0
-              device i2c 50 on end
+            chip drivers/generic/generic # ???
+              device i2c 08 on end
             end
-            chip drivers/generic/generic #dimm 0-0-1
-              device i2c 51 on end
+            chip drivers/i2c/i2cmux # pca9556 smbus mux
+              device i2c 18 on #0 pca9516 1
+                # I don't know what 30-33 are for,
+                # they seem to have something to do with the DIMM's
+                chip drivers/generic/generic # ???
+                  device i2c 30 on end
+                end
+                chip drivers/generic/generic # ???
+                  device i2c 31 on end
+                end
+                chip drivers/generic/generic # ???
+                  device i2c 32 on end
+                end
+                chip drivers/generic/generic # ???
+                  device i2c 33 on end
+                end
+                chip drivers/generic/generic #dimm H0-0
+                  device i2c 50 on end
+                end
+                chip drivers/generic/generic #dimm H0-1
+                  device i2c 51 on end
+                end
+                chip drivers/generic/generic #dimm H0-2
+                  device i2c 52 on end
+                end
+                chip drivers/generic/generic #dimm H0-3
+                  device i2c 53 on end
+                end
+              end
+              device i2c 18 on #1 pca9516 2
+                chip drivers/generic/generic # ???
+                  device i2c 30 on end
+                end
+                chip drivers/generic/generic # ???
+                  device i2c 31 on end
+                end
+                chip drivers/generic/generic # ???
+                  device i2c 32 on end
+                end
+                chip drivers/generic/generic # ???
+                  device i2c 33 on end
+                end
+                chip drivers/generic/generic #dimm H1-0
+                  device i2c 50 on end
+                end
+                chip drivers/generic/generic #dimm H1-1
+                  device i2c 51 on end
+                end
+                chip drivers/generic/generic #dimm H1-2
+                  device i2c 52 on end
+                end
+                chip drivers/generic/generic #dimm H1-3
+                  device i2c 53 on end
+                end
+              end
             end
-            chip drivers/generic/generic #dimm 0-1-0
-              device i2c 52 on end
+            chip drivers/generic/generic # ???
+              device i2c 69 on end
             end
-            chip drivers/generic/generic #dimm 0-1-1
-              device i2c 53 on end
-            end
-            chip drivers/generic/generic #dimm 1-0-0
-              device i2c 54 on end
-            end
-            chip drivers/generic/generic #dimm 1-0-1
-              device i2c 55 on end
-            end
-            chip drivers/generic/generic #dimm 1-1-0
-              device i2c 56 on end
-            end
-            chip drivers/generic/generic #dimm 1-1-1
-              device i2c 57 on end
-            end
-            chip drivers/i2c/adt7463 # CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3
-              device i2c 2d on end
-            end
-            chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN
-              device i2c 2a on end
-            end
-            chip drivers/generic/generic # Winbond HWM 0x92
-              device i2c 49 on end
-            end
-            chip drivers/generic/generic # Winbond HWM 0x94
-              device i2c 4a on end
-            end
           end # acpi
-          device pci 1.5 off end
-          device pci 1.6 off end
+          device pci 1.4 off end
+          device pci 1.5 off end # AC97 Audio
+          device pci 1.6 off end # MC97 Modem
           register "ide0_enable" = "1"
           register "ide1_enable" = "1"
         end
-      end #  device pci 18.0
+      end #  device pci 18.0                       
       device pci 18.1 on end
       device pci 18.2 on end
       device pci 18.3 on end
Index: src/mainboard/hp/dl145_g1/romstage.c
===================================================================
--- src/mainboard/hp/dl145_g1/romstage.c	(revision 5719)
+++ src/mainboard/hp/dl145_g1/romstage.c	(working copy)
@@ -40,28 +40,54 @@
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
+      /* Set the memreset low */
+      outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+      /* Ensure the BIOS has control of the memory lines */
+      outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+   } else {
+      /* Ensure the CPU has controll of the memory lines */
+      outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
    }
-   else {
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-   }
-        outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
    if (is_cpu_pre_c0()) {
-        udelay(800);
-        outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-        udelay(90);
+      udelay(800);
+      /* Set memreset_high */
+      outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+      udelay(90);
    }
 }
 
+#define SMBUS_HUB 0x18
+
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
-	/* nothing to do */
+  int ret,i;
+  unsigned device=(ctrl->channel0[0])>>8;
+  /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
+  i=2;
+  do {
+    ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
+  } while ((ret!=0) && (i-->0));
+  
+  smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
 
+static inline void change_i2c_mux(unsigned device)
+{
+  int ret, i;
+  print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
+  i=2;
+  do {
+    ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
+    print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
+  } while ((ret!=0) && (i-->0));
+  ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
+  print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
+}
+
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -69,12 +95,19 @@
 
 #include "northbridge/amd/amdk8/raminit.c"
 #include "resourcemap.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
 
+#define RC0 ((1<<1)<<8) // Not sure about these values
+#define RC1 ((1<<2)<<8) // Not sure about these values
 
+#define DIMM0 0x50
+#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
 
 #include "cpu/amd/car/post_cache_as_ram.c"
 
@@ -83,14 +116,17 @@
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
-			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
-			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
+			//first node
+                        RC0|DIMM0, RC0|DIMM2, 0, 0,
+                        RC0|DIMM1, RC0|DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
-			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
+			//second node
+                        RC1|DIMM0, RC1|DIMM2, 0, 0,
+                        RC1|DIMM1, RC1|DIMM3, 0, 0,
 #endif
 	};
 
@@ -123,11 +159,8 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-        setup_s2881_resource_map();
-#if 0
-        dump_pci_device(PCI_DEV(0, 0x18, 0));
-	dump_pci_device(PCI_DEV(0, 0x19, 0));
-#endif
+        setup_dl145g1_resource_map();
+        //setup_default_resource_map();
 
 	needs_reset = setup_coherent_ht_domain();
 
@@ -146,13 +179,19 @@
        	}
 
 	enable_smbus();
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-#if 0
-	dump_smbus_registers();
-#endif
 
+	int i;
+	for(i=0;i<2;i++) {
+		activate_spd_rom(&ctrl[i]);
+	}
+        for(i=2;i<8;i<<=1) {
+                change_i2c_mux(i);
+        }
+
+        //dump_spd_registers(&ctrl[0]);
+        //dump_spd_registers(&ctrl[1]);
+	//dump_smbus_registers();
+
         allow_all_aps_stop(bsp_apicid);
 
         nodes = get_nodes();
@@ -162,10 +201,7 @@
         memreset_setup();
         sdram_initialize(nodes, ctrl);
 
-#if 0
-	dump_pci_devices();
-#endif
+	//dump_pci_devices();
 
 	post_cache_as_ram();
 }
-
Index: src/mainboard/hp/dl145_g1/Makefile.inc
===================================================================
--- src/mainboard/hp/dl145_g1/Makefile.inc	(revision 5719)
+++ src/mainboard/hp/dl145_g1/Makefile.inc	(working copy)
@@ -1 +1 @@
-obj-y += ../../../drivers/i2c/adt7463/adt7463.o
+obj-y += ../../../drivers/i2c/i2cmux/i2cmux.o
\ No newline at end of file
Index: src/mainboard/hp/dl145_g1/mptable.c
===================================================================
--- src/mainboard/hp/dl145_g1/mptable.c	(revision 5719)
+++ src/mainboard/hp/dl145_g1/mptable.c	(working copy)
@@ -24,7 +24,7 @@
 {
         static const char sig[4] = "PCMP";
         static const char oem[8] = "COREBOOT";
-        static const char productid[12] = "S2881       ";
+        static const char productid[12] = "DL145G1     ";
         struct mp_config_table *mc;
 
         unsigned char bus_num;
@@ -62,7 +62,7 @@
 
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
-	smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
+	smp_write_ioapic(mc, apicid_8111, 0x20, 0xfec00000);
         {
                 device_t dev;
                 struct resource *res;
@@ -70,14 +70,14 @@
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
-                                smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
+                                smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
                         }
                 }
                 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
                 if (dev) {
                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
                         if (res) {
-                                smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
+                                smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
                         }
                 }
 
@@ -85,43 +85,32 @@
 
 	mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
 
+	//
+	// The out-commented lines are auto-detected on my servers,
+	//
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-//8111 LPC ????
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13);
+	// Integrated SMBus 2.0
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111  , 0x15);
+	// Integrated AMD AC97 Audio
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111  , 0x11);
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111  , 0x12);
+	// Integrated AMD USB
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111  , 0x10);
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111  , 0x13);
+	// On board ATI Rage XL
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111  , 0x14);
+	// On board Broadcom nics
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
+	// On board LSI SCSI
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
 
-//On Board AMD USB ???
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
+	// PCIX-133 Slot
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01);
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
 
-//On Board ATI Display Adapter
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
-
-//On Board SI Serial ATA
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
-
-//Slot 3 PCIX 100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
-        }
-
-//On Board NIC and adaptec scsi
-        for(i=0;i<2;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|i, apicid_8131_1, (0+i)%4); //24
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (0+i)%4); //24
-        }
-
-//Slot 1 PCI-X 133/100/66 or Side 1 on raiser card
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
-        }
-
-        //Slot 1 PCI-X 133/100/66, Side 2 on raiser card
-        //Fix ME, IRQ Pins?
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (1+i)%4); //28
-        }
-
-
-
 /*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
 	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
Index: src/mainboard/hp/dl145_g1/resourcemap.c
===================================================================
--- src/mainboard/hp/dl145_g1/resourcemap.c	(revision 5719)
+++ src/mainboard/hp/dl145_g1/resourcemap.c	(working copy)
@@ -1,9 +1,9 @@
 /*
- * Tyan S2881 needs a different resource map
- *
+ * DL145G1 needs a different resource map
+ * This file may need more tweaking, it is copied from the Tyan S2881 mainboard
  */
 
-static void setup_s2881_resource_map(void)
+static void setup_dl145g1_resource_map(void)
 {
 	static const unsigned int register_values[] = {
 	/* Careful set limit registers before base registers which contain the enables */
@@ -117,7 +117,8 @@
 	PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+	//PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000b20,
 	PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
 
@@ -152,7 +153,8 @@
 	PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
-	PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+	//PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000a03,
 	PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
 
@@ -252,8 +254,8 @@
 	 * [31:24] Bus Number Limit i
 	 *	   This field defines the highest bus number in configuration regin i
 	 */
-//	PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203,
-//	PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
+	PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203,
+	PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
 	PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
 	};
Index: src/mainboard/hp/dl145_g1/mainboard.c
===================================================================
--- src/mainboard/hp/dl145_g1/mainboard.c	(revision 5719)
+++ src/mainboard/hp/dl145_g1/mainboard.c	(working copy)
@@ -4,6 +4,7 @@
  * Copyright (C) 2005 Tyan
  * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
  * Copyright (C) 2007 Ward Vandewege <ward@gnu.org>
+ * Copyright (C) 2010 FOI Oskar Enoksson <oskeno@foi.se>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -24,5 +25,5 @@
 #include "chip.h"
 
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("Tyan S2881 Mainboard")
+	CHIP_NAME("HP DL145G1 Mainboard")
 };
