Index: cbv2/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- cbv2.orig/src/northbridge/amd/amdk8/northbridge.c
+++ cbv2/src/northbridge/amd/amdk8/northbridge.c
@@ -36,56 +36,38 @@
 
 struct amdk8_sysconf_t sysconf;
 
-#define FX_DEVS 8
-static device_t __f0_dev[FX_DEVS];
-static device_t __f1_dev[FX_DEVS];
-
-#if 0
-static void debug_fx_devs(void)
-{
-	int i;
-	for(i = 0; i < FX_DEVS; i++) {
-		device_t dev;
-		dev = __f0_dev[i];
-		if (dev) {
-			printk_debug("__f0_dev[%d]: %s bus: %p\n",
-				i, dev_path(dev), dev->bus);
-		}
-		dev = __f1_dev[i];
-		if (dev) {
-			printk_debug("__f1_dev[%d]: %s bus: %p\n",
-				i, dev_path(dev), dev->bus);
-		}
-	}
-}
-#endif
+#define MAX_FX_DEVS 8
+static device_t __f0_dev[MAX_FX_DEVS];
+static device_t __f1_dev[MAX_FX_DEVS];
+static unsigned fx_devs=0;
 
 static void get_fx_devs(void)
 {
 	int i;
-	if (__f1_dev[0]) {
-		return;
-	}
-	for(i = 0; i < FX_DEVS; i++) {
+	for(i = 0; i < MAX_FX_DEVS; i++) {
 		__f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
 		__f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
+		if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
+			fx_devs = i+1;
 	}
-	if (!__f1_dev[0]) {
-		die("Cannot find 0:0x18.1\n");
+	if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
+		die("Cannot find 0:0x18.[0|1]\n");
 	}
 }
 
 static uint32_t f1_read_config32(unsigned reg)
 {
-	get_fx_devs();
+	if ( fx_devs == 0)
+		get_fx_devs();
 	return pci_read_config32(__f1_dev[0], reg);
 }
 
 static void f1_write_config32(unsigned reg, uint32_t value)
 {
 	int i;
-	get_fx_devs();
-	for(i = 0; i < FX_DEVS; i++) {
+	if ( fx_devs == 0)
+		get_fx_devs();
+	for(i = 0; i < fx_devs; i++) {
 		device_t dev;
 		dev = __f1_dev[i];
 		if (dev && dev->enabled) {
@@ -291,7 +273,7 @@ static int reg_useable(unsigned reg,
 	unsigned nodeid, link=0;
 	int result;
 	res = 0;
-	for(nodeid = 0; !res && (nodeid < FX_DEVS); nodeid++) {
+	for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
 		device_t dev;
 		dev = __f0_dev[nodeid];
 		if (!dev)
@@ -634,7 +616,6 @@ struct chip_operations northbridge_amd_a
 
 static void amdk8_domain_read_resources(device_t dev)
 {
-	struct resource *resource;
 	unsigned reg;
 
 	/* Find the already assigned resource pairs */
@@ -652,10 +633,10 @@ static void amdk8_domain_read_resources(
 			reg_dev = __f0_dev[nodeid];
 			if (reg_dev) {
 				/* Reserve the resource  */
-				struct resource *reg_resource;
-				reg_resource = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
-				if (reg_resource) {
-					reg_resource->flags = 1;
+				struct resource *res;
+				res = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
+				if (res) {
+					res->flags = 1;
 				}
 			}
 		}
@@ -725,15 +706,14 @@ static struct hw_mem_hole_info get_hw_me
 		mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
 		mem_hole.node_id = -1;
 
-		for (i = 0; i < FX_DEVS; i++) {
+		for (i = 0; i < fx_devs; i++) {
 			uint32_t base;
 			uint32_t hole;
 			base  = f1_read_config32(0x40 + (i << 3));
 			if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 				continue;
 			}
-			if (!__f1_dev[i])
-				continue;
+
 			hole = pci_read_config32(__f1_dev[i], 0xf0);
 			if(hole & 1) { // we find the hole
 				mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
@@ -769,9 +749,10 @@ static struct hw_mem_hole_info get_hw_me
 		return mem_hole;
 
 }
-static void disable_hoist_memory(unsigned long hole_startk, int i)
+
+static void disable_hoist_memory(unsigned long hole_startk, int node_id)
 {
-	int ii;
+	int i;
 	device_t dev;
 	uint32_t base, limit;
 	uint32_t hoist;
@@ -787,33 +768,35 @@ static void disable_hoist_memory(unsigne
 
 	hole_sizek = (4*1024*1024) - hole_startk;
 
-	for(ii=7;ii>i;ii--) {
+	for(i=7;i>node_id;i--) {
 
-		base  = f1_read_config32(0x40 + (ii << 3));
+		base  = f1_read_config32(0x40 + (i << 3));
 		if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 			continue;
 		}
-		limit = f1_read_config32(0x44 + (ii << 3));
-		f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
-		f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
+		limit = f1_read_config32(0x44 + (i << 3));
+		f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
+		f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
 	}
-	limit = f1_read_config32(0x44 + (i << 3));
-	f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
-	dev = __f1_dev[i];
-	if (dev) {
-		hoist = pci_read_config32(dev, 0xf0);
-		if(hoist & 1) {
-			pci_write_config32(dev, 0xf0, 0);
-		} else {
-			base = pci_read_config32(dev, 0x40 + (i << 3));
-			f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
-		}
+	limit = f1_read_config32(0x44 + (node_id << 3));
+	f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
+	dev = __f1_dev[node_id];
+	if (dev == NULL) {
+		printk_err("%s: node %x is NULL!\n", __func__, node_id);
+		return;
+	}
+	hoist = pci_read_config32(dev, 0xf0);
+	if(hoist & 1)
+		pci_write_config32(dev, 0xf0, 0);
+	else {
+		base = pci_read_config32(dev, 0x40 + (node_id << 3));
+		f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
 	}
 }
 
-static uint32_t hoist_memory(unsigned long hole_startk, int i)
+static uint32_t hoist_memory(unsigned long hole_startk, int node_id)
 {
-	int ii;
+	int i;
 	uint32_t carry_over;
 	device_t dev;
 	uint32_t base, limit;
@@ -822,27 +805,27 @@ static uint32_t hoist_memory(unsigned lo
 
 	carry_over = (4*1024*1024) - hole_startk;
 
-	for(ii=7;ii>i;ii--) {
+	for(i=7;i>node_id;i--) {
 
-		base  = f1_read_config32(0x40 + (ii << 3));
+		base  = f1_read_config32(0x40 + (i << 3));
 		if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
 			continue;
 		}
-		limit = f1_read_config32(0x44 + (ii << 3));
-		f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
-		f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
-	}
-	limit = f1_read_config32(0x44 + (i << 3));
-	f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
-	dev = __f1_dev[i];
-	base  = pci_read_config32(dev, 0x40 + (i << 3));
+		limit = f1_read_config32(0x44 + (i << 3));
+		f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
+		f1_write_config32(0x40 + (i << 3),base + (carry_over << 2));
+	}
+	limit = f1_read_config32(0x44 + (node_id << 3));
+	f1_write_config32(0x44 + (node_id << 3),limit + (carry_over << 2));
+	dev = __f1_dev[node_id];
+	base  = pci_read_config32(dev, 0x40 + (node_id << 3));
 	basek  = (base & 0xffff0000) >> 2;
 	if(basek == hole_startk) {
 		//don't need set memhole here, because hole off set will be 0, overflow
 		//so need to change base reg instead, new basek will be 4*1024*1024
 		base &= 0x0000ffff;
 		base |= (4*1024*1024)<<2;
-		f1_write_config32(0x40 + (i<<3), base);
+		f1_write_config32(0x40 + (node_id<<3), base);
 	}
 	else if (dev)
 	{
@@ -980,7 +963,7 @@ static void amdk8_domain_set_resources(d
 		#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
 			//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
 			uint32_t basek_pri;
-			for (i = 0; i < FX_DEVS; i++) {
+			for (i = 0; i < fx_devs; i++) {
 				uint32_t base;
 				uint32_t basek;
 				base  = f1_read_config32(0x40 + (i << 3));
@@ -1005,7 +988,7 @@ static void amdk8_domain_set_resources(d
 #endif
 
 	idx = 0x10;
-	for(i = 0; i < FX_DEVS; i++) {
+	for(i = 0; i < fx_devs; i++) {
 		uint32_t base, limit;
 		unsigned basek, limitk, sizek;
 		base  = f1_read_config32(0x40 + (i << 3));
@@ -1100,7 +1083,7 @@ static unsigned int amdk8_domain_scan_bu
 	 * Including enabling relaxed ordering if it is safe.
 	 */
 	get_fx_devs();
-	for(i = 0; i < FX_DEVS; i++) {
+	for(i = 0; i < fx_devs; i++) {
 		device_t f0_dev;
 		f0_dev = __f0_dev[i];
 		if (f0_dev && f0_dev->enabled) {
