Uwe Hermann wrote:
Actually, scratch that. It seems intel/car/cache_as_ram.inc hardcodes the base to:
#define CacheBase (0xd0000 - CacheSize)
I.e. the DCACHE_RAM_BASE option is never used for this CAR implementation. We have multiple possibilities to fix this:
- Drop DCACHE_RAM_BASE for these CPUs/sockets, and leave in the hardcoded CacheBase, which means all of them will use the same base.
I think this is the right thing to do, at least for now. Maybe hardcode cache size too.
And by "for now" I mean "until someone investigates the CAR situation on all affected CPUs".
//Peter