diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/arch/i386/boot/pirq_routing.c LinuxBIOSv2/src/arch/i386/boot/pirq_routing.c
--- LinuxBIOSv2.orig/src/arch/i386/boot/pirq_routing.c	2006-02-24 10:33:50.000000000 +0100
+++ LinuxBIOSv2/src/arch/i386/boot/pirq_routing.c	2006-02-21 18:24:11.000000000 +0100
@@ -90,7 +90,8 @@
 	addr &= ~15;
 
 	/* This table must be betweeen 0xf0000 & 0x100000 */
-	printk_info("Copying IRQ routing tables to 0x%x...", addr);
+	printk_info("Copying IRQ routing tables from 0x%x to 0x%x size 0x%x...",
+		&intel_irq_routing_table, addr, intel_irq_routing_table.size);
 	memcpy((void *)addr, &intel_irq_routing_table, intel_irq_routing_table.size);
 	printk_info("done.\n");
 	verify_copy_pirq_routing_table(addr);
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/arch/i386/lib/cpu.c LinuxBIOSv2/src/arch/i386/lib/cpu.c
--- LinuxBIOSv2.orig/src/arch/i386/lib/cpu.c	2006-02-24 10:33:51.000000000 +0100
+++ LinuxBIOSv2/src/arch/i386/lib/cpu.c	2006-02-21 18:24:11.000000000 +0100
@@ -231,6 +231,8 @@
 		die("CPU: missing cpu device structure");
 	}
 
+
+
 	// Check that we haven't been passed bad information as the result of a race 
 	// (i.e. BSP timed out while waiting for us to load secondary_stack)
 
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/cpu/amd/model_gx1/cpu_setup.inc LinuxBIOSv2/src/cpu/amd/model_gx1/cpu_setup.inc
--- LinuxBIOSv2.orig/src/cpu/amd/model_gx1/cpu_setup.inc	2006-02-24 10:33:40.000000000 +0100
+++ LinuxBIOSv2/src/cpu/amd/model_gx1/cpu_setup.inc	2006-02-21 18:24:11.000000000 +0100
@@ -9,6 +9,7 @@
 /* USES: esi, ecx, eax */
 
 #include <cpu/amd/gx1def.h>
+	intel_chip_post_macro(0x19)
 
 	movl %eax, %ebp /* preserve bist */
 
@@ -24,32 +25,6 @@
 	outb	%al, $0x23
 	loop	cpu_setup_loop
 
-	movb	$0xff, %al		/* DIR1 -- Identification Register 1 */
-	outb	%al, $0x22
-	inb	$0x23, %al
-	cmpb	$0x63, %al		/* Revision for GXLV rev 3 */
-	jbe	cpu_no_ccr4
-
-	movb	$0xe8, %al		/* CCR4 */
-	outb	%al, $0x22
-	inb	$0x23, %al
-	orb	$0x20, %al		/* Enable FPU Fast Mode */
-	outb	%al, $0x23
-
-	movb	$0xf0, %al		/* PCR1 --- Performace Control  */
-	outb	%al, $0x22
-	inb	$0x23, %al
-	orb	$0x02, %al		/* Incrementor on, whatever that is */
-	outb	%al, $0x23
-
-	movb	$0x20, %al		/* PCR0 --- Performace Control  */
-	outb	%al, $0x22
-	inb	$0x23, %al
-	orb	$0x20, %al		/* Must be 1 according to data book */
-	orb	$0x04, %al		/* Incrementor Margin 10 */
-	outb	%al, $0x23
-cpu_no_ccr4:
-
 	jmp	cpu_setup_end
 
 cpu_setup_table:
@@ -58,7 +33,10 @@
 	.byte	0x20, 0x00
 	.byte	0xb8, GX_BASE>>30	/* Enable GXBASE address */
 	.byte	0xc2, 0x00
-	.byte	0xe8, 0x98
+	.byte	0xe8, 0xf8		// enable fast FPU mode
+//	.byte	0xeb, 0x01		// enable EMMX
+	.byte	0xf0, 0x03		// enable incrementor
+	.byte	0x20, 0x24		// set incrementor margins
 	.byte	0xc3, 0xf8		/* Enable CPU config register */
 cpu_setup_len = (.-cpu_setup_table)/2
 
@@ -66,3 +44,4 @@
 	nop
 
 	movl %ebp, %eax	/* Restore bist */
+	intel_chip_post_macro(0x20)
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/cpu/amd/model_gx1/gx_setup.inc LinuxBIOSv2/src/cpu/amd/model_gx1/gx_setup.inc
--- LinuxBIOSv2.orig/src/cpu/amd/model_gx1/gx_setup.inc	2006-02-24 10:33:40.000000000 +0100
+++ LinuxBIOSv2/src/cpu/amd/model_gx1/gx_setup.inc	2006-02-21 18:24:11.000000000 +0100
@@ -7,6 +7,7 @@
 */
 
 #include <cpu/amd/gx1def.h>
+	intel_chip_post_macro(0x21)
 
 	movl %eax, %ebp /* Preserve bist */
 
@@ -45,3 +46,4 @@
 	nop
 
 	movl %ebp, %eax	/* Restore bist */
+	intel_chip_post_macro(0x22)
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/cpu/amd/model_gx1/model_gx1_init.c LinuxBIOSv2/src/cpu/amd/model_gx1/model_gx1_init.c
--- LinuxBIOSv2.orig/src/cpu/amd/model_gx1/model_gx1_init.c	2006-02-24 10:33:40.000000000 +0100
+++ LinuxBIOSv2/src/cpu/amd/model_gx1/model_gx1_init.c	2006-02-21 18:24:11.000000000 +0100
@@ -92,6 +92,7 @@
 
 static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_CYRIX, 0x0540 },
+	{ X86_VENDOR_NSC,   0x0540 },
 	{ 0, 0 },
 };
 
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/cpu/x86/fpu/enable_fpu.inc LinuxBIOSv2/src/cpu/x86/fpu/enable_fpu.inc
--- LinuxBIOSv2.orig/src/cpu/x86/fpu/enable_fpu.inc	2006-02-24 10:33:41.000000000 +0100
+++ LinuxBIOSv2/src/cpu/x86/fpu/enable_fpu.inc	2006-02-21 18:24:11.000000000 +0100
@@ -1,5 +1,7 @@
 	/* preserve BIST in %eax */
 __fpu_start:
+	intel_chip_post_macro(0x17)
+
 	movl %eax, %ebp
 
 	/* Disable floating point emulation */
@@ -8,3 +10,4 @@
 	movl	%eax, %cr0
 
 	movl %ebp, %eax
+	intel_chip_post_macro(0x18)
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/cpu/x86/lapic/lapic.c LinuxBIOSv2/src/cpu/x86/lapic/lapic.c
--- LinuxBIOSv2.orig/src/cpu/x86/lapic/lapic.c	2006-02-24 10:33:41.000000000 +0100
+++ LinuxBIOSv2/src/cpu/x86/lapic/lapic.c	2006-02-21 18:24:11.000000000 +0100
@@ -58,6 +58,7 @@
 	printk_debug(" apic_id: %d ", lapicid());
 
 #else /* !NEED_LLAPIC */
+#if 0
 	/* Only Pentium Pro and later have those MSR stuff */
 	msr_t msr;
 
@@ -66,6 +67,7 @@
 	msr = rdmsr(LAPIC_BASE_MSR);
 	msr.lo &= ~LAPIC_BASE_MSR_ENABLE;
 	wrmsr(LAPIC_BASE_MSR, msr);
+#endif
 #endif /* !NEED_LAPIC */
 	printk_info("done.\n");
 	post_code(0x9b);
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/devices/pci_device.c LinuxBIOSv2/src/devices/pci_device.c
--- LinuxBIOSv2.orig/src/devices/pci_device.c	2006-02-24 10:33:39.000000000 +0100
+++ LinuxBIOSv2/src/devices/pci_device.c	2006-03-31 10:31:22.000000000 +0200
@@ -532,7 +532,9 @@
 		printk_err("ERROR: invalid resource->index %x\n",
 			resource->index);
 	}
+
 	report_resource_stored(dev, resource, "");
+
 	return;
 }
 
@@ -645,6 +647,15 @@
 
 	run_bios(dev, ram);
 #endif
+
+	// special general pci slot hack for SC2200
+	if ((PCI_SLOT(dev->path.u.pci.devfn) == 0x11) && (PCI_FUNC(dev->path.u.pci.devfn) == 0)) {
+		pci_write_config8(dev, 0x3c, 0x0A); // IRQ12
+		pci_write_config8(dev, 0x3d, 0x01); // use PCI INTB#
+		printk_debug("%s: SC2200 special hack for %02x:%02x:%02x\n", __FUNCTION__,
+			0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+	}
+
 }
 
 /** Default device operation for PCI devices */
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/include/device/pci_ids.h LinuxBIOSv2/src/include/device/pci_ids.h
--- LinuxBIOSv2.orig/src/include/device/pci_ids.h	2006-02-24 10:33:40.000000000 +0100
+++ LinuxBIOSv2/src/include/device/pci_ids.h	2006-02-21 18:24:11.000000000 +0100
@@ -133,6 +133,7 @@
 #define PCI_DEVICE_ID_COMPAQ_1280	0x3033
 #define PCI_DEVICE_ID_COMPAQ_TRIFLEX	0x4000
 #define PCI_DEVICE_ID_COMPAQ_6010	0x6010
+#define PCI_DEVICE_ID_COMPAQ_ZFMICRO	0xa0f8
 #define PCI_DEVICE_ID_COMPAQ_TACHYON	0xa0fc
 #define PCI_DEVICE_ID_COMPAQ_SMART2P	0xae10
 #define PCI_DEVICE_ID_COMPAQ_NETEL100	0xae32
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/include/nanodisplay.h LinuxBIOSv2/src/include/nanodisplay.h
--- LinuxBIOSv2.orig/src/include/nanodisplay.h	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/include/nanodisplay.h	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,13 @@
+#define NANODISPLAY_SET_CURSOR  0x10
+#define NANODISPLAY_SET_AREA    0x11
+#define NANODISPLAY_CLEAR_AREA  0x12
+#define NANODISPLAY_INVERT_AREA 0x13
+#define NANODISPLAY_SET_OUTLINE 0x14
+#define NANODISPLAY_RESET       0x19
+#define NANODISPLAY_HEX         0x60
+
+extern void nanodisplay_clrscr(void);
+extern void nanodisplay_clrrow(int row);
+extern void nanodisplay_set_xy(int x, int y);
+extern void nanodisplay_write(int row, char *buf, int len);
+extern void nanodisplay_progressbar(int row, int percentage);
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/lib/memcpy.c LinuxBIOSv2/src/lib/memcpy.c
--- LinuxBIOSv2.orig/src/lib/memcpy.c	2006-02-24 10:33:48.000000000 +0100
+++ LinuxBIOSv2/src/lib/memcpy.c	2006-02-21 18:24:11.000000000 +0100
@@ -1,3 +1,5 @@
+//#include <console/console.h>
+//#include <arch/pirq_routing.h>
 #include <string.h>
 void *memcpy(void *vdest, const void *vsrc, size_t bytes)
 {
@@ -5,8 +7,14 @@
 	char *dest = vdest;
 	int i;
 
-	for (i = 0; i < bytes; i++)
+	for (i = 0; i < bytes; i++) {
+//		if (vsrc == &intel_irq_routing_table)
+//			printk_info("mempcpy: writing 0x%x from 0x%x to 0x%x...",
+//			src[i], &src[i], &dest[i]);
 		dest[i] = src[i];
+//		if (vsrc == &intel_irq_routing_table)
+//			printk_info("0x%x written.\n", dest[i]);
+	}
 
 	return vdest;
 }
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/auto.c LinuxBIOSv2/src/mainboard/nano-system/ncg266/auto.c
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/auto.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/auto.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,31 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <arch/hlt.h>
+#include <arch/cpu.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "cpu/x86/bist.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+
+
+#include "superio/NSC/scx200/scx200_superio_early_serial.c"
+#include "northbridge/amd/gx1/raminit.c"
+
+static void main(unsigned long bist)
+{
+	scx200_init_early_serial();
+	uart_init();
+	console_init();
+
+	sdram_init();
+}
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/chip.h LinuxBIOSv2/src/mainboard/nano-system/ncg266/chip.h
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/chip.h	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/chip.h	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,5 @@
+extern struct chip_operations mainboard_nano_system_ncg266_ops;
+
+struct mainboard_nano_system_ncg266_config {
+	int nothing;
+};
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/cmos.layout LinuxBIOSv2/src/mainboard/nano-system/ncg266/cmos.layout
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/cmos.layout	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/cmos.layout	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,74 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432	     8       h       0        boot_countdown
+1008         16      h       0        check_sum
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+
+checksums
+
+checksum 392 1007 1008
+
+
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/Config.lb LinuxBIOSv2/src/mainboard/nano-system/ncg266/Config.lb
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/Config.lb	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/Config.lb	2006-03-30 17:10:17.000000000 +0200
@@ -0,0 +1,210 @@
+##
+## Author: Per Hallsmark <per.hallsmark@t2data.se>
+##
+
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=0x10000
+#default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+if HAVE_PIRQ_TABLE object irq_tables.o end
+if HAVE_HARD_RESET object reset.o end
+object nanodisplay.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+	depends "$(MAINBOARD)/failover.c ./romcc" 
+	action "./romcc -E -mcpu=i386 -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+	depends "$(MAINBOARD)/failover.c ./romcc"
+	action "./romcc    -mcpu=i386 -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E 
+	depends	"$(MAINBOARD)/auto.c option_table.h ./romcc" 
+	action	"./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc 
+	depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	action	"./romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if HAVE_FALLBACK_BOOT
+	if USE_FALLBACK_IMAGE 
+		mainboardinit cpu/x86/16bit/reset16.inc 
+		ldscript /cpu/x86/16bit/reset16.lds 
+	else
+		mainboardinit cpu/x86/32bit/reset32.inc 
+		ldscript /cpu/x86/32bit/reset32.lds 
+	end
+else
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+mainboardinit southbridge/amd/scx200/scx200_southbridge_setup.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds 
+	mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/amd/model_gx1/cpu_setup.inc
+mainboardinit cpu/amd/model_gx1/gx_setup.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files 
+##
+dir /pc80
+config chip.h
+
+chip northbridge/amd/gx1
+  device pci_domain 0 on 
+    device pci 0.0 on end
+      chip southbridge/amd/scx200
+        device pci  a.0 on  end		# ETH0
+        device pci  b.0 on  end		# ETH1
+        device pci 11.0 on  end		# external PCI slot
+        device pci 12.0 on              # SuperIO
+          chip superio/NSC/scx200
+            device pnp 2e.0 on		# Realtime clock
+              io  0x60 = 0x070
+              io  0x62 = 0x072
+              irq 0x70 = 8
+            end
+            device pnp 2e.1 off	# System wakeup control
+              io  0x60 = 0x860
+              irq 0x70 = 9
+            end
+            device pnp 2e.2 on		# Serial port 3
+              io  0x60 = 0x3e8
+              irq 0x70 = 4
+              drq 0x74 = 4  # disable DMA ch 0
+              drq 0x75 = 4  # disable DMA ch 1
+            end
+            device pnp 2e.3 on		# Serial port 1
+              io  0x60 = 0x3f8
+              irq 0x70 = 4
+            end
+            device pnp 2e.4 off		# N/A
+            end
+            device pnp 2e.5 off		# i2c 1
+              io  0x60 = 0x820
+              irq 0x70 = 0
+            end
+            device pnp 2e.6 off		# i2c 2
+              io  0x60 = 0x840
+              irq 0x70 = 0
+            end
+            device pnp 2e.7 off		# Parallell port
+              io  0x60 = 0x278
+              irq 0x70 = 7
+            end
+            device pnp 2e.8 on		# Serial port 2
+              io  0x60 = 0x2f8
+              irq 0x70 = 3
+            end
+            register "com1" = "{TTYS0_BAUD}"
+            register "com2" = "{TTYS0_BAUD}"
+            register "com3" = "{19200}"
+        end
+      end
+      device pci 12.1 on  end		# SMI
+      device pci 12.2 on  end		# IDE
+      device pci 12.3 on  end		# Audio
+      device pci 12.4 on  end		# VGA
+      device pci 12.5 on  end		# X-Bus
+      device pci 13.0 on  end		# USB
+    end
+  end
+
+  device apic_cluster 0 on
+    chip cpu/amd/model_gx1
+      device apic 0 on end
+    end
+  end
+
+end
+
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/debug.c LinuxBIOSv2/src/mainboard/nano-system/ncg266/debug.c
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/debug.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/debug.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,66 @@
+
+static void print_debug_pci_dev(unsigned dev)
+{
+	print_debug("PCI: ");
+	print_debug_hex8((dev >> 16) & 0xff);
+	print_debug_char(':');
+	print_debug_hex8((dev >> 11) & 0x1f);
+	print_debug_char('.');
+	print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0); 
+		dev <= PCI_DEV(0, 0x1f, 0x7); 
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		print_debug_pci_dev(dev);
+		print_debug("\r\n");
+	}
+}
+
+static void dump_pci_device(unsigned dev)
+{
+	int i;
+	print_debug_pci_dev(dev);
+	print_debug("\r\n");
+	
+	for(i = 0; i <= 255; i++) {
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+		print_debug_char(' ');
+		print_debug_hex8(val);
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\r\n");
+		}
+	}
+}
+
+static void dump_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0); 
+		dev <= PCI_DEV(0, 0x1f, 0x7); 
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		dump_pci_device(dev);
+	}
+}
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/failover.c LinuxBIOSv2/src/mainboard/nano-system/ncg266/failover.c
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/failover.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/failover.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,32 @@
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "arch/romcc_io.h"
+#include "pc80/mc146818rtc_early.c"
+
+static unsigned long main(unsigned long bist)
+{
+	/* This is the primary cpu how should I boot? */
+	if (do_normal_boot()) {
+		goto normal_image;
+	}
+	else {
+		goto fallback_image;
+	}
+ normal_image:
+	asm volatile ("jmp __normal_image" 
+		: /* outputs */ 
+		: "a" (bist) /* inputs */
+		: /* clobbers */
+		);
+ cpu_reset:
+	asm volatile ("jmp __cpu_reset"
+		: /* outputs */ 
+		: "a"(bist) /* inputs */
+		: /* clobbers */
+		);
+ fallback_image:
+	return bist;
+}
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/irq_tables.c LinuxBIOSv2/src/mainboard/nano-system/ncg266/irq_tables.c
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/irq_tables.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/irq_tables.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,34 @@
+#include <arch/pirq_routing.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,			// u32 signature
+	PIRQ_VERSION,			// u16 version
+	32+5*sizeof(struct irq_info),	// there can be total 5 devices on the bus
+	0x00,				// Where the interrupt router lies (bus)
+	PCI_DEVFN(12,0),		// Where the interrupt router lies (dev)
+	0,				// IRQs devoted exclusively to PCI usage
+	PCI_VENDOR_ID_CYRIX,		// Vendor
+	PCI_DEVICE_ID_CYRIX_5520,	// Device
+	0,				// Crap (miniport)
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // u8 rfu[11]
+	0xa3,				// u8 checksum , this has to be set to
+					// some value that would give 0 after
+					// the sum of all bytes for this
+					// structure (including checksum)
+	{
+// bus,     dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu
+/* Eth0     */	{0x00,(0x0a<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+/* Eth1     */	{0x00,(0x0b<<3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+/* PCI-slot */	{0x00,(0x11<<3)|0x0, {{0x01, 0x0400}, {0x02, 0x0400}, {0x03, 0x0020}, {0x00, 0x00000}}, 0x1, 0x0},
+/* Audio    */	{0x00,(0x12<<3)|0x3, {{0x03, 0x0020}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+/* USB      */	{0x00,(0x13<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0x00800}}, 0x0, 0x0},
+	}
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	return copy_pirq_routing_table(addr);
+}
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/mainboard.c LinuxBIOSv2/src/mainboard/nano-system/ncg266/mainboard.c
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/mainboard.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/mainboard.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,22 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "chip.h"
+
+struct chip_operations mainboard_nano_system_ncg266_ops = {
+	CHIP_NAME("Nano-system NCG266 mainboard ")
+};
+
+#if !CONFIG_UDELAY_TSC
+void udelay(int usecs)
+{
+  int i;
+  for(i = 0; i < usecs; i++)
+    outb(i&0xff, 0x80);
+}
+#endif
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/nanodisplay.c LinuxBIOSv2/src/mainboard/nano-system/ncg266/nanodisplay.c
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/nanodisplay.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/nanodisplay.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,81 @@
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "uart8250.h"
+#include "nanodisplay.h"
+
+#define nanodisplay_hw_put(x) uart8250_tx_byte(0x3e8, x)
+
+void nanodisplay_clrscr(void)
+{
+  nanodisplay_hw_put(NANODISPLAY_CLEAR_AREA);
+  nanodisplay_hw_put(0);
+  nanodisplay_hw_put(0);
+  nanodisplay_hw_put(127);
+  nanodisplay_hw_put(31);
+}
+
+void nanodisplay_clrrow(int row)
+{
+  nanodisplay_hw_put(NANODISPLAY_CLEAR_AREA);
+  nanodisplay_hw_put(0);
+  nanodisplay_hw_put(row*8);
+  nanodisplay_hw_put(127);
+  nanodisplay_hw_put(row*8+7);
+}
+
+void nanodisplay_set_xy(int x, int y)
+{
+  nanodisplay_hw_put(NANODISPLAY_SET_CURSOR);
+  nanodisplay_hw_put(x);
+  nanodisplay_hw_put(y);
+}
+
+void nanodisplay_write(int row, char *buf, int len)
+{
+  int i=0;
+  nanodisplay_clrrow(row);
+  nanodisplay_set_xy(0,row*8+7);
+  if (!len) {
+    len=strlen(buf);
+  }
+  while (len--) {
+    nanodisplay_hw_put(buf[i++]);
+  }
+}
+
+static int old_row;
+static int old_percentage;
+
+void nanodisplay_progressbar(int row, int percentage)
+{
+  if (old_row == row)
+    if (old_percentage == percentage)
+      return;
+
+  nanodisplay_hw_put(NANODISPLAY_SET_OUTLINE);
+  nanodisplay_hw_put(0);
+  nanodisplay_hw_put(row*8);
+  nanodisplay_hw_put(127);
+  nanodisplay_hw_put(row*8+7);
+
+#if 0
+  nanodisplay_hw_put(NANODISPLAY_CLEAR_AREA);
+  nanodisplay_hw_put(1);
+  nanodisplay_hw_put(row*8+1);
+  nanodisplay_hw_put(126);
+  nanodisplay_hw_put(row*8+6);
+#endif
+
+  if (percentage) {
+    nanodisplay_hw_put(NANODISPLAY_SET_AREA);
+    nanodisplay_hw_put(1);
+    nanodisplay_hw_put(row*8+1);
+    nanodisplay_hw_put((126*percentage)/100);
+    nanodisplay_hw_put(row*8+6);
+  }
+
+  old_row        = row;
+  old_percentage = percentage;
+}
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/Options.lb LinuxBIOSv2/src/mainboard/nano-system/ncg266/Options.lb
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/Options.lb	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/Options.lb	2006-03-31 10:51:33.000000000 +0200
@@ -0,0 +1,182 @@
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_ACPI_TABLES
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses HAVE_OPTION_TABLE
+uses USE_OPTION_TABLE
+uses CONFIG_ROM_STREAM
+uses IRQ_SLOT_COUNT
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
+uses ARCH
+uses FALLBACK_SIZE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses _RAMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses HAVE_MP_TABLE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses CONFIG_UDELAY_TSC
+uses CONFIG_UDELAY_IO
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses DEBUG
+uses PNP_CFGADDR
+uses PNP_CFGDATA
+
+#uses CONFIG_USE_INIT
+#default CONFIG_USE_INIT=1
+
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE  = 0x40000
+
+###
+### Build options
+###
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=0
+
+##
+## no MP table
+##
+default HAVE_MP_TABLE=0
+
+##
+## no ACPI tables
+##
+default HAVE_ACPI_TABLES=0
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Delay timer options, choose either IO or TSC
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_UDELAY_IO=0
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=5
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=0
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+default FALLBACK_SIZE = 0
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x4000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x8000
+
+##
+## Only use the option table in a normal image
+##
+#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default USE_OPTION_TABLE = 0
+
+default _RAMBASE = 0x00004000
+
+default CONFIG_ROM_STREAM = 1
+
+##
+## PNP stuff
+##
+default PNP_CFGADDR=0x2e
+default PNP_CFGDATA=0x2f
+
+##
+## The default compiler
+##
+default CROSS_COMPILE=""
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG      1   system is unusable               
+## ALERT      2   action must be taken immediately 
+## CRIT       3   critical conditions              
+## ERR        4   error conditions                 
+## WARNING    5   warning conditions               
+## NOTICE     6   normal but significant condition 
+## INFO       7   informational                    
+## DEBUG      8   debug-level messages             
+## SPEW       9   Way too many details             
+
+## Request this level of debugging output
+default  DEFAULT_CONSOLE_LOGLEVEL=0
+## At a maximum only compile in this level of debugging
+default  MAXIMUM_CONSOLE_LOGLEVEL=0
+
+default DEBUG=0
+
+end
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/reset.c LinuxBIOSv2/src/mainboard/nano-system/ncg266/reset.c
--- LinuxBIOSv2.orig/src/mainboard/nano-system/ncg266/reset.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/mainboard/nano-system/ncg266/reset.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,11 @@
+#include <arch/io.h>
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+	(((BUS) & 0xFF) << 16) | \
+	(((DEV) & 0x1f) << 11) | \
+	(((FN)  & 0x7) << 8))
+
+void hard_reset(void)
+{
+	pci_write_config8(PCI_DEV(0, 0x12, 0), 0x44, 1);
+}
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/northbridge/amd/gx1/northbridge.c LinuxBIOSv2/src/northbridge/amd/gx1/northbridge.c
--- LinuxBIOSv2.orig/src/northbridge/amd/gx1/northbridge.c	2006-02-24 10:33:48.000000000 +0100
+++ LinuxBIOSv2/src/northbridge/amd/gx1/northbridge.c	2006-02-21 18:24:11.000000000 +0100
@@ -11,16 +11,21 @@
 #include "northbridge.h"
 #include <cpu/amd/gx1def.h>
 
-#define NORTHBRIDGE_FILE "northbridge.c"
-/*
-*/
-
 static void optimize_xbus(device_t dev)
 {
+	uint16_t reg16;
+
+	// disable SERR, PARERR
+	reg16 = pci_read_config16(dev, 0x04);
+	reg16 &= ~0x0140;
+	pci_write_config16(dev, 0x04, reg16);
+
 	/* Optimise X-Bus performance */
 	pci_write_config8(dev, 0x40, 0x1e);
-	pci_write_config8(dev, 0x41, 0x52);
-	pci_write_config8(dev, 0x43, 0xc1);
+//	pci_write_config8(dev, 0x41, 0x52);
+	pci_write_config8(dev, 0x41, 0x00); // PER - changed 52 to 00
+//	pci_write_config8(dev, 0x43, 0xc1);
+	pci_write_config8(dev, 0x43, 0x26); // PER - changed c1 to 26
 	pci_write_config8(dev, 0x44, 0x00);
 }
 
@@ -31,7 +36,7 @@
 
 static void northbridge_init(device_t dev) 
 {
-	printk_debug("northbridge: %s()\n", __FUNCTION__);
+	printk_debug("%s:\n", __FUNCTION__);
 	
 	optimize_xbus(dev);
 	enable_shadow(dev);
@@ -53,15 +58,13 @@
 	.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, 
 };
 
-
-
 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
 
 static void pci_domain_read_resources(device_t dev)
 {
         struct resource *resource;
 
-	printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
+	printk_spew("%s:%s()\n", __FILE__, __FUNCTION__);
 
         /* Initialize the system wide io space constraints */
         resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/northbridge/amd/gx1/raminit.c LinuxBIOSv2/src/northbridge/amd/gx1/raminit.c
--- LinuxBIOSv2.orig/src/northbridge/amd/gx1/raminit.c	2006-02-24 10:33:48.000000000 +0100
+++ LinuxBIOSv2/src/northbridge/amd/gx1/raminit.c	2006-02-21 18:24:11.000000000 +0100
@@ -318,20 +318,61 @@
 
 static void sdram_init(void) 
 {
-unsigned int mem_config = 0x00700070;
+	uint32_t mem_config = 0x00700070;
+	uint32_t reg32;
 
 	print_debug("Setting up default parameters for memory\r\n");
 	outb(0x70, 0x80);
 
+#if 0
+	// reset settings according to errata 2.14
+	setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x248C0040);
+	setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x00000801);
+	setGX1Mem(GX_BASE + MC_BANK_CFG,   0x41104110);
+	setGX1Mem(GX_BASE + MC_SYNC_TIM1,  0x2A733225);
+#endif
+	
+#if 1
+#if 0
 	setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */
 	setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */
 	setGX1Mem(GX_BASE + MC_BANK_CFG,   0x00700070); /* No DIMMS installed */
 	setGX1Mem(GX_BASE + MC_SYNC_TIM1,  0x3a733225); /* LTMODE=3, RC=10, RAS=7, RP=3, RCD=3, RRD=2, DPL=2 */
+#else
+	// set mem configuration
+	setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x00000018);
+	setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0xb68e3f04);
+	setGX1Mem(GX_BASE + MC_SYNC_TIM1,  0x27532125);
+
+
+	// unlock mem config
+	reg32 = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
+	reg32 &= ~0x20001;
+	setGX1Mem(GX_BASE + MC_MEM_CNTRL1, reg32);
+	reg32 = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
+	reg32 |= 0x20001;
+	setGX1Mem(GX_BASE + MC_MEM_CNTRL1, reg32);
+
+	// set mem configuration again
+	setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x00000018);
+	setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0xb68e3f04);
+	setGX1Mem(GX_BASE + MC_SYNC_TIM1,  0x27532125);
+
+	// unlock mem config
+	reg32 = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
+	reg32 &= ~0x20001;
+	setGX1Mem(GX_BASE + MC_MEM_CNTRL1, reg32);
+	reg32 = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
+	reg32 |= 0x20001;
+	setGX1Mem(GX_BASE + MC_MEM_CNTRL1, reg32);
+
+#endif
 	setGX1Mem(GX_BASE + MC_BANK_CFG,   0x57405740); /* Largest DIMM size 
 						0x4000 -- 2 module banks
 						0x1000 -- 4 component banks
 						0x0700 -- DIMM size 512MB
 						0x0040 -- Page Size 16kB */
+#endif
 
 	enable_dimm();
 
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/chip.h LinuxBIOSv2/src/southbridge/amd/scx200/chip.h
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/chip.h	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/chip.h	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,10 @@
+#ifndef _SOUTHBRIDGE_AMD_SCX200
+#define _SOUTHBRIDGE_AMD_SCX200
+
+extern struct chip_operations southbridge_amd_scx200_ops;
+
+struct southbridge_amd_scx200_config {
+	/* PCI function enables so the pci scan bus finds the devices */
+};
+
+#endif	/* _SOUTHBRIDGE_AMD_SCX200 */
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/Config.lb LinuxBIOSv2/src/southbridge/amd/scx200/Config.lb
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/Config.lb	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/Config.lb	2006-03-30 17:13:49.000000000 +0200
@@ -0,0 +1,9 @@
+driver scx200_southbridge.o
+driver scx200_smi.o
+driver scx200_ide.o
+driver scx200_audio.o
+driver scx200_video.o
+driver scx200_xbus.o
+driver scx200_usb.o
+#driver scx200_pci.o
+driver rtl8139.o
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/rtl8139.c LinuxBIOSv2/src/southbridge/amd/scx200/rtl8139.c
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/rtl8139.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/rtl8139.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,54 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+
+static void rtl8139_init(struct device *dev)
+{
+	uint16_t word;
+
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+
+	// set PCI master capability
+	word = pci_read_config16(dev, 0x04);
+	word |= 0x04;
+	pci_write_config16(dev, 0x04, word);
+
+	// disable SERR, PARERR
+	word = pci_read_config16(dev, 0x04);
+	word &= ~0x0140;
+	pci_write_config16(dev, 0x04, word);
+
+	// IRQ10
+	pci_write_config8(dev, 0x3c, 0xA);
+
+	// INTA#
+	pci_write_config8(dev, 0x3d, 1);
+}
+
+static void rtl8139_enable(struct device *dev)
+{
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+}
+
+static struct device_operations nic_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init		  = rtl8139_init,
+	.scan_bus         = 0,
+	.enable		  = rtl8139_enable,
+};
+
+static struct pci_driver nic_driver __pci_driver = {
+	.ops    = &nic_ops,
+	.vendor = PCI_VENDOR_ID_REALTEK,
+	.device = PCI_DEVICE_ID_REALTEK_8139,
+};
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_audio.c LinuxBIOSv2/src/southbridge/amd/scx200/scx200_audio.c
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_audio.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/scx200_audio.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,44 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+static void scx200_audio_init(struct device *dev)
+{
+	uint16_t word;
+
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+
+	// set PCI master capability
+	word = pci_read_config16(dev, 0x04);
+	word |= 0x04;
+	pci_write_config16(dev, 0x04, word);
+
+	// enable bit 25 in PMR, AC97_CLK output
+}
+
+static void scx200_audio_enable(struct device *dev)
+{
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+}
+
+static struct device_operations audio_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init		  = scx200_audio_init,
+	.scan_bus         = 0,
+	.enable		  = scx200_audio_enable,
+};
+
+static struct pci_driver audio_driver __pci_driver = {
+	.ops    = &audio_ops,
+	.vendor = PCI_VENDOR_ID_NS,
+	.device = PCI_DEVICE_ID_NS_SCx200_AUDIO,
+};
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_ide.c LinuxBIOSv2/src/southbridge/amd/scx200/scx200_ide.c
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_ide.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/scx200_ide.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,128 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+// set to 1 to enable DMA usage
+#define DMA  1
+
+// set to 1 to enable IDE1 - ncg266 can't use IDE1 since
+// there's a pin conflict when using TFT functionality
+#define IDE1 0  
+
+static void scx200_ide_init(struct device *dev)
+{
+	uint8_t reg8;
+	uint16_t reg16;
+	uint32_t reg32;
+	uint32_t ide;
+
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+
+	// set PCI master capability
+	reg16 = pci_read_config16(dev, 0x04);
+	reg16 |= 0x04;
+	pci_write_config16(dev, 0x04, reg16);
+
+#if DMA
+	// set ide0 (primary and secondary) DMA
+
+	reg32  = 0x80000000; // PIO format 1 - separate timing for cmd/data
+//	reg32  = 0x00000000; // PIO format 0 - same timing for cmd/data
+//	reg32 |= 0x00077771; // Multiword DMA Mode 0
+//	reg32 |= 0x00002020; // Multiword DMA Mode 2
+//	reg32 |= 0x00921250; // UltraDMA Mode 0
+	reg32 |= 0x00911030; // UltraDMA Mode 2
+	pci_write_config32(dev, 0x44, reg32);
+	pci_write_config32(dev, 0x4c, reg32);
+
+	// set ide0 (primary and secondary) PIO mode depending on PIO format
+	if (reg32 & 0x80000000) {
+//		reg32 = 0x9172D132; // PIO mode 0
+		reg32 = 0x00100010; // PIO mode 4
+	} else {
+//		reg32 = 0x00009172; // PIO mode 0
+		reg32 = 0x00400010; // PIO mode 4
+	}
+	pci_write_config32(dev, 0x40, reg32);
+	pci_write_config32(dev, 0x48, reg32);
+
+	ide = pci_read_config32(dev, 0x10) & 0xFFFE;
+
+	// enable ide0 (primary and secondary) DMA
+	reg8 = inb(ide+2);
+	reg8 |= 0x60;
+	outb(reg8, ide+2);
+#else
+	// disable ide0 (primary and secondary) DMA
+	reg8 = inb(ide+2);
+	reg8 &= ~0x60;
+	outb(reg8, ide+2);
+#endif
+
+	// reset bits 3,4 see "AMD Geode SC2200 Processor Data Book" pg 277
+	reg8 = inb(ide+2);
+	reg8 &= ~0x18;
+//	outb(reg8, ide+2);
+
+#if IDE1
+#if DMA
+  ncg266 platform uses TFT/LVDS interface which is
+  fighting with IDE1 for io-pins... :-)
+	// set ide1 (primary and secondary) to PIO mode 4 
+	reg32 = 0x00100010;
+	pci_write_config32(dev, 0x50, reg32);
+	pci_write_config32(dev, 0x58, reg32);
+
+	// set ide1 (primary and secondary) DMA
+	reg32  = 0x80000000; // PIO format 1
+	reg32 |= 0x00077771; // Multiword DMA Mode 2
+	pci_write_config32(dev, 0x54, reg32);
+	pci_write_config32(dev, 0x5c, reg32);
+
+	ide = pci_read_config32(dev, 0x14) & 0xFFFE;
+
+	// enable ide1 (primary and secondary) DMA
+	reg8 = inb(ide+0xa);
+	reg8 |= 0x60;
+	outb(reg8, ide+0xa);
+#else
+	// disable ide0 (primary and secondary) DMA
+	reg8 = inb(ide+2);
+	reg8 &= ~0x60;
+	outb(reg8, ide+2);
+#endif
+
+	// reset bits 3,4 see "AMD Geode SC2200 Processor Data Book" pg 277
+	reg8 = inb(ide+2);
+	reg8 &= ~0x18;
+	outb(reg8, ide+2);
+#endif
+}
+
+static void scx200_ide_enable(struct device *dev)
+{
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+}
+
+static struct device_operations ide_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = scx200_ide_init,
+	.scan_bus         = 0,
+	.enable           = scx200_ide_enable,
+};
+
+static struct pci_driver ide_driver __pci_driver = {
+	.ops    = &ide_ops,
+	.vendor = PCI_VENDOR_ID_NS,
+	.device = PCI_DEVICE_ID_NS_SCx200_IDE,
+};
+
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_smi.c LinuxBIOSv2/src/southbridge/amd/scx200/scx200_smi.c
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_smi.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/scx200_smi.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,40 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+static void scx200_smi_init(struct device *dev)
+{
+	uint16_t word;
+	uint8_t byte;
+	uint32_t reg32;
+
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+}
+
+static void scx200_smi_enable(struct device *dev)
+{
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+}
+
+static struct device_operations smi_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = scx200_smi_init,
+	.scan_bus         = 0,
+	.enable           = scx200_smi_enable,
+};
+
+static struct pci_driver smi_driver __pci_driver = {
+	.ops    = &smi_ops,
+	.vendor = PCI_VENDOR_ID_NS,
+	.device = PCI_DEVICE_ID_NS_SCx200_SMI,
+};
+
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_southbridge.c LinuxBIOSv2/src/southbridge/amd/scx200/scx200_southbridge.c
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_southbridge.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/scx200_southbridge.c	2006-03-31 09:34:16.000000000 +0200
@@ -0,0 +1,154 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "scx200_southbridge.h"
+
+static void scx200_southbridge_init(struct device *dev)
+{
+	uint8_t ilevsel1;
+	uint8_t ilevsel2;
+	uint32_t gpio;
+	uint32_t lpc;
+	uint8_t reg8;
+	uint16_t reg16;
+	uint32_t reg32;
+
+	printk_debug("%s:\n", __FUNCTION__);
+
+	// disable SERR, PARERR enable MemWINV
+        reg16 = pci_read_config16(dev, 0x04);
+//        reg16 &= ~0x0140;
+        reg16 |=  0x0010;
+        pci_write_config16(dev, 0x04, reg16);
+
+	// Set Cache Line Size to 32 bytes
+        reg8 = pci_read_config8(dev, 0x0c);
+        reg8 = 8;
+        pci_write_config8(dev, 0x0c, reg8);
+
+	// PCI Latency timer disable
+        reg8 = pci_read_config8(dev, 0x0d);
+        reg8 = 0;
+        pci_write_config8(dev, 0x0d, reg8);
+
+	// PCI func ctrl 1
+        reg8 = pci_read_config8(dev, 0x40);
+        reg8 = 0x19;
+        pci_write_config8(dev, 0x40, reg8);
+
+	// Delay transaction register
+        reg8 = pci_read_config8(dev, 0x43);
+        reg8 = 0x3c;
+        pci_write_config8(dev, 0x43, reg8);
+
+	// Enable GPIO & LPC
+        reg8 = pci_read_config8(dev, 0x47);
+        reg8 = 0x6;
+        pci_write_config8(dev, 0x47, reg8);
+
+	// highest system mem address
+        reg32 = pci_read_config32(dev, 0x4c);
+        reg32 = 0x7ffffffc;
+        pci_write_config32(dev, 0x4c, reg32);
+
+	// ISA I/O recovery
+        reg8 = pci_read_config8(dev, 0x51);
+        reg8 = 0x40;  //  8 and 16 bit access, max back2back backoff
+        pci_write_config8(dev, 0x51, reg8);
+
+	// IO speedups
+        reg8 = pci_read_config8(dev, 0x5a);
+        reg8 |= 0x1d; // COM1-3, RTC
+        pci_write_config8(dev, 0x5a, reg8);
+        reg8 = pci_read_config8(dev, 0x5b);
+        reg8 |= 0x38; // BIOS ROM, IDE0-1
+        pci_write_config8(dev, 0x5b, reg8);
+
+	// Chip select #1
+        pci_write_config16(dev, 0x70, 0x8000);
+        pci_write_config16(dev, 0x72, 0x00ff);
+
+	// Power management
+        pci_write_config8(dev, 0x80, 0x07);
+        pci_write_config8(dev, 0x82, 0x18);
+
+	// General purpose timer 2, set to 1 ms. (used by whom??)
+        pci_write_config8(dev, 0x8a, 0x01);
+        pci_write_config8(dev, 0x8b, 0x08);
+
+	// misc reg
+        pci_write_config8(dev, 0x93, 0xC0);
+	
+	ilevsel1 = inb(0x4d0);
+	ilevsel2 = inb(0x4d1);
+	ilevsel2 |= 0x1E; // level sense on IRQ9-12
+	outb(ilevsel2, 0x4d1);
+
+	// connect PCI INTA# and INTB# to IRQ10
+	pci_write_config8(dev, 0x5c, 0xAA);
+	// connect PCI INTC# and INTD# to IRQ11
+	pci_write_config8(dev, 0x5d, 0xBB);
+
+	gpio = pci_read_config32(dev, 0x10) & 0xFFFE;
+	printk_debug("%s: GPIO base 0x%X\n", __FUNCTION__, gpio);
+
+	// Configure GPIO which has LED's connected to them as output
+	//   LED 1 is connected to GPIO 33
+	outl(0x20, gpio+0x20);
+	outl(0x45, gpio+0x24);
+	//   LED 2 is connected to GPIO 34
+	outl(0x21, gpio+0x20);
+	outl(0x45, gpio+0x24);
+	//   LED 3 is connected to GPIO 32
+	outl(0x22, gpio+0x20);
+	outl(0x45, gpio+0x24);
+
+	// Let LED3 (positioned lowest on back panel) be enabled
+	reg32 = inl(gpio+0x10);
+	reg32 &= ~7;
+	reg32 |= 1;
+	outl(reg32, gpio+0x10);
+
+	lpc  = pci_read_config32(dev, 0x14) & 0xFFFE;
+}
+
+#if 1
+static void scx200_southbridge_enable(struct device *dev)
+{
+	printk_debug("%s: dev is %p\n", __FUNCTION__, dev);
+}
+
+static void scx200_southbridge_enable_resources(device_t dev)
+{
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+	pci_dev_enable_resources(dev);
+	enable_childrens_resources(dev);
+
+}
+#endif
+
+static struct device_operations southbridge_ops = {
+	.set_resources    = pci_dev_set_resources,
+#if 1
+	.read_resources   = pci_dev_read_resources,
+	.enable_resources = scx200_southbridge_enable_resources,
+#else
+	.read_resources   = pci_bus_read_resources,
+	.enable_resources = pci_bus_enable_resources,
+#endif
+	.enable           = scx200_southbridge_enable,
+	.init             = scx200_southbridge_init,
+	.scan_bus         = scan_static_bus,
+};
+
+static struct pci_driver scx200_pci_driver __pci_driver = {
+	.ops 	= &southbridge_ops,
+	.vendor = PCI_VENDOR_ID_NS,
+	.device = PCI_DEVICE_ID_NS_SCx200_BRIDGE,
+};
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_southbridge.h LinuxBIOSv2/src/southbridge/amd/scx200/scx200_southbridge.h
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_southbridge.h	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/scx200_southbridge.h	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,4 @@
+#ifndef _SCX200_SOUTHBRIDGE_H
+#define _SCX200_SOUTHBRIDGE_H
+
+#endif
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_southbridge_setup.inc LinuxBIOSv2/src/southbridge/amd/scx200/scx200_southbridge_setup.inc
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_southbridge_setup.inc	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/scx200_southbridge_setup.inc	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,127 @@
+/*
+    Author: Per Hallsmark <per.hallsmark@t2data.se>
+
+    Based on work for freebios by Christer Weinigel <wingel@hack.org>
+
+    Do chipset setup for a National Semiconductor SCx200 CPU
+*/
+
+/**********************************************************************/
+
+#define SCx200_CB_BASE 0x00009000
+#define SCx200_PMR     0x028628d1
+#define SCx200_MCR     0x00000011
+#define F5CFG          0x80009500
+#define F5BAR0         0x00001C80
+
+// watchdog timeout set to 2 minutes
+#define WATCHDOG_INIT  300
+
+scx200_core_setup_start:
+	intel_chip_post_macro(0x12)
+
+	/* Configure F5BAR0 */
+	movl	$f5_setup_table, %esi
+	movl	$f5_setup_len, %ecx
+	movl	$F5CFG, %ebx
+
+f5_setup_loop:
+	movb	(%esi), %bl
+	CALLSP(scx200_pci_read_config_byte)
+	incl	%esi
+	andb	(%esi), %al
+	incl	%esi
+	orb	(%esi), %al
+	CALLSP(scx200_pci_write_config_byte)
+	incl	%esi
+	loopl	f5_setup_loop
+
+	/* Configure SIO address */
+	movw    $F5BAR0, %dx		/* X-Bus expansion registers base */
+	inl     %dx, %eax
+	movl    $0x05040000, %eax	/* set SIO cfg space at 0x2e */
+	outl    %eax, %dx
+
+config_block_setup:
+	movw	$0x2ea, %dx		/* initial register to set address */
+	movw	$SCx200_CB_BASE, %ax	/* Config Block Base Address */
+	outw	%ax, %dx
+
+	movw	$SCx200_CB_BASE, %bx	/* Config Block Base Address */
+	movw	%bx, %dx
+#ifdef SCx200_PMR
+	addw	$0x30, %dx		/* PMR */
+	movl	$SCx200_PMR, %eax
+	outl	%eax, %dx
+	movw	%bx, %dx
+#endif
+#ifdef SCx200_MCR
+	addw	$0x34, %dx		/* MCR */
+	movl	$SCx200_MCR, %eax
+	outl	%eax, %dx
+	movw	%bx, %dx
+#endif
+	addw	$0x12, %dx		/* PPCR */
+	inb	%dx, %al
+	andb	$0x91, %al		/* Enable PLLs */
+	outb	%al, %dx
+
+#if 0
+	/* But this stops the serial port from working. */
+	movw	%bx, %dx
+	addw	$0x18, %dx		/* PLL3 */
+	movl	$0x7601d004, %eax	/* Must be programmed with this */
+	outl	%eax, %dx		/*     value according to databook */
+#endif
+
+#ifdef WATCHDOG_INIT
+watchdog_setup:
+	movw	$SCx200_CB_BASE, %bx	/* Config Block Base Address */
+	movw	%bx, %dx
+	addw	$0x2, %dx		/* WDCNFG */
+	movw	$0xfa, %ax		/* enable watchdog */
+	outw	%ax, %dx
+	movw	%bx, %dx		/* WDTO */
+	movw	$32*(WATCHDOG_INIT), %ax
+	outw	%ax, %dx
+#endif
+
+	intel_chip_post_macro(0x13)
+	jmp	scx200_core_setup_end
+
+scx200_pci_read_config_byte:
+        movw    $0xcf8, %dx
+        movl    %ebx, %eax
+        outl    %eax, %dx
+        movw    %ax, %dx
+        andw    $3, %dx
+        orw     $0xcfc, %dx
+        inb     %dx, %al
+        RETSP
+
+scx200_pci_write_config_byte:
+        movw    $0xcf8, %dx
+        xchgl   %ebx, %eax
+        outl    %eax, %dx
+        movw    %ax, %dx
+        andw    $3, %dx
+        orw     $0xcfc, %dx
+        xchgl   %ebx, %eax
+        outb    %al, %dx
+        RETSP
+
+f5_setup_table:
+	.byte	0x40, 0x00, 0xc1	/* F5BAR0 Mask = 0xffffffc1 */
+	.byte	0x41, 0x00, 0xff
+	.byte	0x42, 0x00, 0xff
+	.byte	0x43, 0x00, 0xff
+	.byte	0x10, 0x00, 0x81	/* F5BAR0/X-Bus = 0x00001C81 */
+	.byte	0x11, 0x00, 0x1C
+	.byte	0x12, 0x00, 0x00
+	.byte	0x13, 0x00, 0x00
+
+	.byte	0x04, 0x00, 0x03	/* Enable F5 Memory and I/O Space */
+f5_setup_len = (.-f5_setup_table) / 3
+
+scx200_core_setup_end:
+	intel_chip_post_macro(0x14)
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_usb.c LinuxBIOSv2/src/southbridge/amd/scx200/scx200_usb.c
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_usb.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/scx200_usb.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,57 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+static void scx200_usb_init(struct device *dev)
+{
+	uint32_t word;
+
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+                0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+	pci_write_config8(dev, 0x3c, 0x0B); // IRQ11
+	pci_write_config8(dev, 0x3d, 0x04); // use PCI INTD#
+
+	// enable PCI master, MEM, IO
+        word = pci_read_config16(dev, 0x04);
+        word |= 0x07;
+        pci_write_config16(dev, 0x04, word);
+
+	// disable SERR,PARERR
+	word = pci_read_config16(dev, 0x04);
+//	word &= ~0x0140;
+	pci_write_config16(dev, 0x04, word);
+}
+
+static void scx200_usb_enable(struct device *dev)
+{
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+                0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+}
+
+static void scx200_usb_dev_enable_resources(device_t dev)
+{
+        printk_spew("%s: %s()\n", __FILE__, __FUNCTION__);
+        pci_dev_enable_resources(dev);
+
+        printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+                0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+}
+
+static struct device_operations usb_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = scx200_usb_init,
+	.scan_bus         = 0,
+	.enable           = scx200_usb_enable,
+};
+
+static struct pci_driver usb_driver __pci_driver = {
+	.ops    = &usb_ops,
+	.vendor = PCI_VENDOR_ID_COMPAQ,
+	.device = PCI_DEVICE_ID_COMPAQ_ZFMICRO,
+};
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_video.c LinuxBIOSv2/src/southbridge/amd/scx200/scx200_video.c
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_video.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/scx200_video.c	2006-03-30 17:02:53.000000000 +0200
@@ -0,0 +1,46 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+
+static void scx200_video_init(struct device *dev)
+{
+	uint16_t word;
+
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+
+	// IRQ definitions
+	pci_write_config8(dev, 0x3c, 0x0D); // IRQ11
+	pci_write_config8(dev, 0x3d, 0x03); // use PCI INTC#
+
+	// unset bit 17 in MCR, HSYNC for CRT
+	// unset bit 16 in MCR, HSYNC for CRT
+
+}
+
+static void scx200_video_enable(struct device *dev)
+{
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+}
+
+static struct device_operations video_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init		  = scx200_video_init,
+	.scan_bus         = 0,
+	.enable		  = scx200_video_enable,
+};
+
+static struct pci_driver video_driver __pci_driver = {
+	.ops    = &video_ops,
+	.vendor = PCI_VENDOR_ID_NS,
+	.device = PCI_DEVICE_ID_NS_SCx200_VIDEO,
+};
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_xbus.c LinuxBIOSv2/src/southbridge/amd/scx200/scx200_xbus.c
--- LinuxBIOSv2.orig/src/southbridge/amd/scx200/scx200_xbus.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/southbridge/amd/scx200/scx200_xbus.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,60 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+
+static void scx200_xbus_init(struct device *dev)
+{
+	uint32_t xbus_ext;
+	uint16_t word;
+	uint8_t byte;
+	uint32_t reg32;
+
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+
+	// set PCI master capability
+	word = pci_read_config16(dev, 0x04);
+	word |= 0x03;
+	pci_write_config16(dev, 0x04, word);
+
+	xbus_ext = pci_read_config32(dev, 0x10) & 0xFFFE;
+
+	reg32 = inl(xbus_ext);
+	printk_debug("%s: offs 0x%X 0x%X\n", __FUNCTION__, xbus_ext, reg32);
+//	reg32 |= 0x08000000; // enable SIO_IR, also used for com3
+	reg32 |= 0x00040000; // enable USB
+//	reg32 |= 0x00180000; // enable USB SMI's
+	outl(reg32, xbus_ext);
+
+	// USB full power
+	reg32 = inl(xbus_ext+8);
+	outl(reg32 | 0xFF00, xbus_ext+8);
+	
+}
+
+static void scx200_xbus_enable(struct device *dev)
+{
+	printk_debug("%s: %02x:%02x:%02x\n", __FUNCTION__,
+		0, PCI_SLOT(dev->path.u.pci.devfn), PCI_FUNC(dev->path.u.pci.devfn));
+}
+
+static struct device_operations xbus_ops  = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = scx200_xbus_init,
+	.scan_bus         = 0,
+	.enable           = scx200_xbus_enable,
+};
+
+static struct pci_driver xbus_driver __pci_driver = {
+	.ops    = &xbus_ops,
+	.vendor = PCI_VENDOR_ID_NS,
+	.device = PCI_DEVICE_ID_NS_SCx200_XBUS,
+};
+
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/superio/NSC/scx200/chip.h LinuxBIOSv2/src/superio/NSC/scx200/chip.h
--- LinuxBIOSv2.orig/src/superio/NSC/scx200/chip.h	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/superio/NSC/scx200/chip.h	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,11 @@
+#ifndef _SUPERIO_NSC_SCX200
+#define _SUPERIO_NSC_SCX200
+
+#include <uart8250.h>
+
+extern struct chip_operations superio_NSC_scx200_ops;
+
+struct superio_NSC_scx200_config {
+	struct uart8250 com1, com2, com3;
+};
+#endif /* _SUPERIO_NSC_SCX200 */
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/superio/NSC/scx200/Config.lb LinuxBIOSv2/src/superio/NSC/scx200/Config.lb
--- LinuxBIOSv2.orig/src/superio/NSC/scx200/Config.lb	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/superio/NSC/scx200/Config.lb	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,2 @@
+config chip.h
+object scx200_superio.o
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/superio/NSC/scx200/scx200_superio.c LinuxBIOSv2/src/superio/NSC/scx200/scx200_superio.c
--- LinuxBIOSv2.orig/src/superio/NSC/scx200/scx200_superio.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/superio/NSC/scx200/scx200_superio.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,179 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include "chip.h"
+#include "scx200_superio.h"
+
+extern void nanodisplay_clrscr(void);
+extern void nanodisplay_clrrow(int row);
+extern void nanodisplay_set_xy(int x, int y);
+extern void nanodisplay_write(int row, char *buf, int len);
+extern void nanodisplay_progressbar(int row, int percentage);
+
+#define GENERIC_UART_SETUP 1
+
+static void scx200_superio_RTC_setup(device_t dev)
+{
+	uint8_t  reg8;
+	struct resource *res0;
+
+	res0 = find_resource(dev, PNP_IDX_IO0);
+
+	// set intr type "low polarity"
+	// because we've set irq to 8
+	reg8 = pnp_read_config(dev, 0x71);
+	pnp_write_config(dev, 0x71, reg8 & 0xFD);
+
+	// wakeup RTC
+	outb(0xD, res0->base); // select RTC register CRD
+	reg8 = inb(res0->base+1);
+	reg8 = inb(res0->base+1);
+	if (!(reg8 & 0x80)) {
+		printk_warning("SCx200 RTC suffer from low battery level!\n");
+	}
+	outb(0xB, res0->base); // select RTC register CRB
+	reg8 = inb(res0->base+1);
+//	reg8 |= 0x01; // enable DST
+	reg8 |= 0x02; // enable 24H format
+}
+
+#if !GENERIC_UART_SETUP
+static void scx200_superio_SP_set_bank(int port, int bank)
+{
+	uint8_t reg8;
+	reg8 = inb(port + UART_LCR);
+	switch (bank) {
+		case 0:
+			break;
+		case 1:
+			reg8 |= 0x80;
+			break;
+		case 2:
+			reg8 |= 0xe0;
+			break;
+		case 3:
+			reg8 |= 0xe4;
+			break;
+		default:
+			break;
+	}
+	outb(reg8, port + UART_LCR);
+}
+#endif
+
+static void scx200_superio_SP_setup(device_t dev, struct uart8250 *uart)
+{
+	uint8_t  reg8;
+	uint8_t  lcr;
+	uint16_t divisor;
+	struct resource *res0;
+
+	// set intr type "high polarity"
+	reg8 = pnp_read_config(dev, 0x71);
+	pnp_write_config(dev, 0x71, reg8 | 0x02);
+
+	// enable serial port bank switching
+	reg8 = pnp_read_config(dev, 0xF0);
+	pnp_write_config(dev, 0xF0, reg8 | 0x80);
+
+	res0 = find_resource(dev, PNP_IDX_IO0);
+
+#if GENERIC_UART_SETUP
+	init_uart8250(res0->base, uart);
+#else
+	lcr = 0x3; // 8 data bits, 1 stop bit, no parity
+	divisor = 115200/(uart->baud ? uart->baud: 1);
+
+	outb(0x00,                  res0->base + UART_IER); // disable intr
+	outb(0x01,                  res0->base + UART_FCR); // enable FIFO
+	outb(lcr,                   res0->base + UART_LCR);
+	scx200_superio_SP_set_bank(res0->base, 1);
+	outb(divisor & 0xFF,        res0->base + UART_DLL);
+	outb((divisor >> 8) & 0xFF, res0->base + UART_DLM);
+	scx200_superio_SP_set_bank(res0->base, 0);
+	outb(res0->base + UART_MCR, 0xb); // DTR, RTS, AO2
+#endif
+}
+
+static void scx200_superio_init(device_t dev)
+{
+	struct superio_NSC_scx200_config *conf;
+	struct resource *res0;
+
+	printk_debug("%s: dev %d, enabled %d\n", __FUNCTION__,
+		dev->path.u.pnp.device, dev->enabled);
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	conf = dev->chip_info;
+
+	switch (dev->path.u.pnp.device) {
+		case SCX200_SIO_RTC:
+			scx200_superio_RTC_setup(dev);
+			break;
+
+		case SCX200_SIO_SP1:
+			scx200_superio_SP_setup(dev, &conf->com1);
+			break;
+
+		case SCX200_SIO_SP2:
+			scx200_superio_SP_setup(dev, &conf->com2);
+			break;
+
+		case SCX200_SIO_SP3:
+			scx200_superio_SP_setup(dev, &conf->com3);
+			nanodisplay_clrscr();
+			nanodisplay_write(0, "SecureBIOS stage1", 0);
+			break;
+
+		default:
+			break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = scx200_superio_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+  { &ops, SCX200_SIO_RTC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0,
+    { 0x07FE, 0 }, { 0x07FE, 0 }, },
+  { &ops, SCX200_SIO_SWC,  PNP_IO0 | PNP_IRQ0,
+    { 0xFFF0, 0 }, },
+  { &ops, SCX200_SIO_SP3,  PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1,
+    { 0x07F8, 0 }, },
+  { &ops, SCX200_SIO_SP1,  PNP_IO0 | PNP_IRQ0,
+    { 0x07F8, 0 }, },
+  { &ops, SCX200_SIO_NA,
+    },
+  { &ops, SCX200_SIO_ACB1, PNP_IO0 | PNP_IRQ0,
+    { 0xFFF8, 0 }, },
+  { &ops, SCX200_SIO_ACB2, PNP_IO0 | PNP_IRQ0,
+    { 0xFFF8, 0 }, },
+  { &ops, SCX200_SIO_PP,   PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
+    { 0x03F8, 0 }, },
+  { &ops, SCX200_SIO_SP2,  PNP_IO0 | PNP_IRQ0,
+    { 0x07F8, 0 }, },
+};
+
+static void scx200_superio_enable_dev(struct device *dev)
+{
+	printk_debug("%s: dev %d\n", __FUNCTION__, dev->path.u.pnp.device);
+
+	pnp_enable_devices(dev, &ops,
+		sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_NSC_scx200_ops = {
+  CHIP_NAME("NSC scx200 superio")
+  .enable_dev = scx200_superio_enable_dev,
+};
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/superio/NSC/scx200/scx200_superio_early_serial.c LinuxBIOSv2/src/superio/NSC/scx200/scx200_superio_early_serial.c
--- LinuxBIOSv2.orig/src/superio/NSC/scx200/scx200_superio_early_serial.c	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/superio/NSC/scx200/scx200_superio_early_serial.c	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,70 @@
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pnp_def.h>
+#include <delay.h>
+#include "scx200_superio.h"
+
+static void scx200_superio_enable_serial(device_t dev, unsigned iobase)
+{
+	uint8_t reg8;
+
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+
+	// enable serial port bank switching
+	reg8 = pnp_read_config(dev, 0xF0);
+	pnp_write_config(dev, 0xF0, reg8 | 0x80);
+}
+
+static void scx200_set_port_bank(int port, int bank)
+{
+	uint8_t reg8;
+	reg8 = inb(port + UART_LCR);
+	switch (bank) {
+		case 0:
+			break;
+		case 1:
+			reg8 |= 0x80;
+			break;
+		case 2:
+			reg8 |= 0xe0;
+			break;
+		case 3:
+			reg8 |= 0xe4;
+			break;
+		default:
+			break;
+	}
+	outb(reg8, port + UART_LCR);
+}
+
+static void scx200_setup_port(int port, int baudrate)
+{
+	uint8_t  lcr;
+	uint16_t divisor;
+	lcr = 0x3; // 8 data bits, 1 stop bit, no parity
+        divisor = 115200/(baudrate ? baudrate: 1);
+        outb(0x00,                  port + UART_IER); // disable intr
+        outb(0x01,                  port + UART_FCR); // enable FIFO
+        outb(lcr,                   port + UART_LCR);
+	scx200_set_port_bank(port, 1);
+        outb(divisor & 0xFF,        port + UART_DLL);
+        outb((divisor >> 8) & 0xFF, port + UART_DLM);
+	scx200_set_port_bank(port, 0);
+	outb(port + UART_MCR, 0xb); // DTR, RTS, AO2
+}
+
+void scx200_init_early_serial(void)
+{
+	// PNP enable serial HW
+	scx200_superio_enable_serial(SCX200_SIO_SP1_DEV, SCX200_SIO_SP1_PORT);
+	scx200_superio_enable_serial(SCX200_SIO_SP3_DEV, SCX200_SIO_SP3_PORT);
+
+	// setup baudrate etc.
+	scx200_setup_port(SCX200_SIO_SP1_PORT, TTYS0_BAUD);
+	scx200_setup_port(SCX200_SIO_SP3_PORT, 19200);
+}
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/superio/NSC/scx200/scx200_superio_early_serial.h LinuxBIOSv2/src/superio/NSC/scx200/scx200_superio_early_serial.h
--- LinuxBIOSv2.orig/src/superio/NSC/scx200/scx200_superio_early_serial.h	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/superio/NSC/scx200/scx200_superio_early_serial.h	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,14 @@
+#ifndef SCX200_SUPERIO_EARLY_SERIAL
+#define SCX200_SUPERIO_EARLY_SERIAL
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+// init routine
+extern void scx200_init_early_serial(void);
+
+// read routine
+extern char scx200_rx_port_ch(int port);
+
+// write routines
+extern void scx200_tx_port_ch(int port, char ch);
+extern void scx200_tx_port_str(int port, char *str);
+#endif
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/src/superio/NSC/scx200/scx200_superio.h LinuxBIOSv2/src/superio/NSC/scx200/scx200_superio.h
--- LinuxBIOSv2.orig/src/superio/NSC/scx200/scx200_superio.h	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/src/superio/NSC/scx200/scx200_superio.h	2006-02-21 18:24:11.000000000 +0100
@@ -0,0 +1,43 @@
+#ifndef _SCX200_SIO_
+#define _SCX200_SIO_
+
+/* Author: Per Hallsmark <per.hallsmark@t2data.se> */
+
+#define SCX200_SIO_RTC       0x000
+#define SCX200_SIO_SWC       0x001
+#define SCX200_SIO_SP3       0x002
+#define SCX200_SIO_SP1       0x003
+#define SCX200_SIO_NA        0x004
+#define SCX200_SIO_ACB1      0x005
+#define SCX200_SIO_ACB2      0x006
+#define SCX200_SIO_PP        0x007
+#define SCX200_SIO_SP2       0x008
+
+#define SCX200_SIO_SWC_PORT  0x0E8
+#define SCX200_SIO_SP1_PORT  0x3F8
+#define SCX200_SIO_SP2_PORT  0x2F8
+#define SCX200_SIO_SP3_PORT  0x3E8
+
+#define SCX200_SIO_SP1_DEV PNP_DEV(PNP_CFGADDR, SCX200_SIO_SP1)
+#define SCX200_SIO_SP2_DEV PNP_DEV(PNP_CFGADDR, SCX200_SIO_SP2)
+#define SCX200_SIO_SP3_DEV PNP_DEV(PNP_CFGADDR, SCX200_SIO_SP3)
+
+/* Data */
+#define UART_RX  0x00
+#define UART_TX  0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+#endif /* _SCX200_SIO_ */
diff --exclude-from=excludes -urwN LinuxBIOSv2.orig/targets/nano-system/ncg266/Config.lb LinuxBIOSv2/targets/nano-system/ncg266/Config.lb
--- LinuxBIOSv2.orig/targets/nano-system/ncg266/Config.lb	1970-01-01 01:00:00.000000000 +0100
+++ LinuxBIOSv2/targets/nano-system/ncg266/Config.lb	2006-02-24 15:44:32.000000000 +0100
@@ -0,0 +1,25 @@
+target ncg266
+mainboard nano-system/ncg266
+
+option ROM_SIZE=0x40000
+
+option CC="gcc -m32"
+#option CC="/opt/nanodev/toolchains/prov1/gcc-3.4.4-glibc-2.3.5/i686-unknown-linux-gnu/bin/i686-unknown-linux-gnu-gcc -m32"
+
+romimage "normal"
+	option USE_FALLBACK_IMAGE=0
+	option ROM_IMAGE_SIZE=0x10000
+	option LINUXBIOS_EXTRA_VERSION=".1Normal"
+	payload ../../rtl8139--filo.zelf
+#	payload ../../filo.zelf
+end
+buildrom ./linuxbios.rom ROM_SIZE "normal"
+
+#romimage "fallback" 
+#	option USE_FALLBACK_IMAGE=1
+#	option ROM_IMAGE_SIZE=0x10000
+#	option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+#	payload ../../filo.zelf
+#end
+#
+#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
Binary files LinuxBIOSv2.orig/targets/nano-system/ncg266/rtl8139--filo.zelf and LinuxBIOSv2/targets/nano-system/ncg266/rtl8139--filo.zelf differ
Binary files LinuxBIOSv2.orig/util/newconfig/yappsrt.pyc and LinuxBIOSv2/util/newconfig/yappsrt.pyc differ
