Frank Vibrans III (frank.vibrans@amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/135
-gerrit
commit ca8ec0be0a6d2218eae4f3b22f76dfad27d98a41 Author: efdesign98 efdesign98@gmail.com Date: Thu Aug 4 21:24:41 2011 -0600
AMD F14 southbridge update
This change adds the southbridge related code to support the update of the AMD Family14 cpus to the rec C0 level. Some of the changes reside in mainboard folders but they reference changed files in the southbridge folder so they are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e Signed-off-by: Frank Vibrans frank.vibrans@amd.com Signed-off-by: efdesign98 efdesign98@gmail.com --- src/mainboard/advansus/a785e-i/pmio.h | 8 +- src/mainboard/amd/torpedo/BiosCallOuts.c | 3 +- src/mainboard/amd/torpedo/Makefile.inc | 2 - src/mainboard/amd/torpedo/cfg.c | 307 ------- src/mainboard/amd/torpedo/cfg.h | 1242 --------------------------- src/southbridge/amd/cimx/sb800/Amd.h | 2 +- src/southbridge/amd/cimx/sb800/SbEarly.h | 18 +- src/southbridge/amd/cimx/sb800/bootblock.c | 33 + src/southbridge/amd/cimx/sb800/cfg.c | 8 + src/southbridge/amd/cimx/sb800/early.c | 306 +++++++ src/southbridge/amd/cimx/sb800/late.c | 27 +- src/southbridge/amd/cimx/sb800/lpc.c | 8 +- src/southbridge/amd/cimx/sb800/smbus.c | 19 + src/southbridge/amd/cimx/sb900/Makefile.inc | 4 +- src/southbridge/amd/cimx/sb900/cfg.c | 307 +++++++ src/southbridge/amd/cimx/sb900/cfg.h | 1242 +++++++++++++++++++++++++++ src/vendorcode/amd/cimx/sb800/AMDSBLIB.h | 3 +- 17 files changed, 1978 insertions(+), 1561 deletions(-)
diff --git a/src/mainboard/advansus/a785e-i/pmio.h b/src/mainboard/advansus/a785e-i/pmio.h index 78ab6e9..1d36ff9 100644 --- a/src/mainboard/advansus/a785e-i/pmio.h +++ b/src/mainboard/advansus/a785e-i/pmio.h @@ -20,8 +20,12 @@ #ifndef _PMIO_H_ #define _PMIO_H_
-#define PM_INDEX 0xCD6 -#define PM_DATA 0xCD7 +#ifndef PM_INDEX + #define PM_INDEX 0xCD6 +#endif +#ifndef PM_DATA + #define PM_DATA 0xCD7 +#endif #define PM2_INDEX 0xCD0 #define PM2_DATA 0xCD1
diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index ff55e24..083bc25 100755 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -525,7 +525,6 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT32 GpioMmioAddr; UINT8 Data8; UINT16 Data16; - UINT8 TempData8;
FcnData = Data; MemData = ConfigPtr; @@ -598,7 +597,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
if (ResetInfo->ResetControl == DeassertSlotReset) { - if (ResetInfo->ResetId & BIT2+BIT3) { //de-assert + if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45); if (Data8 & BIT7) { diff --git a/src/mainboard/amd/torpedo/Makefile.inc b/src/mainboard/amd/torpedo/Makefile.inc index 1a7dc95..986d90d 100755 --- a/src/mainboard/amd/torpedo/Makefile.inc +++ b/src/mainboard/amd/torpedo/Makefile.inc @@ -36,7 +36,6 @@ romstage-y += agesawrapper.c romstage-y += dimmSpd.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c -romstage-y += cfg.c romstage-y += gpio.c
ramstage-y += buildOpts.c @@ -44,7 +43,6 @@ ramstage-y += agesawrapper.c ramstage-y += dimmSpd.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c -ramstage-y += cfg.c
ramstage-y += reset.c ramstage-y += pmio.c diff --git a/src/mainboard/amd/torpedo/cfg.c b/src/mainboard/amd/torpedo/cfg.c deleted file mode 100755 index 809b7a3..0000000 --- a/src/mainboard/amd/torpedo/cfg.c +++ /dev/null @@ -1,307 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <string.h> -#include "SbPlatform.h" -#include "cfg.h" -#include <console/console.h> /* printk */ - - -/** - * @brief South Bridge CIMx configuration - * - * should be called before exeucte CIMx function. - * this function will be called in romstage and ramstage. - */ -void sb900_cimx_config(AMDSBCFG *sb_config) -{ - if (!sb_config) { - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n"); - return; - } - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n"); - memset(sb_config, 0, sizeof(AMDSBCFG)); - - /* static Build Parameters */ - sb_config->BuildParameters.BiosSize = BIOS_SIZE; - sb_config->BuildParameters.LegacyFree = LEGACY_FREE; - sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level - - /* Turn on CDROM and HDD Power */ - sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; - - // header - sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; - - // Build Parameters - sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE; // Internal Option - sb_config->BuildParameters.UsbMsi = USB_MSI; // Internal Option - sb_config->BuildParameters.HdAudioMsi = HDAUDIO_MSI; // Internal Option - sb_config->BuildParameters.LpcMsi = LPC_MSI; // Internal Option - sb_config->BuildParameters.PcibMsi = PCIB_MSI; // Internal Option - sb_config->BuildParameters.AbMsi = AB_MSI; // Internal Option - sb_config->BuildParameters.GecShadowRomBase = GEC_SHADOWROM_BASE; // Board Level - sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; // Board Level - sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; // Board Level - sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; // Board Level - sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; // Board Level - sb_config->BuildParameters.OhciSsid = OHCI_SSID; // Board Level - sb_config->BuildParameters.EhciSsid = EHCI_SSID; // Board Level - sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; // Board Level - sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; // Board Level - sb_config->BuildParameters.IdeSsid = IDE_SSID; // Board Level - sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; // Board Level - sb_config->BuildParameters.LpcSsid = LPC_SSID; // Board Level - // sb_config->BuildParameters.PCIBSsid = PCIB_SSID; // Field Retired - - // - // Common Function - // - sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; // External Option - sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_IDE_COMBMD_PRISEC_OPT; // External Option - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = SATA_IDECOMBINED_MODE; // External Option - sb_config->S3Resume = 0; // CIMx Internal Used - sb_config->SpreadSpectrum = INCHIP_SPREAD_SPECTRUM; // Board Level - sb_config->NbSbGen2 = INCHIP_NB_SB_GEN2; // External Option - sb_config->GppGen2 = INCHIP_GPP_GEN2; // External Option - sb_config->GppMemWrImprove = INCHIP_GPP_MEMORY_WRITE_IMPROVE; // Internal Option - sb_config->S4Resume = 0; // CIMx Internal Used - sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; // INCHIP_SATA_MODE // External Option - sb_config->SataIdeMode = INCHIP_IDE_MODE; // External Option - sb_config->sdConfig = SB_SD_CONFIG; // External Option - sb_config->sdSpeed = SB_SD_SPEED; // Internal Option - sb_config->sdBitwidth = SB_SD_BITWIDTH; // Internal Option - sb_config->SataDisUnusedIdePChannel = SATA_DISUNUSED_IDE_P_CHANNEL; // External Option - sb_config->SataDisUnusedIdeSChannel = SATA_DISUNUSED_IDE_S_CHANNEL; // External Option - sb_config->IdeDisUnusedIdePChannel = IDE_DISUNUSED_IDE_P_CHANNEL; // External Option - sb_config->IdeDisUnusedIdeSChannel = IDE_DISUNUSED_IDE_S_CHANNEL; // External Option - sb_config->SATAESPPORT.SataEspPort.PORT0 = SATA_ESP_PORT0; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT1 = SATA_ESP_PORT1; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT2 = SATA_ESP_PORT2; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT3 = SATA_ESP_PORT3; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT4 = SATA_ESP_PORT4; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT5 = SATA_ESP_PORT5; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT6 = SATA_ESP_PORT6; // Board Level - sb_config->SATAESPPORT.SataEspPort.PORT7 = SATA_ESP_PORT7; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT0 = SATA_PORT_POWER_PORT0; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT1 = SATA_PORT_POWER_PORT1; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT2 = SATA_PORT_POWER_PORT2; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT3 = SATA_PORT_POWER_PORT3; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT4 = SATA_PORT_POWER_PORT4; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT5 = SATA_PORT_POWER_PORT5; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT6 = SATA_PORT_POWER_PORT6; // Board Level - sb_config->SATAPORTPOWER.SataPortPower.PORT7 = SATA_PORT_POWER_PORT7; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT0 = SATA_PORTMODE_PORT0; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT1 = SATA_PORTMODE_PORT1; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT2 = SATA_PORTMODE_PORT2; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT3 = SATA_PORTMODE_PORT3; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT4 = SATA_PORTMODE_PORT4; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT5 = SATA_PORTMODE_PORT5; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT6 = SATA_PORTMODE_PORT6; // Board Level - sb_config->SATAPORTMODE.SataPortMd.PORT7 = SATA_PORTMODE_PORT7; // Board Level - sb_config->SataAggrLinkPmCap = INCHIP_SATA_AGGR_LINK_PM_CAP; // Internal Option - sb_config->SataPortMultCap = INCHIP_SATA_PORT_MULT_CAP; // Internal Option - sb_config->SataClkAutoOff = INCHIP_SATA_CLK_AUTO_OFF; // External Option - sb_config->SataPscCap = INCHIP_SATA_PSC_CAP; // External Option - sb_config->SataFisBasedSwitching = INCHIP_SATA_FIS_BASE_SW; // External Option - sb_config->SataCccSupport = INCHIP_SATA_CCC_SUPPORT; // External Option - sb_config->SataSscCap = INCHIP_SATA_SSC_CAP; // External Option - sb_config->SataMsiCapability = INCHIP_SATA_MSI_CAP; // Internal Option - sb_config->SataForceRaid = INCHIP_SATA_FORCE_RAID5; // Internal Option - sb_config->SataTargetSupport8Device = CIMXSB_SATA_TARGET_8DEVICE_CAP; // External Option - sb_config->SataDisableGenericMode = SATA_DISABLE_GENERIC_MODE_CAP;// External Option - sb_config->SataAhciEnclosureManagement = SATA_AHCI_ENCLOSURE_CAP; // Internal Option - sb_config->SataSgpio0 = SATA_GPIO_0_CAP; // External Option - sb_config->SataSgpio1 = SATA_GPIO_1_CAP; // External Option - sb_config->SataPhyPllShutDown = SATA_PHY_PLL_SHUTDOWN; // External Option - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT0 = SATA_HOTREMOVEL_ENH_PORT0; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT1 = SATA_HOTREMOVEL_ENH_PORT1; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT2 = SATA_HOTREMOVEL_ENH_PORT2; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT3 = SATA_HOTREMOVEL_ENH_PORT3; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT4 = SATA_HOTREMOVEL_ENH_PORT4; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT5 = SATA_HOTREMOVEL_ENH_PORT5; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT6 = SATA_HOTREMOVEL_ENH_PORT6; // Board Level - sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT7 = SATA_HOTREMOVEL_ENH_PORT7; // Board Level - // USB - sb_config->USBMODE.UsbMode.Ohci1 = INCHIP_USB_OHCI1_CINFIG; // External Option - sb_config->USBMODE.UsbMode.Ehci1 = INCHIP_USB_EHCI1_CINFIG; // Internal Option* - sb_config->USBMODE.UsbMode.Ohci2 = INCHIP_USB_OHCI2_CINFIG; // External Option - sb_config->USBMODE.UsbMode.Ehci2 = INCHIP_USB_EHCI2_CINFIG; // Internal Option* - sb_config->USBMODE.UsbMode.Ohci3 = INCHIP_USB_OHCI3_CINFIG; // External Option - sb_config->USBMODE.UsbMode.Ehci3 = INCHIP_USB_EHCI3_CINFIG; // Internal Option* - sb_config->USBMODE.UsbMode.Ohci4 = INCHIP_USB_OHCI4_CINFIG; // External Option - // GEC - sb_config->GecConfig = INCHIP_GEC_CONTROLLER; // External Option - sb_config->IrConfig = SB_IR_CONTROLLER; // External Option - sb_config->XhciSwitch = SB_XHCI_SWITCH; // External Option - // Azalia - sb_config->AzaliaController = INCHIP_AZALIA_CONTROLLER; // External Option - sb_config->AzaliaPinCfg = INCHIP_AZALIA_PIN_CONFIG; // Board Level - sb_config->FrontPanelDetected = INCHIP_FRONT_PANEL_DETECTED; // Board Level - sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_PIN_CONFIG; // Board Level - sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; // Board Level - sb_config->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr = NULL; // Board Level - sb_config->AnyHT200MhzLink = INCHIP_ANY_HT_200MHZ_LINK; // Internal Option - sb_config->HpetTimer = SB_HPET_TIMER; // External Option - sb_config->AzaliaSnoop = INCHIP_AZALIA_SNOOP; // Internal Option* - // Generic - sb_config->NativePcieSupport = INCHIP_NATIVE_PCIE_SUPPOORT; // External Option - // USB - sb_config->UsbPhyPowerDown = INCHIP_USB_PHY_POWER_DOWN; // External Option - sb_config->PcibClkStopOverride = INCHIP_PCIB_CLK_STOP_OVERRIDE;// Internal Option - // sb_config->HpetMsiDis = 0; // Field Retired - // sb_config->ResetCpuOnSyncFlood = 0; // Field Retired - // sb_config->PcibAutoClkCtr = 0; // Field Retired - sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level - sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level - sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used - sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used - sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = 0; // CIMx Internal Used - // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired - sb_config->PORTCONFIG[1].PortCfg.PortPresent = SB_GPP_PORT1; // Board Level - sb_config->PORTCONFIG[1].PortCfg.PortDetected = 0; // CIMx Internal Used - sb_config->PORTCONFIG[1].PortCfg.PortIsGen2 = 0; // CIMx Internal Used - sb_config->PORTCONFIG[1].PortCfg.PortHotPlug = 0; // CIMx Internal Used - // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired - sb_config->PORTCONFIG[2].PortCfg.PortPresent = SB_GPP_PORT2; // Board Level - sb_config->PORTCONFIG[2].PortCfg.PortDetected = 0; // CIMx Internal Used - sb_config->PORTCONFIG[2].PortCfg.PortIsGen2 = 0; // CIMx Internal Used - sb_config->PORTCONFIG[2].PortCfg.PortHotPlug = 0; // CIMx Internal Used - // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired - sb_config->PORTCONFIG[3].PortCfg.PortPresent = SB_GPP_PORT3; // Board Level - sb_config->PORTCONFIG[3].PortCfg.PortDetected = 0; // CIMx Internal Used - sb_config->PORTCONFIG[3].PortCfg.PortIsGen2 = 0; // CIMx Internal Used - sb_config->PORTCONFIG[3].PortCfg.PortHotPlug = 0; // CIMx Internal Used - // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired - sb_config->GppLinkConfig = INCHIP_GPP_LINK_CONFIG; // External Option - sb_config->GppFoundGfxDev = 0; // CIMx Internal Used - sb_config->GppFunctionEnable = SB_GPP_CONTROLLER; // External Option - sb_config->GppUnhidePorts = INCHIP_GPP_UNHIDE_PORTS; // Internal Option - sb_config->GppPortAspm = INCHIP_GPP_PORT_ASPM; // Internal Option - sb_config->GppLaneReversal = INCHIP_GPP_LANEREVERSAL; // External Option - sb_config->AlinkPhyPllPowerDown = INCHIP_ALINK_PHY_PLL_POWER_DOWN; // External Option - sb_config->GppPhyPllPowerDown = INCHIP_GPP_PHY_PLL_POWER_DOWN;// External Option - sb_config->GppDynamicPowerSaving = INCHIP_GPP_DYNAMIC_POWER_SAVING; // External Option - sb_config->PcieAER = INCHIP_PCIE_AER; // External Option - sb_config->PcieRAS = INCHIP_PCIE_RAS; // External Option - sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option - sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option - sb_config->sdbEnable = 0; // CIMx Internal Used - sb_config->TempMMIO = NULL; // CIMx Internal Used - // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired - sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option - sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option - sb_config->SbPcieOrderRule = INCHIP_SB_PCIE_ORDER_RULE; // External Option - sb_config->AcDcMsg = INCHIP_ACDC_MSG; // Internal Option - sb_config->TimerTickTrack = INCHIP_TIMER_TICK_TRACK; // Internal Option - sb_config->ClockInterruptTag = INCHIP_CLOCK_INTERRUPT_TAG; // Internal Option - sb_config->OhciTrafficHanding = INCHIP_OHCI_TRAFFIC_HANDING; // Internal Option - sb_config->EhciTrafficHanding = INCHIP_EHCI_TRAFFIC_HANDING; // Internal Option - sb_config->FusionMsgCMultiCore = INCHIP_FUSION_MSGC_MULTICORE; // Internal Option - sb_config->FusionMsgCStage = INCHIP_FUSION_MSGC_STAGE; // Internal Option - sb_config->ALinkClkGateOff = INCHIP_ALINK_CLK_GATE_OFF; // External Option - sb_config->BLinkClkGateOff = INCHIP_BLINK_CLK_GATE_OFF; // External Option - // sb_config->sdb = 0; // Field Retired - sb_config->GppGen2Strap = 0; // CIMx Internal Used - sb_config->SlowSpeedABlinkClock = INCHIP_SLOW_SPEED_ABLINK_CLOCK; // Internal Option - sb_config->DYNAMICGECROM.DynamicGecRomAddress_Ptr = NULL; // Board Level - sb_config->AbClockGating = INCHIP_AB_CLOCK_GATING; // External Option - sb_config->GppClockGating = INCHIP_GPP_CLOCK_GATING; // External Option - sb_config->L1TimerOverwrite = INCHIP_L1_TIMER_OVERWRITE; // Internal Option - // sb_config->UmiLinkWidth = 0; // Field Retired - sb_config->UmiDynamicSpeedChange = INCHIP_UMI_DYNAMIC_SPEED_CHANGE; // Internal Option - // sb_config->PcieRefClockOverclocking = 0; // Field Retired - sb_config->SbAlinkGppTxDriverStrength = INCHIP_ALINK_GPP_TX_DRV_STRENGTH; // Internal Option - sb_config->PwrFailShadow = 0x02; // Board Level - sb_config->StressResetMode = INCHIP_STRESS_RESET_MODE; // Internal Option - sb_config->hwm.fanSampleFreqDiv = 0x03; // Board Level - sb_config->hwm.hwmSbtsiAutoPoll = 1; // Board Level - - /* General */ - sb_config->PciClks = SB_PCI_CLOCK_RESERVED; - sb_config->hwm.hwmEnable = 0x0; - -#ifndef __PRE_RAM__ - /* ramstage cimx config here */ - if (!sb_config->StdHeader.CALLBACK.CalloutPtr) { - sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry; - } - - //sb_config-> -#endif //!__PRE_RAM__ - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); -} - -void SbPowerOnInit_Config(AMDSBCFG *sb_config) -{ - if (!sb_config) { - printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n"); - return; - } - printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n"); - memset(sb_config, 0, sizeof(AMDSBCFG)); - - // Set the build parameters - sb_config->BuildParameters.BiosSize = BIOS_SIZE; // Field Retired - sb_config->BuildParameters.LegacyFree = SBCIMx_LEGACY_FREE; // Board Level - sb_config->BuildParameters.SpiSpeed = SBCIMX_SPI_SPEED; // Internal Option - sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option - // sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired - sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option - sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internla Option - sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level - sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.GecShadowRomBase = GEC_ROM_SHADOW_ADDRESS; // Board Level - sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level - sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; // Board Level - sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; // Board Level - sb_config->SATAMODE.SataMode.SataController = INCHIP_SATA_CONTROLLER; // External Option - sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_COMBINE_MODE_CHANNEL;// External Option - sb_config->SATAMODE.SataMode.SataSetMaxGen2 = SATA_MAX_GEN2_MODE; // External Option - sb_config->SATAMODE.SataMode.SataIdeCombinedMode= SATA_COMBINE_MODE; // External Option - sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option - sb_config->NbSbGen2 = NB_SB_GEN2; // External Option - sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option - sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level - sb_config->sdbEnable = 0; // CIMx Internal Used - sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option - - printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - End.\n"); -} - - diff --git a/src/mainboard/amd/torpedo/cfg.h b/src/mainboard/amd/torpedo/cfg.h deleted file mode 100755 index 6565d6c..0000000 --- a/src/mainboard/amd/torpedo/cfg.h +++ /dev/null @@ -1,1242 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#ifndef _SB900_CFG_H_ -#define _SB900_CFG_H_ - -#include <stdint.h> - - -/** - * @section BIOSSize BIOSSize - * @li <b>0</b> - 1M - * @li <b>1</b> - 2M - * @li <b>3</b> - 4M - * @li <b>7</b> - 8M - * In Hudson-2, default ROM size is 1M Bytes, if your platform - * ROM bigger then 1M you have to set the ROM size outside CIMx - * module and before AGESA module get call. - */ -#define BIOS_SIZE_1M 0 -#define BIOS_SIZE_2M 1 -#define BIOS_SIZE_4M 3 -#define BIOS_SIZE_8M 7 - -#ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 - #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 - #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 - #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 - #define BIOS_SIZE BIOS_SIZE_8M -#endif -#endif - -/** - * @section SBCIMx_LEGACY_FREE SBCIMx_LEGACY_FREE - * @li <b>1</b> - Legacy free enable - * @li <b>0</b> - Legacy free disable - */ -#ifndef SBCIMx_LEGACY_FREE - #define SBCIMx_LEGACY_FREE 0 -#endif - -/** - * @section SpiSpeed - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#ifndef SBCIMX_SPI_SPEED - #define SBCIMX_SPI_SPEED 0 -#endif - -/** - * @section SpiFastSpeed - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#ifndef SBCIMX_SPI_FASTSPEED - #define SBCIMX_SPI_FASTSPEED 0 -#endif - -/** - * @section SpiMode - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#ifndef SBCIMX_SPI_MODE - #define SBCIMX_SPI_MODE 0 -#endif - -/** - * @section SpiBurstWrite - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#ifndef SBCIMX_SPI_BURST_WRITE - #define SBCIMX_SPI_BURST_WRITE 0 -#endif - -/** - * @section INCHIP_EC_KBD INCHIP_EC_KBD - * @li <b>0</b> - Use SIO PS/2 function. - * @li <b>1</b> - Use EC PS/2 function. - */ -#ifndef INCHIP_EC_KBD - #define INCHIP_EC_KBD 0 -#endif - -/** - * @section INCHIP_EC_CHANNEL10 INCHIP_EC_CHANNEL10 - * @li <b>0</b> - EC controller NOT support Channel10 - * @li <b>1</b> - EC controller support Channel10. - */ -#ifndef INCHIP_EC_CHANNEL10 - #define INCHIP_EC_CHANNEL10 1 -#endif - -/** - * @section Smbus0BaseAddress - */ -// #ifndef SMBUS0_BASE_ADDRESS -// #define SMBUS0_BASE_ADDRESS 0xB00 -// #endif - -/** - * @section Smbus1BaseAddress - */ -// #ifndef SMBUS1_BASE_ADDRESS -// #define SMBUS1_BASE_ADDRESS 0xB21 -// #endif - -/** - * @section SioPmeBaseAddress - */ -// #ifndef SIO_PME_BASE_ADDRESS -// #define SIO_PME_BASE_ADDRESS 0xE00 -// #endif - -/** - * @section WatchDogTimerBase - */ -// #ifndef WATCHDOG_TIMER_BASE_ADDRESS -// #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000 -// #endif - -/** - * @section GecShadowRomBase - */ -#ifndef GEC_ROM_SHADOW_ADDRESS - #define GEC_ROM_SHADOW_ADDRESS 0xFED61000 -#endif - -/** - * @section SpiRomBaseAddress - */ -// #ifndef SPI_BASE_ADDRESS -// #define SPI_BASE_ADDRESS 0xFEC10000 -// #endif - -/** - * @section AcpiPm1EvtBlkAddr - */ -// #ifndef PM1_EVT_BLK_ADDRESS -// #define PM1_EVT_BLK_ADDRESS 0x400 -// #endif - -/** - * @section AcpiPm1CntBlkAddr - */ -// #ifndef PM1_CNT_BLK_ADDRESS -// #define PM1_CNT_BLK_ADDRESS 0x404 -// #endif - -/** - * @section AcpiPmTmrBlkAddr - */ -// #ifndef PM1_TMR_BLK_ADDRESS -// #define PM1_TMR_BLK_ADDRESS 0x408 -// #endif - -/** - * @section CpuControlBlkAddr - */ -// #ifndef CPU_CNT_BLK_ADDRESS -// #define CPU_CNT_BLK_ADDRESS 0x410 -// #endif - -/** - * @section AcpiGpe0BlkAddr - */ -// #ifndef GPE0_BLK_ADDRESS -// #define GPE0_BLK_ADDRESS 0x420 -// #endif - -/** - * @section SmiCmdPortAddr - */ -// #ifndef SMI_CMD_PORT -// #define SMI_CMD_PORT 0xB0 -// #endif - -/** - * @section AcpiPmaCntBlkAddr - */ -// #ifndef ACPI_PMA_CNT_BLK_ADDRESS -// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 -// #endif - -/** - * @section SataController - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#ifndef INCHIP_SATA_CONTROLLER - #define INCHIP_SATA_CONTROLLER 1 -#endif - -/** - * @section SataIdeCombMdPriSecOpt - * @li <b>0</b> - Primary - * @li <b>1</b> - Secondary<TD></TD> - * Sata Controller set as primary or - * secondary while Combined Mode is enabled - */ -#ifndef SATA_COMBINE_MODE_CHANNEL - #define SATA_COMBINE_MODE_CHANNEL 0 -#endif - -/** - * @section SataSetMaxGen2 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - * SataController Set to Max Gen2 mode - */ -#ifndef SATA_MAX_GEN2_MODE - #define SATA_MAX_GEN2_MODE 0 -#endif - -/** - * @section SataIdeCombinedMode - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - * Sata IDE Controller set to Combined Mode - */ -#ifndef SATA_COMBINE_MODE - #define SATA_COMBINE_MODE 0 -#endif - -#define SATA_CLK_RESERVED 9 - -/** - * @section NbSbGen2 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#ifndef NB_SB_GEN2 - #define NB_SB_GEN2 1 -#endif - -/** - * @section SataInternal100Spread - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#ifndef INCHIP_SATA_INTERNAL_100_SPREAD - #define INCHIP_SATA_INTERNAL_100_SPREAD 0 -#endif - -/** - * @section Cg2Pll - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#ifndef INCHIP_CG2_PLL - #define INCHIP_CG2_PLL 0 -#endif - - - - -/** - * @section SpreadSpectrum - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - * Spread Spectrum function - */ -#define INCHIP_SPREAD_SPECTRUM 1 - -/** - * @section INCHIP_USB_CINFIG INCHIP_USB_CINFIG - * - * - Usb Ohci1 Contoller is define at BIT0 - * 0:Disable 1:Enable - * (Bus 0 Dev 18 Func0) - * - Usb Ehci1 Contoller is define at BIT1 - * 0:Disable 1:Enable - * (Bus 0 Dev 18 Func2) - * - Usb Ohci2 Contoller is define at BIT2 - * 0:Disable 1:Enable - * (Bus 0 Dev 19 Func0) - * - Usb Ehci2 Contoller is define at BIT3 - * 0:Disable 1:Enable - * (Bus 0 Dev 19 Func2) - * - Usb Ohci3 Contoller is define at BIT4 - * 0:Disable 1:Enable - * (Bus 0 Dev 22 Func0) - * - Usb Ehci3 Contoller is define at BIT5 - * 0:Disable 1:Enable - * (Bus 0 Dev 22 Func2) - * - Usb Ohci4 Contoller is define at BIT6 - * 0:Disable 1:Enable - * (Bus 0 Dev 20 Func5) - */ -#define INCHIP_USB_CINFIG 0x7F -#define INCHIP_USB_OHCI1_CINFIG 0x01 -#define INCHIP_USB_OHCI2_CINFIG 0x01 -#if CONFIG_ONBOARD_USB30 == 1 -#define INCHIP_USB_OHCI3_CINFIG 0x00 -#else -#define INCHIP_USB_OHCI3_CINFIG 0x01 -#endif -#define INCHIP_USB_OHCI4_CINFIG 0x01 -#define INCHIP_USB_EHCI1_CINFIG 0x01 -#define INCHIP_USB_EHCI2_CINFIG 0x01 -#define INCHIP_USB_EHCI3_CINFIG 0x01 - -/** - * @section INCHIP_SATA_MODE INCHIP_SATA_MODE - * @li <b>000</b> - Native IDE mode - * @li <b>001</b> - RAID mode - * @li <b>010</b> - AHCI mode - * @li <b>011</b> - Legacy IDE mode - * @li <b>100</b> - IDE->AHCI mode - * @li <b>101</b> - AHCI mode as 7804 ID (AMD driver) - * @li <b>110</b> - IDE->AHCI mode as 7804 ID (AMD driver) - */ -#define INCHIP_SATA_MODE 0 - -/** - * @section INCHIP_IDE_MODE INCHIP_IDE_MODE - * @li <b>0</b> - Legacy IDE mode - * @li <b>1</b> - Native IDE mode<TD></TD> - * ** DO NOT ALLOW SATA & IDE use same mode ** - */ -#define INCHIP_IDE_MODE 1 - -#define SATA_PORT_MULT_CAP_RESERVED 1 - -/** - * @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER - * @li <b>0</b> - Auto : Detect Azalia controller automatically. - * @li <b>1</b> - Diable : Disable Azalia controller. - * @li <b>2</b> - Enable : Enable Azalia controller. - */ -#define INCHIP_AZALIA_CONTROLLER 2 -#define AZALIA_AUTO 0 -#define AZALIA_DISABLE 1 -#define AZALIA_ENABLE 2 - -/** - * @section INCHIP_AZALIA_PIN_CONFIG INCHIP_AZALIA_PIN_CONFIG - * @li <b>0</b> - disable - * @li <b>1</b> - enable - */ -#define INCHIP_AZALIA_PIN_CONFIG 1 - -/** - * @section AZALIA_PIN_CONFIG AZALIA_PIN_CONFIG - * - * SDIN0 is define at BIT0 & BIT1 - * - 00: GPIO PIN - * - 01: Reserved - * - 10: As a Azalia SDIN pin<TD></TD> - * SDIN1 is define at BIT2 & BIT3 - * - 00: GPIO PIN - * - 01: Reserved - * - 10: As a Azalia SDIN pin<TD></TD> - * SDIN2 is define at BIT4 & BIT5 - * - 00: GPIO PIN - * - 01: Reserved - * - 10: As a Azalia SDIN pin<TD></TD> - * SDIN3 is define at BIT6 & BIT7 - * - 00: GPIO PIN - * - 01: Reserved - * - 10: As a Azalia SDIN pin - */ -#define AZALIA_PIN_CONFIG 0x2A - -/** - * @section AzaliaSnoop - * @li <b>0</b> - disable - * @li <b>1</b> - enable * - */ -#define INCHIP_AZALIA_SNOOP 0x01 - -/** - * @section NCHIP_GEC_CONTROLLER - * @li <b>0</b> - Enable * - * @li <b>1</b> - Disable - */ -#define INCHIP_GEC_CONTROLLER 0x00 - -/** - * @section SB_HPET_TIMER SB_HPET_TIMER - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SB_HPET_TIMER 1 - -/** - * @section SB_GPP_CONTROLLER SB_GPP_CONTROLLER - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SB_GPP_CONTROLLER 1 - -/** - * @section GPP_LINK_CONFIG GPP_LINK_CONFIG - * @li <b>0000</b> - Port ABCD -> 4:0:0:0 - * @li <b>0001</b> - N/A - * @li <b>0010</b> - Port ABCD -> 2:2:0:0 - * @li <b>0011</b> - Port ABCD -> 2:1:1:0 - * @li <b>0100</b> - Port ABCD -> 1:1:1:1 - */ -#define GPP_LINK_CONFIG 4 - -/** - * @section SB_GPP_PORT0 SB_GPP_PORT0 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SB_GPP_PORT0 1 - -/** - * @section SB_GPP_PORT1 SB_GPP_PORT1 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SB_GPP_PORT1 1 - -/** - * @section SB_GPP_PORT2 SB_GPP_PORT2 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SB_GPP_PORT2 1 - -/** - * @section SB_GPP_PORT3 SB_GPP_PORT3 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SB_GPP_PORT3 1 - -/** - * @section SB_IR_CONTROLLER - * @li <b>00 </b> - disable - * @li <b>01 </b> - Rx and Tx0 - * @li <b>10 </b> - Rx and Tx1 - * @li <b>11 </b> - Rx and both Tx0,Tx1 - */ -#define SB_IR_CONTROLLER 3 - -/** - * @section INCHIP_USB_PHY_POWER_DOWN - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_USB_PHY_POWER_DOWN 0 - -/** - * @section INCHIP_NATIVE_PCIE_SUPPOORT - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_NATIVE_PCIE_SUPPOORT 1 - -/** - * @section INCHIP_NB_SB_GEN2 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_NB_SB_GEN2 1 - -/** - * @section INCHIP_GPP_GEN2 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_GPP_GEN2 1 - -/** - * @section INCHIP_GPP_MEMORY_WRITE_IMPROVE - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_GPP_MEMORY_WRITE_IMPROVE 1 - -/** - * @section INCHIP_GEC_PHY_STATUS - * @li <b>0</b> - Gb PHY Mode * - * @li <b>1</b> - 100/10 PHY Mode - */ -#define INCHIP_GEC_PHY_STATUS 0 - -/** - * @section INCHIP_GEC_POWER_POLICY - * @li <b>0</b> - S3/S5 - * @li <b>1</b> - S5 - * @li <b>2</b> - S3 - * @li <b>3</b> - Never power down * - */ -#define INCHIP_GEC_POWER_POLICY 3 - -/** - * @section INCHIP_GEC_DEBUGBUS - * @li <b>0</b> - Disable * - * @li <b>1</b> - Enable - */ -#define INCHIP_GEC_DEBUGBUS 0 - -/** - * @section SATA_MAX_GEN2_MODE SATA_MAX_GEN2_MODE - * @li <b>0</b> - Disable * - * @li <b>1</b> - Enable - * SataController Set to Max Gen2 mode - */ -#define SATA_MAX_GEN2_MODE 0 - -/** - * @section INCHIP_SATA_AGGR_LINK_PM_CAP - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - * SataController Set to aggressive link PM capability - */ -#define INCHIP_SATA_AGGR_LINK_PM_CAP 0 - -/** - * @section INCHIP_SATA_PORT_MULT_CAP - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - * SataController Set to Port Multiple capability - */ -#define INCHIP_SATA_PORT_MULT_CAP 1 - -/** - * @section INCHIP_SATA_PSC_CAP - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * -*/ -#define INCHIP_SATA_PSC_CAP 0 - -/** - * @section INCHIP_SATA_SSC_CAP - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define INCHIP_SATA_SSC_CAP 0 - -/** - * @section INCHIP_SATA_CLK_AUTO_OFF - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define INCHIP_SATA_CLK_AUTO_OFF 1 - -/** - * @section INCHIP_SATA_FIS_BASE_SW - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define INCHIP_SATA_FIS_BASE_SW 1 - -/** - * @section INCHIP_SATA_CCC_SUPPORT - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define INCHIP_SATA_CCC_SUPPORT 1 - -/** - * @section INCHIP_SATA_MSI_CAP - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define INCHIP_SATA_MSI_CAP 1 - -/** - * @section CIMXSB_SATA_TARGET_8DEVICE_CAP - * @li <b>0</b> - Disable * - * @li <b>1</b> - Enable - */ -#define CIMXSB_SATA_TARGET_8DEVICE_CAP 0 - -/** - * @section SATA_DISABLE_GENERIC_MODE - * @li <b>0</b> - Disable * - * @li <b>1</b> - Enable - */ -#define SATA_DISABLE_GENERIC_MODE_CAP 0 - -/** - * @section SATA_AHCI_ENCLOSURE_CAP - * @li <b>0</b> - Disable * - * @li <b>1</b> - Enable - */ -#define SATA_AHCI_ENCLOSURE_CAP 0 - -/** - * @section SataForceRaid (RISD5 mode) - * @li <b>0</b> - Disable * - * @li <b>1</b> - Enable - */ -#define INCHIP_SATA_FORCE_RAID5 0 - -/** - * @section SATA_GPIO_0_CAP - * @li <b>0</b> - Disable * - * @li <b>1</b> - Enable - */ -#define SATA_GPIO_0_CAP 0 - -/** - * @section SATA_GPIO_1_CAP - * @li <b>0</b> - Disable * - * @li <b>1</b> - Enable - */ -#define SATA_GPIO_1_CAP 0 - -/** - * @section SataPhyPllShutDown - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define SATA_PHY_PLL_SHUTDOWN 1 - -/** - * @section ImcEnableOverWrite - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define IMC_ENABLE_OVER_WRITE 0 - -/** - * @section UsbMsi - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define USB_MSI 0 - -/** - * @section HdAudioMsi - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define HDAUDIO_MSI 0 - -/** - * @section LpcMsi - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define LPC_MSI 0 - -/** - * @section PcibMsi - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define PCIB_MSI 0 - -/** - * @section AbMsi - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define AB_MSI 0 - -/** - * @section GecShadowRomBase - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define GEC_SHADOWROM_BASE 0xFED61000 - -/** - * @section SataController - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define SATA_CONTROLLER 1 - -/** - * @section SataIdeCombMdPriSecOpt - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_IDE_COMBMD_PRISEC_OPT 0 - -/** - * @section SataIdeCombinedMode - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_IDECOMBINED_MODE 0 - -/** - * @section sdConfig - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define SB_SD_CONFIG 1 - -/** - * @section sdSpeed - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define SB_SD_SPEED 1 - -/** - * @section sdBitwidth - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable * - */ -#define SB_SD_BITWIDTH 1 - -/** - * @section SataDisUnusedIdePChannel - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_DISUNUSED_IDE_P_CHANNEL 0 - -/** - * @section SataDisUnusedIdeSChannel - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_DISUNUSED_IDE_S_CHANNEL 0 - -/** - * @section IdeDisUnusedIdePChannel - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define IDE_DISUNUSED_IDE_P_CHANNEL 0 - -/** - * @section IdeDisUnusedIdeSChannel - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define IDE_DISUNUSED_IDE_S_CHANNEL 0 - -/** - * @section IdeDisUnusedIdeSChannel - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ - -/** - * @section SataEspPort0 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_ESP_PORT0 0 - -/** - * @section SataEspPort1 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_ESP_PORT1 0 - -/** - * @section SataEspPort2 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_ESP_PORT2 0 - -/** - * @section SataEspPort3 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_ESP_PORT3 0 - -/** - * @section SataEspPort4 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_ESP_PORT4 0 - -/** - * @section SataEspPort5 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_ESP_PORT5 0 - -/** - * @section SataEspPort6 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_ESP_PORT6 0 - -/** - * @section SataEspPort7 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_ESP_PORT7 0 - -/** - * @section SataPortPower0 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORT_POWER_PORT0 0 - -/** - * @section SataPortPower1 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORT_POWER_PORT1 0 - -/** - * @section SataPortPower2 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORT_POWER_PORT2 0 - -/** - * @section SataPortPower3 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORT_POWER_PORT3 0 - -/** - * @section SataPortPower4 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORT_POWER_PORT4 0 - -/** - * @section SataPortPower5 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORT_POWER_PORT5 0 - -/** - * @section SataPortPower6 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORT_POWER_PORT6 0 - -/** - * @section SataPortPower7 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORT_POWER_PORT7 0 - -/** - * @section SataPortMd0 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORTMODE_PORT0 3 - -/** - * @section SataPortMd1 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORTMODE_PORT1 3 - -/** - * @section SataPortMd2 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORTMODE_PORT2 3 - -/** - * @section SataPortMd3 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORTMODE_PORT3 3 - -/** - * @section SataPortMd4 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORTMODE_PORT4 0 - -/** - * @section SataPortMd5 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORTMODE_PORT5 0 - -/** - * @section SataPortMd6 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORTMODE_PORT6 0 - -/** - * @section SataPortMd7 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_PORTMODE_PORT7 0 - -/** - * @section SataHotRemovelEnh0 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT0 0 - -/** - * @section SataHotRemovelEnh1 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT1 0 - -/** - * @section SataHotRemovelEnh2 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT2 0 - -/** - * @section SataHotRemovelEnh3 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT3 0 - -/** - * @section SataHotRemovelEnh4 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT4 0 - -/** - * @section SataHotRemovelEnh5 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT5 0 - -/** - * @section SataHotRemovelEnh6 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT6 0 - -/** - * @section SataHotRemovelEnh7 - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define SATA_HOTREMOVEL_ENH_PORT7 0 - -/** - * @section XhciSwitch - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#if CONFIG_ONBOARD_USB30 == 1 - #define SB_XHCI_SWITCH 0 -#else -#define SB_XHCI_SWITCH 1 -#endif - -/** - * @section FrontPanelDetected - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_FRONT_PANEL_DETECTED 0 - -/** - * @section AnyHT200MhzLink - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_ANY_HT_200MHZ_LINK 0 - -/** - * @section PcibClkStopOverride - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_PCIB_CLK_STOP_OVERRIDE 0 - -/** - * @section GppLinkConfig - * @li <b>0000</b> - Port ABCD -> 4:0:0:0 - * @li <b>0001</b> - N/A - * @li <b>0010</b> - Port ABCD -> 2:2:0:0 - * @li <b>0011</b> - Port ABCD -> 2:1:1:0 - * @li <b>0100</b> - Port ABCD -> 1:1:1:1 - */ -#define INCHIP_GPP_LINK_CONFIG 4 - -/** - * @section GppUnhidePorts - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_GPP_UNHIDE_PORTS 0 - -/** - * @section GppPortAspm - * @li <b>01</b> - Disabled - * @li <b>01</b> - L0s - * @li <b>10</b> - L1 - * @li <b>11</b> - L0s + L1 - */ -#define INCHIP_GPP_PORT_ASPM 3 - -/** - * @section GppLaneReversal - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_GPP_LANEREVERSAL 0 - -/** - * @section AlinkPhyPllPowerDown - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_ALINK_PHY_PLL_POWER_DOWN 1 - -/** - * @section GppPhyPllPowerDown - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_GPP_PHY_PLL_POWER_DOWN 1 - -/** - * @section GppDynamicPowerSaving - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_GPP_DYNAMIC_POWER_SAVING 1 - -/** - * @section PcieAER - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_PCIE_AER 0 - -/** - * @section PcieRAS - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_PCIE_RAS 0 - -/** - * @section GppHardwareDowngrade - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_GPP_HARDWARE_DOWNGRADE 0 - -/** - * @section GppToggleReset - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_GPP_TOGGLE_RESET 0 - -/** - * @section SbPcieOrderRule - * @li <b>00</b> - Disable - * @li <b>01</b> - Rule 1 - * @li <b>10</b> - Rule 2 - */ -#define INCHIP_SB_PCIE_ORDER_RULE 2 - -/** - * @section AcDcMsg - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_ACDC_MSG 0 - -/** - * @section TimerTickTrack - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_TIMER_TICK_TRACK 1 - -/** - * @section ClockInterruptTag - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_CLOCK_INTERRUPT_TAG 1 - -/** - * @section OhciTrafficHanding - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_OHCI_TRAFFIC_HANDING 0 - -/** - * @section EhciTrafficHanding - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_EHCI_TRAFFIC_HANDING 0 - -/** - * @section FusionMsgCMultiCore - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_FUSION_MSGC_MULTICORE 0 - -/** - * @section FusionMsgCStage - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_FUSION_MSGC_STAGE 0 - -/** - * @section ALinkClkGateOff - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_ALINK_CLK_GATE_OFF 0 - -/** - * @section BLinkClkGateOff - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_BLINK_CLK_GATE_OFF 0 - -/** - * @section SlowSpeedABlinkClock - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_SLOW_SPEED_ABLINK_CLOCK 0 - -/** - * @section AbClockGating - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_AB_CLOCK_GATING 1 - -/** - * @section GppClockGating - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_GPP_CLOCK_GATING 1 - -/** - * @section L1TimerOverwrite - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_L1_TIMER_OVERWRITE 0 - -/** - * @section UmiDynamicSpeedChange - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_UMI_DYNAMIC_SPEED_CHANGE 0 - -/** - * @section SbAlinkGppTxDriverStrength - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_ALINK_GPP_TX_DRV_STRENGTH 0 - -/** - * @section StressResetMode - * @li <b>0</b> - Disable - * @li <b>1</b> - Enable - */ -#define INCHIP_STRESS_RESET_MODE 0 - -#ifndef SB_PCI_CLOCK_RESERVED - #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F -#endif - -/** - * @brief South Bridge CIMx configuration - * - */ -void sb900_cimx_config(AMDSBCFG *sb_cfg); -void SbPowerOnInit_Config(AMDSBCFG *sb_cfg); - -/** - * @brief Entry point of Southbridge CIMx callout - * - * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) - * - * @param[in] func Southbridge CIMx Function ID. - * @param[in] data Southbridge Input Data. - * @param[in] sb_cfg Southbridge configuration structure pointer. - * - */ -u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg); - -#endif diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h index 6f2d5f1..6ad81c4 100644 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ b/src/southbridge/amd/cimx/sb800/Amd.h @@ -156,7 +156,7 @@ typedef struct _AMD_MODULE_HEADER { #define ILLEGAL_SBDFO 0xFFFFFFFF
/// CPUID data received registers format -typedef struct _SB_CPUID_DATA { +typedef struct _CPUID_DATA { IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX diff --git a/src/southbridge/amd/cimx/sb800/SbEarly.h b/src/southbridge/amd/cimx/sb800/SbEarly.h index 2dd0e6d..b346373 100644 --- a/src/southbridge/amd/cimx/sb800/SbEarly.h +++ b/src/southbridge/amd/cimx/sb800/SbEarly.h @@ -21,6 +21,21 @@ #ifndef _CIMX_SB_EARLY_H_ #define _CIMX_SB_EARLY_H_
+#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 + +#define SB800_ACPI_IO_BASE 0x800 + +#define ACPI_PM_EVT_BLK (SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x0F) /* 1 byte */ +#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x08) /* 4 bytes */ +#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x20) /* 8 bytes */ +#define ACPI_CPU_CONTROL (SB800_ACPI_IO_BASE + 0x10) /* 6 bytes */ + +#define REV_SB800_A11 0x11 +#define REV_SB800_A12 0x12 + /** * @brief Get SouthBridge device number, called by finalize_node_setup() * @param[in] bus target bus number @@ -32,6 +47,7 @@ u32 get_sbdn(u32 bus); * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper. */ void sb_poweron_init(void); -//void sb_before_pci_init(void); +void sb800_early_setup(void); +void sb800_before_pci_init(void);
#endif diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 593bd6b..87d09a3 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -20,6 +20,39 @@ #include <arch/io.h> #include <arch/romcc_io.h>
+ +#if CONFIG_CONSOLE_POST == 1 + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 + +#ifndef CONFIG_TTYS0_DIV +#if ((115200%CONFIG_TTYS0_BAUD) != 0) +#error Bad ttys0 baud rate +#endif +#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) +#endif // CONFIG_TTYS0_DIV + +#define UART_LCS CONFIG_TTYS0_LCS + +#endif // CONFIG_CONSOLE_POST == 1 + + static void enable_rom(void) { u16 word; diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 0a09e11..fb4dce3 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -20,6 +20,7 @@
#include "SBPLATFORM.h" #include "cfg.h" +#include <console/console.h> /* printk */
/** @@ -31,8 +32,10 @@ void sb800_cimx_config(AMDSBCFG *sb_config) { if (!sb_config) { + printk(BIOS_DEBUG, "SB800 - Cfg.c - sb800_cimx_config - No sb_config.\n"); return; } + printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - Start.\n"); //memset(sb_config, 0, sizeof(AMDSBCFG));
/* header */ @@ -99,6 +102,10 @@ void sb800_cimx_config(AMDSBCFG *sb_config) sb_config->GppFunctionEnable = GPP_CONTROLLER; sb_config->GppLinkConfig = GPP_CFGMODE; //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE; + sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED; + sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED; sb_config->GppUnhidePorts = TRUE; //visable always, even port empty //sb_config->NbSbGen2 = TRUE; //sb_config->GppGen2 = TRUE; @@ -119,5 +126,6 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
//sb_config-> #endif //!__PRE_RAM__ + printk(BIOS_INFO, "SB800 - Cfg.c - sb800_cimx_config - End.\n"); }
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40a18cc..9b3a00f 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -26,6 +26,9 @@ #include "SBPLATFORM.h" #include "SbEarly.h" #include "cfg.h" /*sb800_cimx_config*/ +#include <console/console.h> +#include <console/loglevel.h> +#include "smbus.h"
/** @@ -37,11 +40,13 @@ u32 get_sbdn(u32 bus) { device_t dev;
+ printk(BIOS_DEBUG, "SB800 - Early.c - get_sbdn - Start.\n"); //dev = PCI_DEV(bus, 0x14, 0); dev = pci_locate_device_on_bus( PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM), bus);
+ printk(BIOS_DEBUG, "SB800 - Early.c - get_sbdn - End.\n"); return (dev >> 15) & 0x1f; }
@@ -54,6 +59,7 @@ void sb_poweron_init(void) { AMDSBCFG sb_early_cfg;
+ printk(BIOS_DEBUG, "SB800 - Early.c - sb_poweron_init - Start.\n"); sb800_cimx_config(&sb_early_cfg); //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; //AmdSbDispatcher(&sb_early_cfg); @@ -61,4 +67,304 @@ void sb_poweron_init(void) //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, // VerifyImage() will fail, LocateImage() take minitues to find the image. sbPowerOnInit(&sb_early_cfg); + printk(BIOS_DEBUG, "SB800 - Early.c - sb_poweron_init - End.\n"); } + + +static void pmio_write(u8 reg, u8 value) +{ + outb(reg, PM_INDEX); + outb(value, PM_INDEX + 1); +} + + +static u8 pmio_read(u8 reg) +{ + outb(reg, PM_INDEX); + return inb(PM_INDEX + 1); +} + + +/* RPR 2.28 Get SB ASIC Revision.*/ +static u8 get_sb800_revision(void) +{ + device_t dev; + u8 rev_id; + u8 rev = 0; + + /* if (rev != 0) return rev; */ + + dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0); + + if (dev == PCI_DEV_INVALID) { + die("SMBUS controller not found\n"); + /* NOT REACHED */ + } + rev_id = pci_read_config8(dev, 0x08); + + if (rev_id == 0x40) { + rev = REV_SB800_A11; + } else if (rev_id == 0x41) { + rev = REV_SB800_A12; + } else { + die("It is not SB800 or SB810\r\n"); + } + + return rev; +} + + +/* sbDevicesPorInitTable */ +static void sb800_devices_por_init(void) +{ + device_t dev; + u8 byte; + + printk(BIOS_INFO, "sb800_devices_por_init()\n"); + /* SMBus Device, BDF:0-20-0 */ + printk(BIOS_INFO, "sb800_devices_por_init(): SMBus Device, BDF:0-20-0\n"); + dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0); + + if (dev == PCI_DEV_INVALID) { + die("SMBUS controller not found\n"); + /* NOT REACHED */ + } + printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\n", + get_sb800_revision()); + + /* sbPorAtStartOfTblCfg */ + /* rpr 4.1.Set A-Link bridge access address. + * This is an I/O address. The I/O address must be on 16-byte boundry. */ + //pci_write_config32(dev, 0xf0, AB_INDX); + pmio_write(0xE0, AB_INDX & 0xFF); + pmio_write(0xE1, (AB_INDX >> 8) & 0xFF); + pmio_write(0xE2, (AB_INDX >> 16) & 0xFF); + pmio_write(0xE3, (AB_INDX >> 24) & 0xFF); + + /* To enable AB/BIF DMA access, a specific register inside the BIF register space needs to be configured first. */ + /* 4.2:Enables the SB800 to send transactions upstream over A-Link Express interface. */ + axcfg_reg(0x04, 1 << 2, 1 << 2); + //axindxc_reg(0x21, 0xff, 0); + + /* 4.15:Enabling Non-Posted Memory Write for the K8 Platform */ + axindxc_reg(0x10, 1 << 9, 1 << 9); + /* END of sbPorAtStartOfTblCfg */ + + /* sbDevicesPorInitTables */ + /* set smbus iobase */ + //pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); + /* The base address of SMBUS is set in a different way with sb700. */ + byte = (SMBUS_IO_BASE & 0xFF) | 1; + pmio_write(0x2c, byte & 0xFF); + pmio_write(0x2d, SMBUS_IO_BASE >> 8); + + /* AcpiMMioDecodeEn */ + byte = pmio_read(0x24); + byte |= 1; + byte &= ~(1 << 1); + pmio_write(0x24, byte); + /* enable smbus controller interface */ + //byte = pci_read_config8(dev, 0xd2); + //byte |= (1 << 0); + //pci_write_config8(dev, 0xd2, byte); + + /* KB2RstEnable */ + //pci_write_config8(dev, 0x40, 0x44); + + /* Enable ISA Address 0-960K decoding */ + //pci_write_config8(dev, 0x48, 0x0f); + + /* Enable ISA Address 0xC0000-0xDFFFF decode */ + //pci_write_config8(dev, 0x49, 0xff); + + /* Enable decode cycles to IO C50, C51, C52 GPM controls. */ + //byte = pci_read_config8(dev, 0x41); + //byte &= 0x80; + //byte |= 0x33; + //pci_write_config8(dev, 0x41, byte); + + /* Legacy DMA Prefetch Enhancement, CIM masked it. */ + /* pci_write_config8(dev, 0x43, 0x1); */ + + /* clear any lingering errors, so the transaction will run */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + /* IDE Device, BDF:0-20-1 */ + printk(BIOS_INFO, "sb800_devices_por_init(): IDE Device, BDF:0-20-1\n"); + dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0); + /* Disable prefetch */ + byte = pci_read_config8(dev, 0x63); + byte |= 0x1; + pci_write_config8(dev, 0x63, byte); + + /* LPC Device, BDF:0-20-3 */ + printk(BIOS_INFO, "sb800_devices_por_init(): LPC Device, BDF:0-20-3\n"); + dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + /* DMA enable */ + pci_write_config8(dev, 0x40, 0x04); + + /* LPC Sync Timeout */ + pci_write_config8(dev, 0x49, 0xFF); + + /* Set LPC ROM size, it has been done in sb800_lpc_init(). + * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; + * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB + * pci_write_config16(dev, 0x68, 0x000e) + * pci_write_config16(dev, 0x6c, 0xfff0);*/ + + /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ + pci_write_config8(dev, 0x7C, 0x05); + + /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, + */ + printk(BIOS_INFO, "sb800_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); + dev = PCI_DEV(0, 0x14, 4);//pci_locate_device(PCI_ID(0x1002, 0x4384), 0); + + /* Arbiter enable. */ + pci_write_config8(dev, 0x43, 0xff); + + /* Set PCDMA request into hight priority list. */ + /* pci_write_config8(dev, 0x49, 0x1) */ ; + + pci_write_config8(dev, 0x40, 0x26); + + pci_write_config8(dev, 0x0d, 0x40); + pci_write_config8(dev, 0x1b, 0x40); + /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ + pci_write_config8(dev, 0x50, 0x01); + + /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ + printk(BIOS_INFO, "sb800_devices_por_init(): SATA Device, BDF:0-18-0\n"); + dev = PCI_DEV(0, 0x11, 0);//pci_locate_device(PCI_ID(0x1002, 0x4390), 0); + + /*PHY Global Control*/ + pci_write_config16(dev, 0x86, 0x2C00); +} + + +/* +*/ +static void sb800_por_init(void) +{ + /* sbDevicesPorInitTable + sbK8PorInitTable */ + sb800_devices_por_init(); + + /* sbPmioPorInitTable + sbK8PmioPorInitTable */ + //sb800_pmio_por_init(); +} + + +static void sb800_acpi_init(void) +{ + pmio_write(0x60, ACPI_PM_EVT_BLK & 0xFF); + pmio_write(0x61, ACPI_PM_EVT_BLK >> 8); + pmio_write(0x62, ACPI_PM1_CNT_BLK & 0xFF); + pmio_write(0x63, ACPI_PM1_CNT_BLK >> 8); + pmio_write(0x64, ACPI_PM_TMR_BLK & 0xFF); + pmio_write(0x65, ACPI_PM_TMR_BLK >> 8); + pmio_write(0x68, ACPI_GPE0_BLK & 0xFF); + pmio_write(0x69, ACPI_GPE0_BLK >> 8); + + /* CpuControl is in _PR.CPU0, 6 bytes */ + pmio_write(0x66, ACPI_CPU_CONTROL & 0xFF); + pmio_write(0x67, ACPI_CPU_CONTROL >> 8); + + pmio_write(0x6A, 0xB0); /* AcpiSmiCmdLo */ + pmio_write(0x6B, 0); /* AcpiSmiCmdHi */ + + pmio_write(0x6E, 0xB8); /* AcpiPmaCntBlkLo */ + pmio_write(0x6F, 0); /* AcpiPmaCntBlkHi */ + + pmio_write(0x6C, ACPI_PMA_CNT_BLK & 0xFF); + pmio_write(0x6D, ACPI_PMA_CNT_BLK >> 8); + + pmio_write(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses + * the contents of the PM registers at + * index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ +} + + +/* +* This function should be called after enable_sb800_smbus(). +*/ +void sb800_early_setup(void) +{ + printk(BIOS_INFO, "sb800_early_setup()\n"); + sb800_por_init(); + sb800_acpi_init(); +} + + +/* +* Add any south bridge setting. +*/ +static void sb800_pci_cfg(void) +{ + device_t dev; + u8 byte; + + /* SMBus Device, BDF:0-20-0 */ + dev = PCI_DEV(0, 0x14, 0);//pci_locate_device(PCI_ID(0x1002, 0x4385), 0); + /* Enable watchdog decode timer */ + byte = pci_read_config8(dev, 0x41); + byte |= (1 << 3); + pci_write_config8(dev, 0x41, byte); + + /* rpr 7.4. Set to 1 to reset USB on the software (such as IO-64 or IO-CF9 cycles) + * generated PCIRST#. */ + byte = pmio_read(0xF0); + byte |= (1 << 2); + pmio_write(0xF0, byte); + + /* IDE Device, BDF:0-20-1 */ + dev = PCI_DEV(0, 0x14, 1);//pci_locate_device(PCI_ID(0x1002, 0x439C), 0); + /* Enable IDE Explicit prefetch, 0x63[0] clear */ + byte = pci_read_config8(dev, 0x63); + byte &= 0xfe; + pci_write_config8(dev, 0x63, byte); + + /* LPC Device, BDF:0-20-3 */ + /* The code below is ported from old chipset. It is not + * metioned in RPR. But I keep them. The registers and the + * comments are compatible. */ + dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + /* Enabling LPC DMA function. */ + byte = pci_read_config8(dev, 0x40); + byte |= (1 << 2); + pci_write_config8(dev, 0x40, byte); + /* Disabling LPC TimeOut. 0x48[7] clear. */ + byte = pci_read_config8(dev, 0x48); + byte &= 0x7f; + pci_write_config8(dev, 0x48, byte); + /* Disabling LPC MSI Capability, 0x78[1] clear. */ + byte = pci_read_config8(dev, 0x78); + byte &= 0xfd; + pci_write_config8(dev, 0x78, byte); + + /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ + dev = PCI_DEV(0, 0x11, 0);//pci_locate_device(PCI_ID(0x1002, 0x4390), 0); + /* rpr7.12 SATA MSI and D3 Power State Capability. */ + byte = pci_read_config8(dev, 0x40); + byte |= 1 << 0; + pci_write_config8(dev, 0x40, byte); + if (get_sb800_revision() <= 0x12) + pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */ + else + pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */ + byte &= ~(1 << 0); + pci_write_config8(dev, 0x40, byte); +} + + +/* +* It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration. +*/ +void sb800_before_pci_init(void) +{ + printk(BIOS_INFO, "sb800_before_pci_init()\n"); + sb800_pci_cfg(); +} + diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index b16bc50..821604d 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -58,6 +58,7 @@ u32 sb800_callout_entry(u32 func, u32 data, void* config) { u32 ret = 0;
+ printk(BIOS_DEBUG, "SB800 - Late.c - sb900_callout_entry - Start.\n"); switch (func) { case CB_SBGPP_RESET_ASSERT: //set_pcie_assert(); @@ -76,6 +77,7 @@ u32 sb800_callout_entry(u32 func, u32 data, void* config) break; }
+ printk(BIOS_DEBUG, "SB800 - Late.c - sb900_callout_entry - End.\n"); return ret; }
@@ -87,14 +89,18 @@ static struct pci_operations lops_pci = { static void lpc_enable_resources(device_t dev) {
+ printk(BIOS_DEBUG, "SB800 - Late.c - lpc_enable_resources - Start.\n"); pci_dev_enable_resources(dev); //lpc_enable_childrens_resources(dev); + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_enable_resources - End.\n"); }
static void lpc_init(device_t dev) { + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); /* SB Configure HPET base and enable bit */ hpetInit(sb_config, &(sb_config->BuildParameters)); + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); }
static struct device_operations lpc_ops = { @@ -115,16 +121,20 @@ static const struct pci_driver lpc_driver __pci_driver = {
static void sata_enable_resources(struct device *dev) { + printk(BIOS_DEBUG, "SB800 - Late.c - sata_enable_resources - Start.\n"); sataInitAfterPciEnum(sb_config); pci_dev_enable_resources(dev); + printk(BIOS_DEBUG, "SB800 - Late.c - sata_enable_resources - End.\n"); }
static void sata_init(struct device *dev) { + printk(BIOS_DEBUG, "SB800 - Late.c - sata_init - Start.\n"); sb_config->StdHeader.Func = SB_MID_POST_INIT; AmdSbDispatcher(sb_config); //sataInitMidPost only commonInitLateBoot(sb_config); sataInitLatePost(sb_config); + printk(BIOS_DEBUG, "SB800 - Late.c - sata_init - End.\n"); }
static struct device_operations sata_ops = { @@ -140,6 +150,7 @@ static const struct pci_driver sata_driver __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, +/* .device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode 4390 */ };
#if CONFIG_USBDEBUG @@ -149,6 +160,7 @@ static void usb_set_resources(struct device *dev) u32 base; u32 old_debug;
+ printk(BIOS_DEBUG, "SB800 - Late.c - usb_set_resources - Start.\n"); old_debug = get_ehci_debug(); set_ehci_debug(0);
@@ -161,13 +173,16 @@ static void usb_set_resources(struct device *dev) base = res->base; set_ehci_base(base); report_resource_stored(dev, res, ""); + printk(BIOS_DEBUG, "SB800 - Late.c - usb_set_resources - End.\n"); } #endif
static void usb_init(struct device *dev) { + printk(BIOS_DEBUG, "SB800 - Late.c - usb_init - Start.\n"); usbInitAfterPciInit(sb_config); commonInitLateBoot(sb_config); + printk(BIOS_DEBUG, "SB800 - Late.c - usb_init - End.\n"); }
static struct device_operations usb_ops = { @@ -207,7 +222,9 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = {
static void azalia_init(struct device *dev) { + printk(BIOS_DEBUG, "SB800 - Late.c - azalia_init - Start.\n"); azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio + printk(BIOS_DEBUG, "SB800 - Late.c - azalia_init - End.\n"); }
static struct device_operations azalia_ops = { @@ -228,9 +245,10 @@ static const struct pci_driver azalia_driver __pci_driver = {
static void gec_init(struct device *dev) { + printk(BIOS_DEBUG, "SB800 - Late.c - gec_init - Start.\n"); gecInitAfterPciEnum(sb_config); gecInitLatePost(sb_config); - printk(BIOS_DEBUG, "gec hda enabled\n"); + printk(BIOS_DEBUG, "SB800 - Late.c - gec_init - End.\n"); }
static struct device_operations gec_ops = { @@ -266,7 +284,9 @@ static void pci_init(device_t dev)
static void pcie_init(device_t dev) { + printk(BIOS_DEBUG, "SB800 - Late.c - pcie_init - Start.\n"); sbPcieGppLateInit(sb_config); + printk(BIOS_DEBUG, "SB800 - Late.c - pcie_init - End.\n"); }
static struct device_operations pci_ops = { @@ -452,6 +472,11 @@ static void sb800_enable(device_t dev) break; }
+ /* Special setting ABCFG registers before PCI emulation. */ + abSpecialSetBeforePciEnum(sb_config); + usbDesertPll(sb_config); + //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; + //AmdSbDispatcher(sb_config); }
struct chip_operations southbridge_amd_cimx_sb800_ops = { diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index 39762a9..96b7aff 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -19,12 +19,14 @@
#include <device/pci.h> #include "lpc.h" +#include <console/console.h> /* printk */
void lpc_read_resources(device_t dev) { struct resource *res;
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - Start.\n"); /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
@@ -49,18 +51,20 @@ void lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
compact_resources(dev); + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - End.\n"); }
void lpc_set_resources(struct device *dev) { struct resource *res;
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - Start.\n"); pci_dev_set_resources(dev);
/* Specical case. SPI Base Address. The SpiRomEnable should be set. */ res = find_resource(dev, SPIROM_BASE_ADDRESS); pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1); - + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_set_resources - End.\n"); }
/** @@ -76,6 +80,7 @@ void lpc_enable_childrens_resources(device_t dev) int var_num = 0; u16 reg_var[3];
+ printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - Start.\n"); reg = pci_read_config32(dev, 0x44); reg_x = pci_read_config32(dev, 0x48);
@@ -170,4 +175,5 @@ void lpc_enable_childrens_resources(device_t dev) //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata break; } + printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_enable_childrens_resources - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c index 4b13fdb..4dc76ba 100644 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ b/src/southbridge/amd/cimx/sb800/smbus.c @@ -20,6 +20,7 @@
#include <arch/io.h> #include "smbus.h" +#include <console/console.h> /* printk */
static inline void smbus_delay(void) { @@ -71,9 +72,11 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n"); return -2; /* not ready */ }
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - Start.\n"); /* set the device I'm talking too */ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
@@ -90,6 +93,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device) /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTCMD);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - End.\n"); return byte; }
@@ -98,9 +102,11 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n"); return -2; /* not ready */ }
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - Start.\n"); /* set the command... */ outb(val, smbus_io_base + SMBHSTCMD);
@@ -117,6 +123,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) return -3; /* timeout or error */ }
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - End.\n"); return 0; }
@@ -125,9 +132,11 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n"); return -2; /* not ready */ }
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - Start.\n"); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
@@ -147,6 +156,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) /* read results of transaction */ byte = inb(smbus_io_base + SMBHSTDAT0);
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - End.\n"); return byte; }
@@ -155,9 +165,11 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) { + printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n"); return -2; /* not ready */ }
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - Start.\n"); /* set the command/address... */ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
@@ -177,6 +189,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) return -3; /* timeout or error */ }
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - End.\n"); return 0; }
@@ -184,6 +197,7 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) { u32 tmp;
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - Start.\n"); outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -199,12 +213,14 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); + printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ab_indx - End.\n"); }
void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) { u32 tmp;
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - Start.\n"); outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); tmp = inl(AB_DATA); /* rpr 4.2 @@ -220,6 +236,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl(tmp, AB_DATA); outl(0, AB_INDX); + printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_rc_indx - End.\n"); }
/* space = 0: AX_INDXC, AX_DATAC @@ -229,6 +246,7 @@ void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) { u32 tmp;
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - Start.\n"); /* read axindc to tmp */ outl(space << 29 | space << 3 | 0x30, AB_INDX); outl(axindc, AB_DATA); @@ -247,5 +265,6 @@ void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) outl(space << 29 | space << 3 | 0x34, AB_INDX); outl(tmp, AB_DATA); outl(0, AB_INDX); + printk(BIOS_DEBUG, "SB800 - Smbus.c - alink_ax_indx - End.\n"); }
diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc index 17618f9..6292c95 100755 --- a/src/southbridge/amd/cimx/sb900/Makefile.inc +++ b/src/southbridge/amd/cimx/sb900/Makefile.inc @@ -21,11 +21,13 @@ subdirs-$(CONFIG_AMD_CIMX_SB900) += ../../../../../src/vendorcode/amd/cimx/sb900
# SB900 Platform Files
+romstage-y += cfg.c romstage-y += early.c romstage-y += smbus.c
-ramstage-y += late.c +ramstage-y += cfg.c ramstage-y += early.c +ramstage-y += late.c
driver-y += smbus.c driver-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c new file mode 100755 index 0000000..809b7a3 --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -0,0 +1,307 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <string.h> +#include "SbPlatform.h" +#include "cfg.h" +#include <console/console.h> /* printk */ + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb900_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n"); + return; + } + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level + + /* Turn on CDROM and HDD Power */ + sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; + + // header + sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; + + // Build Parameters + sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE; // Internal Option + sb_config->BuildParameters.UsbMsi = USB_MSI; // Internal Option + sb_config->BuildParameters.HdAudioMsi = HDAUDIO_MSI; // Internal Option + sb_config->BuildParameters.LpcMsi = LPC_MSI; // Internal Option + sb_config->BuildParameters.PcibMsi = PCIB_MSI; // Internal Option + sb_config->BuildParameters.AbMsi = AB_MSI; // Internal Option + sb_config->BuildParameters.GecShadowRomBase = GEC_SHADOWROM_BASE; // Board Level + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; // Board Level + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; // Board Level + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; // Board Level + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; // Board Level + sb_config->BuildParameters.OhciSsid = OHCI_SSID; // Board Level + sb_config->BuildParameters.EhciSsid = EHCI_SSID; // Board Level + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; // Board Level + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; // Board Level + sb_config->BuildParameters.IdeSsid = IDE_SSID; // Board Level + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; // Board Level + sb_config->BuildParameters.LpcSsid = LPC_SSID; // Board Level + // sb_config->BuildParameters.PCIBSsid = PCIB_SSID; // Field Retired + + // + // Common Function + // + sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; // External Option + sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_IDE_COMBMD_PRISEC_OPT; // External Option + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = SATA_IDECOMBINED_MODE; // External Option + sb_config->S3Resume = 0; // CIMx Internal Used + sb_config->SpreadSpectrum = INCHIP_SPREAD_SPECTRUM; // Board Level + sb_config->NbSbGen2 = INCHIP_NB_SB_GEN2; // External Option + sb_config->GppGen2 = INCHIP_GPP_GEN2; // External Option + sb_config->GppMemWrImprove = INCHIP_GPP_MEMORY_WRITE_IMPROVE; // Internal Option + sb_config->S4Resume = 0; // CIMx Internal Used + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; // INCHIP_SATA_MODE // External Option + sb_config->SataIdeMode = INCHIP_IDE_MODE; // External Option + sb_config->sdConfig = SB_SD_CONFIG; // External Option + sb_config->sdSpeed = SB_SD_SPEED; // Internal Option + sb_config->sdBitwidth = SB_SD_BITWIDTH; // Internal Option + sb_config->SataDisUnusedIdePChannel = SATA_DISUNUSED_IDE_P_CHANNEL; // External Option + sb_config->SataDisUnusedIdeSChannel = SATA_DISUNUSED_IDE_S_CHANNEL; // External Option + sb_config->IdeDisUnusedIdePChannel = IDE_DISUNUSED_IDE_P_CHANNEL; // External Option + sb_config->IdeDisUnusedIdeSChannel = IDE_DISUNUSED_IDE_S_CHANNEL; // External Option + sb_config->SATAESPPORT.SataEspPort.PORT0 = SATA_ESP_PORT0; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT1 = SATA_ESP_PORT1; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT2 = SATA_ESP_PORT2; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT3 = SATA_ESP_PORT3; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT4 = SATA_ESP_PORT4; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT5 = SATA_ESP_PORT5; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT6 = SATA_ESP_PORT6; // Board Level + sb_config->SATAESPPORT.SataEspPort.PORT7 = SATA_ESP_PORT7; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT0 = SATA_PORT_POWER_PORT0; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT1 = SATA_PORT_POWER_PORT1; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT2 = SATA_PORT_POWER_PORT2; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT3 = SATA_PORT_POWER_PORT3; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT4 = SATA_PORT_POWER_PORT4; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT5 = SATA_PORT_POWER_PORT5; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT6 = SATA_PORT_POWER_PORT6; // Board Level + sb_config->SATAPORTPOWER.SataPortPower.PORT7 = SATA_PORT_POWER_PORT7; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT0 = SATA_PORTMODE_PORT0; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT1 = SATA_PORTMODE_PORT1; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT2 = SATA_PORTMODE_PORT2; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT3 = SATA_PORTMODE_PORT3; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT4 = SATA_PORTMODE_PORT4; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT5 = SATA_PORTMODE_PORT5; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT6 = SATA_PORTMODE_PORT6; // Board Level + sb_config->SATAPORTMODE.SataPortMd.PORT7 = SATA_PORTMODE_PORT7; // Board Level + sb_config->SataAggrLinkPmCap = INCHIP_SATA_AGGR_LINK_PM_CAP; // Internal Option + sb_config->SataPortMultCap = INCHIP_SATA_PORT_MULT_CAP; // Internal Option + sb_config->SataClkAutoOff = INCHIP_SATA_CLK_AUTO_OFF; // External Option + sb_config->SataPscCap = INCHIP_SATA_PSC_CAP; // External Option + sb_config->SataFisBasedSwitching = INCHIP_SATA_FIS_BASE_SW; // External Option + sb_config->SataCccSupport = INCHIP_SATA_CCC_SUPPORT; // External Option + sb_config->SataSscCap = INCHIP_SATA_SSC_CAP; // External Option + sb_config->SataMsiCapability = INCHIP_SATA_MSI_CAP; // Internal Option + sb_config->SataForceRaid = INCHIP_SATA_FORCE_RAID5; // Internal Option + sb_config->SataTargetSupport8Device = CIMXSB_SATA_TARGET_8DEVICE_CAP; // External Option + sb_config->SataDisableGenericMode = SATA_DISABLE_GENERIC_MODE_CAP;// External Option + sb_config->SataAhciEnclosureManagement = SATA_AHCI_ENCLOSURE_CAP; // Internal Option + sb_config->SataSgpio0 = SATA_GPIO_0_CAP; // External Option + sb_config->SataSgpio1 = SATA_GPIO_1_CAP; // External Option + sb_config->SataPhyPllShutDown = SATA_PHY_PLL_SHUTDOWN; // External Option + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT0 = SATA_HOTREMOVEL_ENH_PORT0; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT1 = SATA_HOTREMOVEL_ENH_PORT1; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT2 = SATA_HOTREMOVEL_ENH_PORT2; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT3 = SATA_HOTREMOVEL_ENH_PORT3; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT4 = SATA_HOTREMOVEL_ENH_PORT4; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT5 = SATA_HOTREMOVEL_ENH_PORT5; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT6 = SATA_HOTREMOVEL_ENH_PORT6; // Board Level + sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT7 = SATA_HOTREMOVEL_ENH_PORT7; // Board Level + // USB + sb_config->USBMODE.UsbMode.Ohci1 = INCHIP_USB_OHCI1_CINFIG; // External Option + sb_config->USBMODE.UsbMode.Ehci1 = INCHIP_USB_EHCI1_CINFIG; // Internal Option* + sb_config->USBMODE.UsbMode.Ohci2 = INCHIP_USB_OHCI2_CINFIG; // External Option + sb_config->USBMODE.UsbMode.Ehci2 = INCHIP_USB_EHCI2_CINFIG; // Internal Option* + sb_config->USBMODE.UsbMode.Ohci3 = INCHIP_USB_OHCI3_CINFIG; // External Option + sb_config->USBMODE.UsbMode.Ehci3 = INCHIP_USB_EHCI3_CINFIG; // Internal Option* + sb_config->USBMODE.UsbMode.Ohci4 = INCHIP_USB_OHCI4_CINFIG; // External Option + // GEC + sb_config->GecConfig = INCHIP_GEC_CONTROLLER; // External Option + sb_config->IrConfig = SB_IR_CONTROLLER; // External Option + sb_config->XhciSwitch = SB_XHCI_SWITCH; // External Option + // Azalia + sb_config->AzaliaController = INCHIP_AZALIA_CONTROLLER; // External Option + sb_config->AzaliaPinCfg = INCHIP_AZALIA_PIN_CONFIG; // Board Level + sb_config->FrontPanelDetected = INCHIP_FRONT_PANEL_DETECTED; // Board Level + sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_PIN_CONFIG; // Board Level + sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; // Board Level + sb_config->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr = NULL; // Board Level + sb_config->AnyHT200MhzLink = INCHIP_ANY_HT_200MHZ_LINK; // Internal Option + sb_config->HpetTimer = SB_HPET_TIMER; // External Option + sb_config->AzaliaSnoop = INCHIP_AZALIA_SNOOP; // Internal Option* + // Generic + sb_config->NativePcieSupport = INCHIP_NATIVE_PCIE_SUPPOORT; // External Option + // USB + sb_config->UsbPhyPowerDown = INCHIP_USB_PHY_POWER_DOWN; // External Option + sb_config->PcibClkStopOverride = INCHIP_PCIB_CLK_STOP_OVERRIDE;// Internal Option + // sb_config->HpetMsiDis = 0; // Field Retired + // sb_config->ResetCpuOnSyncFlood = 0; // Field Retired + // sb_config->PcibAutoClkCtr = 0; // Field Retired + sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level + sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level + sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used + sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used + sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = 0; // CIMx Internal Used + // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired + sb_config->PORTCONFIG[1].PortCfg.PortPresent = SB_GPP_PORT1; // Board Level + sb_config->PORTCONFIG[1].PortCfg.PortDetected = 0; // CIMx Internal Used + sb_config->PORTCONFIG[1].PortCfg.PortIsGen2 = 0; // CIMx Internal Used + sb_config->PORTCONFIG[1].PortCfg.PortHotPlug = 0; // CIMx Internal Used + // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired + sb_config->PORTCONFIG[2].PortCfg.PortPresent = SB_GPP_PORT2; // Board Level + sb_config->PORTCONFIG[2].PortCfg.PortDetected = 0; // CIMx Internal Used + sb_config->PORTCONFIG[2].PortCfg.PortIsGen2 = 0; // CIMx Internal Used + sb_config->PORTCONFIG[2].PortCfg.PortHotPlug = 0; // CIMx Internal Used + // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired + sb_config->PORTCONFIG[3].PortCfg.PortPresent = SB_GPP_PORT3; // Board Level + sb_config->PORTCONFIG[3].PortCfg.PortDetected = 0; // CIMx Internal Used + sb_config->PORTCONFIG[3].PortCfg.PortIsGen2 = 0; // CIMx Internal Used + sb_config->PORTCONFIG[3].PortCfg.PortHotPlug = 0; // CIMx Internal Used + // sb_config->PORTCONFIG[0].PortCfg.PortIntxMap = 0; // Field Retired + sb_config->GppLinkConfig = INCHIP_GPP_LINK_CONFIG; // External Option + sb_config->GppFoundGfxDev = 0; // CIMx Internal Used + sb_config->GppFunctionEnable = SB_GPP_CONTROLLER; // External Option + sb_config->GppUnhidePorts = INCHIP_GPP_UNHIDE_PORTS; // Internal Option + sb_config->GppPortAspm = INCHIP_GPP_PORT_ASPM; // Internal Option + sb_config->GppLaneReversal = INCHIP_GPP_LANEREVERSAL; // External Option + sb_config->AlinkPhyPllPowerDown = INCHIP_ALINK_PHY_PLL_POWER_DOWN; // External Option + sb_config->GppPhyPllPowerDown = INCHIP_GPP_PHY_PLL_POWER_DOWN;// External Option + sb_config->GppDynamicPowerSaving = INCHIP_GPP_DYNAMIC_POWER_SAVING; // External Option + sb_config->PcieAER = INCHIP_PCIE_AER; // External Option + sb_config->PcieRAS = INCHIP_PCIE_RAS; // External Option + sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option + sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option + sb_config->sdbEnable = 0; // CIMx Internal Used + sb_config->TempMMIO = NULL; // CIMx Internal Used + // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired + sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option + sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option + sb_config->SbPcieOrderRule = INCHIP_SB_PCIE_ORDER_RULE; // External Option + sb_config->AcDcMsg = INCHIP_ACDC_MSG; // Internal Option + sb_config->TimerTickTrack = INCHIP_TIMER_TICK_TRACK; // Internal Option + sb_config->ClockInterruptTag = INCHIP_CLOCK_INTERRUPT_TAG; // Internal Option + sb_config->OhciTrafficHanding = INCHIP_OHCI_TRAFFIC_HANDING; // Internal Option + sb_config->EhciTrafficHanding = INCHIP_EHCI_TRAFFIC_HANDING; // Internal Option + sb_config->FusionMsgCMultiCore = INCHIP_FUSION_MSGC_MULTICORE; // Internal Option + sb_config->FusionMsgCStage = INCHIP_FUSION_MSGC_STAGE; // Internal Option + sb_config->ALinkClkGateOff = INCHIP_ALINK_CLK_GATE_OFF; // External Option + sb_config->BLinkClkGateOff = INCHIP_BLINK_CLK_GATE_OFF; // External Option + // sb_config->sdb = 0; // Field Retired + sb_config->GppGen2Strap = 0; // CIMx Internal Used + sb_config->SlowSpeedABlinkClock = INCHIP_SLOW_SPEED_ABLINK_CLOCK; // Internal Option + sb_config->DYNAMICGECROM.DynamicGecRomAddress_Ptr = NULL; // Board Level + sb_config->AbClockGating = INCHIP_AB_CLOCK_GATING; // External Option + sb_config->GppClockGating = INCHIP_GPP_CLOCK_GATING; // External Option + sb_config->L1TimerOverwrite = INCHIP_L1_TIMER_OVERWRITE; // Internal Option + // sb_config->UmiLinkWidth = 0; // Field Retired + sb_config->UmiDynamicSpeedChange = INCHIP_UMI_DYNAMIC_SPEED_CHANGE; // Internal Option + // sb_config->PcieRefClockOverclocking = 0; // Field Retired + sb_config->SbAlinkGppTxDriverStrength = INCHIP_ALINK_GPP_TX_DRV_STRENGTH; // Internal Option + sb_config->PwrFailShadow = 0x02; // Board Level + sb_config->StressResetMode = INCHIP_STRESS_RESET_MODE; // Internal Option + sb_config->hwm.fanSampleFreqDiv = 0x03; // Board Level + sb_config->hwm.hwmSbtsiAutoPoll = 1; // Board Level + + /* General */ + sb_config->PciClks = SB_PCI_CLOCK_RESERVED; + sb_config->hwm.hwmEnable = 0x0; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.CALLBACK.CalloutPtr) { + sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); +} + +void SbPowerOnInit_Config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n"); + return; + } + printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + // Set the build parameters + sb_config->BuildParameters.BiosSize = BIOS_SIZE; // Field Retired + sb_config->BuildParameters.LegacyFree = SBCIMx_LEGACY_FREE; // Board Level + sb_config->BuildParameters.SpiSpeed = SBCIMX_SPI_SPEED; // Internal Option + sb_config->BuildParameters.SpiFastSpeed = SBCIMX_SPI_FASTSPEED; // Internal Option + // sb_config->BuildParameters.SpiWriteSpeed = 0; // Field Retired + sb_config->BuildParameters.SpiMode = SBCIMX_SPI_MODE; // Internal Option + sb_config->BuildParameters.SpiBurstWrite = SBCIMX_SPI_BURST_WRITE; // Internla Option + sb_config->BuildParameters.EcKbd = INCHIP_EC_KBD; // Board Level + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.GecShadowRomBase = GEC_ROM_SHADOW_ADDRESS; // Board Level + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; // Board Level + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; // Board Level + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; // Board Level + sb_config->SATAMODE.SataMode.SataController = INCHIP_SATA_CONTROLLER; // External Option + sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = SATA_COMBINE_MODE_CHANNEL;// External Option + sb_config->SATAMODE.SataMode.SataSetMaxGen2 = SATA_MAX_GEN2_MODE; // External Option + sb_config->SATAMODE.SataMode.SataIdeCombinedMode= SATA_COMBINE_MODE; // External Option + sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option + sb_config->NbSbGen2 = NB_SB_GEN2; // External Option + sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option + sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level + sb_config->sdbEnable = 0; // CIMx Internal Used + sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option + + printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - End.\n"); +} + + diff --git a/src/southbridge/amd/cimx/sb900/cfg.h b/src/southbridge/amd/cimx/sb900/cfg.h new file mode 100755 index 0000000..6565d6c --- /dev/null +++ b/src/southbridge/amd/cimx/sb900/cfg.h @@ -0,0 +1,1242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB900_CFG_H_ +#define _SB900_CFG_H_ + +#include <stdint.h> + + +/** + * @section BIOSSize BIOSSize + * @li <b>0</b> - 1M + * @li <b>1</b> - 2M + * @li <b>3</b> - 4M + * @li <b>7</b> - 8M + * In Hudson-2, default ROM size is 1M Bytes, if your platform + * ROM bigger then 1M you have to set the ROM size outside CIMx + * module and before AGESA module get call. + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 + #define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 + #define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 + #define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 + #define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @section SBCIMx_LEGACY_FREE SBCIMx_LEGACY_FREE + * @li <b>1</b> - Legacy free enable + * @li <b>0</b> - Legacy free disable + */ +#ifndef SBCIMx_LEGACY_FREE + #define SBCIMx_LEGACY_FREE 0 +#endif + +/** + * @section SpiSpeed + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#ifndef SBCIMX_SPI_SPEED + #define SBCIMX_SPI_SPEED 0 +#endif + +/** + * @section SpiFastSpeed + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#ifndef SBCIMX_SPI_FASTSPEED + #define SBCIMX_SPI_FASTSPEED 0 +#endif + +/** + * @section SpiMode + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#ifndef SBCIMX_SPI_MODE + #define SBCIMX_SPI_MODE 0 +#endif + +/** + * @section SpiBurstWrite + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#ifndef SBCIMX_SPI_BURST_WRITE + #define SBCIMX_SPI_BURST_WRITE 0 +#endif + +/** + * @section INCHIP_EC_KBD INCHIP_EC_KBD + * @li <b>0</b> - Use SIO PS/2 function. + * @li <b>1</b> - Use EC PS/2 function. + */ +#ifndef INCHIP_EC_KBD + #define INCHIP_EC_KBD 0 +#endif + +/** + * @section INCHIP_EC_CHANNEL10 INCHIP_EC_CHANNEL10 + * @li <b>0</b> - EC controller NOT support Channel10 + * @li <b>1</b> - EC controller support Channel10. + */ +#ifndef INCHIP_EC_CHANNEL10 + #define INCHIP_EC_CHANNEL10 1 +#endif + +/** + * @section Smbus0BaseAddress + */ +// #ifndef SMBUS0_BASE_ADDRESS +// #define SMBUS0_BASE_ADDRESS 0xB00 +// #endif + +/** + * @section Smbus1BaseAddress + */ +// #ifndef SMBUS1_BASE_ADDRESS +// #define SMBUS1_BASE_ADDRESS 0xB21 +// #endif + +/** + * @section SioPmeBaseAddress + */ +// #ifndef SIO_PME_BASE_ADDRESS +// #define SIO_PME_BASE_ADDRESS 0xE00 +// #endif + +/** + * @section WatchDogTimerBase + */ +// #ifndef WATCHDOG_TIMER_BASE_ADDRESS +// #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000 +// #endif + +/** + * @section GecShadowRomBase + */ +#ifndef GEC_ROM_SHADOW_ADDRESS + #define GEC_ROM_SHADOW_ADDRESS 0xFED61000 +#endif + +/** + * @section SpiRomBaseAddress + */ +// #ifndef SPI_BASE_ADDRESS +// #define SPI_BASE_ADDRESS 0xFEC10000 +// #endif + +/** + * @section AcpiPm1EvtBlkAddr + */ +// #ifndef PM1_EVT_BLK_ADDRESS +// #define PM1_EVT_BLK_ADDRESS 0x400 +// #endif + +/** + * @section AcpiPm1CntBlkAddr + */ +// #ifndef PM1_CNT_BLK_ADDRESS +// #define PM1_CNT_BLK_ADDRESS 0x404 +// #endif + +/** + * @section AcpiPmTmrBlkAddr + */ +// #ifndef PM1_TMR_BLK_ADDRESS +// #define PM1_TMR_BLK_ADDRESS 0x408 +// #endif + +/** + * @section CpuControlBlkAddr + */ +// #ifndef CPU_CNT_BLK_ADDRESS +// #define CPU_CNT_BLK_ADDRESS 0x410 +// #endif + +/** + * @section AcpiGpe0BlkAddr + */ +// #ifndef GPE0_BLK_ADDRESS +// #define GPE0_BLK_ADDRESS 0x420 +// #endif + +/** + * @section SmiCmdPortAddr + */ +// #ifndef SMI_CMD_PORT +// #define SMI_CMD_PORT 0xB0 +// #endif + +/** + * @section AcpiPmaCntBlkAddr + */ +// #ifndef ACPI_PMA_CNT_BLK_ADDRESS +// #define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 +// #endif + +/** + * @section SataController + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#ifndef INCHIP_SATA_CONTROLLER + #define INCHIP_SATA_CONTROLLER 1 +#endif + +/** + * @section SataIdeCombMdPriSecOpt + * @li <b>0</b> - Primary + * @li <b>1</b> - Secondary<TD></TD> + * Sata Controller set as primary or + * secondary while Combined Mode is enabled + */ +#ifndef SATA_COMBINE_MODE_CHANNEL + #define SATA_COMBINE_MODE_CHANNEL 0 +#endif + +/** + * @section SataSetMaxGen2 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + * SataController Set to Max Gen2 mode + */ +#ifndef SATA_MAX_GEN2_MODE + #define SATA_MAX_GEN2_MODE 0 +#endif + +/** + * @section SataIdeCombinedMode + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + * Sata IDE Controller set to Combined Mode + */ +#ifndef SATA_COMBINE_MODE + #define SATA_COMBINE_MODE 0 +#endif + +#define SATA_CLK_RESERVED 9 + +/** + * @section NbSbGen2 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#ifndef NB_SB_GEN2 + #define NB_SB_GEN2 1 +#endif + +/** + * @section SataInternal100Spread + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#ifndef INCHIP_SATA_INTERNAL_100_SPREAD + #define INCHIP_SATA_INTERNAL_100_SPREAD 0 +#endif + +/** + * @section Cg2Pll + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#ifndef INCHIP_CG2_PLL + #define INCHIP_CG2_PLL 0 +#endif + + + + +/** + * @section SpreadSpectrum + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + * Spread Spectrum function + */ +#define INCHIP_SPREAD_SPECTRUM 1 + +/** + * @section INCHIP_USB_CINFIG INCHIP_USB_CINFIG + * + * - Usb Ohci1 Contoller is define at BIT0 + * 0:Disable 1:Enable + * (Bus 0 Dev 18 Func0) + * - Usb Ehci1 Contoller is define at BIT1 + * 0:Disable 1:Enable + * (Bus 0 Dev 18 Func2) + * - Usb Ohci2 Contoller is define at BIT2 + * 0:Disable 1:Enable + * (Bus 0 Dev 19 Func0) + * - Usb Ehci2 Contoller is define at BIT3 + * 0:Disable 1:Enable + * (Bus 0 Dev 19 Func2) + * - Usb Ohci3 Contoller is define at BIT4 + * 0:Disable 1:Enable + * (Bus 0 Dev 22 Func0) + * - Usb Ehci3 Contoller is define at BIT5 + * 0:Disable 1:Enable + * (Bus 0 Dev 22 Func2) + * - Usb Ohci4 Contoller is define at BIT6 + * 0:Disable 1:Enable + * (Bus 0 Dev 20 Func5) + */ +#define INCHIP_USB_CINFIG 0x7F +#define INCHIP_USB_OHCI1_CINFIG 0x01 +#define INCHIP_USB_OHCI2_CINFIG 0x01 +#if CONFIG_ONBOARD_USB30 == 1 +#define INCHIP_USB_OHCI3_CINFIG 0x00 +#else +#define INCHIP_USB_OHCI3_CINFIG 0x01 +#endif +#define INCHIP_USB_OHCI4_CINFIG 0x01 +#define INCHIP_USB_EHCI1_CINFIG 0x01 +#define INCHIP_USB_EHCI2_CINFIG 0x01 +#define INCHIP_USB_EHCI3_CINFIG 0x01 + +/** + * @section INCHIP_SATA_MODE INCHIP_SATA_MODE + * @li <b>000</b> - Native IDE mode + * @li <b>001</b> - RAID mode + * @li <b>010</b> - AHCI mode + * @li <b>011</b> - Legacy IDE mode + * @li <b>100</b> - IDE->AHCI mode + * @li <b>101</b> - AHCI mode as 7804 ID (AMD driver) + * @li <b>110</b> - IDE->AHCI mode as 7804 ID (AMD driver) + */ +#define INCHIP_SATA_MODE 0 + +/** + * @section INCHIP_IDE_MODE INCHIP_IDE_MODE + * @li <b>0</b> - Legacy IDE mode + * @li <b>1</b> - Native IDE mode<TD></TD> + * ** DO NOT ALLOW SATA & IDE use same mode ** + */ +#define INCHIP_IDE_MODE 1 + +#define SATA_PORT_MULT_CAP_RESERVED 1 + +/** + * @section INCHIP_AZALIA_CONTROLLER INCHIP_AZALIA_CONTROLLER + * @li <b>0</b> - Auto : Detect Azalia controller automatically. + * @li <b>1</b> - Diable : Disable Azalia controller. + * @li <b>2</b> - Enable : Enable Azalia controller. + */ +#define INCHIP_AZALIA_CONTROLLER 2 +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @section INCHIP_AZALIA_PIN_CONFIG INCHIP_AZALIA_PIN_CONFIG + * @li <b>0</b> - disable + * @li <b>1</b> - enable + */ +#define INCHIP_AZALIA_PIN_CONFIG 1 + +/** + * @section AZALIA_PIN_CONFIG AZALIA_PIN_CONFIG + * + * SDIN0 is define at BIT0 & BIT1 + * - 00: GPIO PIN + * - 01: Reserved + * - 10: As a Azalia SDIN pin<TD></TD> + * SDIN1 is define at BIT2 & BIT3 + * - 00: GPIO PIN + * - 01: Reserved + * - 10: As a Azalia SDIN pin<TD></TD> + * SDIN2 is define at BIT4 & BIT5 + * - 00: GPIO PIN + * - 01: Reserved + * - 10: As a Azalia SDIN pin<TD></TD> + * SDIN3 is define at BIT6 & BIT7 + * - 00: GPIO PIN + * - 01: Reserved + * - 10: As a Azalia SDIN pin + */ +#define AZALIA_PIN_CONFIG 0x2A + +/** + * @section AzaliaSnoop + * @li <b>0</b> - disable + * @li <b>1</b> - enable * + */ +#define INCHIP_AZALIA_SNOOP 0x01 + +/** + * @section NCHIP_GEC_CONTROLLER + * @li <b>0</b> - Enable * + * @li <b>1</b> - Disable + */ +#define INCHIP_GEC_CONTROLLER 0x00 + +/** + * @section SB_HPET_TIMER SB_HPET_TIMER + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SB_HPET_TIMER 1 + +/** + * @section SB_GPP_CONTROLLER SB_GPP_CONTROLLER + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SB_GPP_CONTROLLER 1 + +/** + * @section GPP_LINK_CONFIG GPP_LINK_CONFIG + * @li <b>0000</b> - Port ABCD -> 4:0:0:0 + * @li <b>0001</b> - N/A + * @li <b>0010</b> - Port ABCD -> 2:2:0:0 + * @li <b>0011</b> - Port ABCD -> 2:1:1:0 + * @li <b>0100</b> - Port ABCD -> 1:1:1:1 + */ +#define GPP_LINK_CONFIG 4 + +/** + * @section SB_GPP_PORT0 SB_GPP_PORT0 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SB_GPP_PORT0 1 + +/** + * @section SB_GPP_PORT1 SB_GPP_PORT1 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SB_GPP_PORT1 1 + +/** + * @section SB_GPP_PORT2 SB_GPP_PORT2 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SB_GPP_PORT2 1 + +/** + * @section SB_GPP_PORT3 SB_GPP_PORT3 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SB_GPP_PORT3 1 + +/** + * @section SB_IR_CONTROLLER + * @li <b>00 </b> - disable + * @li <b>01 </b> - Rx and Tx0 + * @li <b>10 </b> - Rx and Tx1 + * @li <b>11 </b> - Rx and both Tx0,Tx1 + */ +#define SB_IR_CONTROLLER 3 + +/** + * @section INCHIP_USB_PHY_POWER_DOWN + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_USB_PHY_POWER_DOWN 0 + +/** + * @section INCHIP_NATIVE_PCIE_SUPPOORT + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_NATIVE_PCIE_SUPPOORT 1 + +/** + * @section INCHIP_NB_SB_GEN2 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_NB_SB_GEN2 1 + +/** + * @section INCHIP_GPP_GEN2 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_GPP_GEN2 1 + +/** + * @section INCHIP_GPP_MEMORY_WRITE_IMPROVE + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_GPP_MEMORY_WRITE_IMPROVE 1 + +/** + * @section INCHIP_GEC_PHY_STATUS + * @li <b>0</b> - Gb PHY Mode * + * @li <b>1</b> - 100/10 PHY Mode + */ +#define INCHIP_GEC_PHY_STATUS 0 + +/** + * @section INCHIP_GEC_POWER_POLICY + * @li <b>0</b> - S3/S5 + * @li <b>1</b> - S5 + * @li <b>2</b> - S3 + * @li <b>3</b> - Never power down * + */ +#define INCHIP_GEC_POWER_POLICY 3 + +/** + * @section INCHIP_GEC_DEBUGBUS + * @li <b>0</b> - Disable * + * @li <b>1</b> - Enable + */ +#define INCHIP_GEC_DEBUGBUS 0 + +/** + * @section SATA_MAX_GEN2_MODE SATA_MAX_GEN2_MODE + * @li <b>0</b> - Disable * + * @li <b>1</b> - Enable + * SataController Set to Max Gen2 mode + */ +#define SATA_MAX_GEN2_MODE 0 + +/** + * @section INCHIP_SATA_AGGR_LINK_PM_CAP + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + * SataController Set to aggressive link PM capability + */ +#define INCHIP_SATA_AGGR_LINK_PM_CAP 0 + +/** + * @section INCHIP_SATA_PORT_MULT_CAP + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + * SataController Set to Port Multiple capability + */ +#define INCHIP_SATA_PORT_MULT_CAP 1 + +/** + * @section INCHIP_SATA_PSC_CAP + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * +*/ +#define INCHIP_SATA_PSC_CAP 0 + +/** + * @section INCHIP_SATA_SSC_CAP + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define INCHIP_SATA_SSC_CAP 0 + +/** + * @section INCHIP_SATA_CLK_AUTO_OFF + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define INCHIP_SATA_CLK_AUTO_OFF 1 + +/** + * @section INCHIP_SATA_FIS_BASE_SW + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define INCHIP_SATA_FIS_BASE_SW 1 + +/** + * @section INCHIP_SATA_CCC_SUPPORT + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define INCHIP_SATA_CCC_SUPPORT 1 + +/** + * @section INCHIP_SATA_MSI_CAP + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define INCHIP_SATA_MSI_CAP 1 + +/** + * @section CIMXSB_SATA_TARGET_8DEVICE_CAP + * @li <b>0</b> - Disable * + * @li <b>1</b> - Enable + */ +#define CIMXSB_SATA_TARGET_8DEVICE_CAP 0 + +/** + * @section SATA_DISABLE_GENERIC_MODE + * @li <b>0</b> - Disable * + * @li <b>1</b> - Enable + */ +#define SATA_DISABLE_GENERIC_MODE_CAP 0 + +/** + * @section SATA_AHCI_ENCLOSURE_CAP + * @li <b>0</b> - Disable * + * @li <b>1</b> - Enable + */ +#define SATA_AHCI_ENCLOSURE_CAP 0 + +/** + * @section SataForceRaid (RISD5 mode) + * @li <b>0</b> - Disable * + * @li <b>1</b> - Enable + */ +#define INCHIP_SATA_FORCE_RAID5 0 + +/** + * @section SATA_GPIO_0_CAP + * @li <b>0</b> - Disable * + * @li <b>1</b> - Enable + */ +#define SATA_GPIO_0_CAP 0 + +/** + * @section SATA_GPIO_1_CAP + * @li <b>0</b> - Disable * + * @li <b>1</b> - Enable + */ +#define SATA_GPIO_1_CAP 0 + +/** + * @section SataPhyPllShutDown + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define SATA_PHY_PLL_SHUTDOWN 1 + +/** + * @section ImcEnableOverWrite + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define IMC_ENABLE_OVER_WRITE 0 + +/** + * @section UsbMsi + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define USB_MSI 0 + +/** + * @section HdAudioMsi + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define HDAUDIO_MSI 0 + +/** + * @section LpcMsi + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define LPC_MSI 0 + +/** + * @section PcibMsi + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define PCIB_MSI 0 + +/** + * @section AbMsi + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define AB_MSI 0 + +/** + * @section GecShadowRomBase + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define GEC_SHADOWROM_BASE 0xFED61000 + +/** + * @section SataController + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define SATA_CONTROLLER 1 + +/** + * @section SataIdeCombMdPriSecOpt + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_IDE_COMBMD_PRISEC_OPT 0 + +/** + * @section SataIdeCombinedMode + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_IDECOMBINED_MODE 0 + +/** + * @section sdConfig + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define SB_SD_CONFIG 1 + +/** + * @section sdSpeed + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define SB_SD_SPEED 1 + +/** + * @section sdBitwidth + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable * + */ +#define SB_SD_BITWIDTH 1 + +/** + * @section SataDisUnusedIdePChannel + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_DISUNUSED_IDE_P_CHANNEL 0 + +/** + * @section SataDisUnusedIdeSChannel + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_DISUNUSED_IDE_S_CHANNEL 0 + +/** + * @section IdeDisUnusedIdePChannel + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define IDE_DISUNUSED_IDE_P_CHANNEL 0 + +/** + * @section IdeDisUnusedIdeSChannel + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define IDE_DISUNUSED_IDE_S_CHANNEL 0 + +/** + * @section IdeDisUnusedIdeSChannel + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ + +/** + * @section SataEspPort0 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_ESP_PORT0 0 + +/** + * @section SataEspPort1 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_ESP_PORT1 0 + +/** + * @section SataEspPort2 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_ESP_PORT2 0 + +/** + * @section SataEspPort3 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_ESP_PORT3 0 + +/** + * @section SataEspPort4 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_ESP_PORT4 0 + +/** + * @section SataEspPort5 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_ESP_PORT5 0 + +/** + * @section SataEspPort6 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_ESP_PORT6 0 + +/** + * @section SataEspPort7 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_ESP_PORT7 0 + +/** + * @section SataPortPower0 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORT_POWER_PORT0 0 + +/** + * @section SataPortPower1 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORT_POWER_PORT1 0 + +/** + * @section SataPortPower2 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORT_POWER_PORT2 0 + +/** + * @section SataPortPower3 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORT_POWER_PORT3 0 + +/** + * @section SataPortPower4 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORT_POWER_PORT4 0 + +/** + * @section SataPortPower5 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORT_POWER_PORT5 0 + +/** + * @section SataPortPower6 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORT_POWER_PORT6 0 + +/** + * @section SataPortPower7 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORT_POWER_PORT7 0 + +/** + * @section SataPortMd0 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORTMODE_PORT0 3 + +/** + * @section SataPortMd1 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORTMODE_PORT1 3 + +/** + * @section SataPortMd2 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORTMODE_PORT2 3 + +/** + * @section SataPortMd3 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORTMODE_PORT3 3 + +/** + * @section SataPortMd4 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORTMODE_PORT4 0 + +/** + * @section SataPortMd5 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORTMODE_PORT5 0 + +/** + * @section SataPortMd6 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORTMODE_PORT6 0 + +/** + * @section SataPortMd7 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_PORTMODE_PORT7 0 + +/** + * @section SataHotRemovelEnh0 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT0 0 + +/** + * @section SataHotRemovelEnh1 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT1 0 + +/** + * @section SataHotRemovelEnh2 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT2 0 + +/** + * @section SataHotRemovelEnh3 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT3 0 + +/** + * @section SataHotRemovelEnh4 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT4 0 + +/** + * @section SataHotRemovelEnh5 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT5 0 + +/** + * @section SataHotRemovelEnh6 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT6 0 + +/** + * @section SataHotRemovelEnh7 + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define SATA_HOTREMOVEL_ENH_PORT7 0 + +/** + * @section XhciSwitch + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#if CONFIG_ONBOARD_USB30 == 1 + #define SB_XHCI_SWITCH 0 +#else +#define SB_XHCI_SWITCH 1 +#endif + +/** + * @section FrontPanelDetected + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_FRONT_PANEL_DETECTED 0 + +/** + * @section AnyHT200MhzLink + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_ANY_HT_200MHZ_LINK 0 + +/** + * @section PcibClkStopOverride + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_PCIB_CLK_STOP_OVERRIDE 0 + +/** + * @section GppLinkConfig + * @li <b>0000</b> - Port ABCD -> 4:0:0:0 + * @li <b>0001</b> - N/A + * @li <b>0010</b> - Port ABCD -> 2:2:0:0 + * @li <b>0011</b> - Port ABCD -> 2:1:1:0 + * @li <b>0100</b> - Port ABCD -> 1:1:1:1 + */ +#define INCHIP_GPP_LINK_CONFIG 4 + +/** + * @section GppUnhidePorts + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_GPP_UNHIDE_PORTS 0 + +/** + * @section GppPortAspm + * @li <b>01</b> - Disabled + * @li <b>01</b> - L0s + * @li <b>10</b> - L1 + * @li <b>11</b> - L0s + L1 + */ +#define INCHIP_GPP_PORT_ASPM 3 + +/** + * @section GppLaneReversal + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_GPP_LANEREVERSAL 0 + +/** + * @section AlinkPhyPllPowerDown + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_ALINK_PHY_PLL_POWER_DOWN 1 + +/** + * @section GppPhyPllPowerDown + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_GPP_PHY_PLL_POWER_DOWN 1 + +/** + * @section GppDynamicPowerSaving + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_GPP_DYNAMIC_POWER_SAVING 1 + +/** + * @section PcieAER + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_PCIE_AER 0 + +/** + * @section PcieRAS + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_PCIE_RAS 0 + +/** + * @section GppHardwareDowngrade + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_GPP_HARDWARE_DOWNGRADE 0 + +/** + * @section GppToggleReset + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_GPP_TOGGLE_RESET 0 + +/** + * @section SbPcieOrderRule + * @li <b>00</b> - Disable + * @li <b>01</b> - Rule 1 + * @li <b>10</b> - Rule 2 + */ +#define INCHIP_SB_PCIE_ORDER_RULE 2 + +/** + * @section AcDcMsg + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_ACDC_MSG 0 + +/** + * @section TimerTickTrack + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_TIMER_TICK_TRACK 1 + +/** + * @section ClockInterruptTag + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_CLOCK_INTERRUPT_TAG 1 + +/** + * @section OhciTrafficHanding + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_OHCI_TRAFFIC_HANDING 0 + +/** + * @section EhciTrafficHanding + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_EHCI_TRAFFIC_HANDING 0 + +/** + * @section FusionMsgCMultiCore + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_FUSION_MSGC_MULTICORE 0 + +/** + * @section FusionMsgCStage + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_FUSION_MSGC_STAGE 0 + +/** + * @section ALinkClkGateOff + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_ALINK_CLK_GATE_OFF 0 + +/** + * @section BLinkClkGateOff + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_BLINK_CLK_GATE_OFF 0 + +/** + * @section SlowSpeedABlinkClock + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_SLOW_SPEED_ABLINK_CLOCK 0 + +/** + * @section AbClockGating + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_AB_CLOCK_GATING 1 + +/** + * @section GppClockGating + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_GPP_CLOCK_GATING 1 + +/** + * @section L1TimerOverwrite + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_L1_TIMER_OVERWRITE 0 + +/** + * @section UmiDynamicSpeedChange + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_UMI_DYNAMIC_SPEED_CHANGE 0 + +/** + * @section SbAlinkGppTxDriverStrength + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_ALINK_GPP_TX_DRV_STRENGTH 0 + +/** + * @section StressResetMode + * @li <b>0</b> - Disable + * @li <b>1</b> - Enable + */ +#define INCHIP_STRESS_RESET_MODE 0 + +#ifndef SB_PCI_CLOCK_RESERVED + #define SB_PCI_CLOCK_RESERVED 0x0 //according to CIMx change 0x1F +#endif + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb900_cimx_config(AMDSBCFG *sb_cfg); +void SbPowerOnInit_Config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h index 83722d8..6c92227 100644 --- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h +++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h @@ -113,5 +113,6 @@ unsigned int ReadIo32(IN unsigned short Address); void WriteIo8(IN unsigned short Address, IN unsigned char Data); void WriteIo16(IN unsigned short Address, IN unsigned short Data); void WriteIo32(IN unsigned short Address, IN unsigned int Data); -void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value); +//void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value); +void CpuidRead(unsigned int CpuidFcnAddress, CPUID_DATA *Value); unsigned char ReadNumberOfCpuCores(void);