Author: stepan Date: Thu Apr 21 00:23:56 2011 New Revision: 6534 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6534
Log: drop dead code from sb800 bootblock Signed-off-by: Stefan Reinauer stefan.reinauer@coreboot.org Acked-by: Stefan Reinauer stefan.reinauer@coreboot.org
Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c
Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c Wed Apr 20 23:14:05 2011 (r6533) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/bootblock.c Thu Apr 21 00:23:56 2011 (r6534) @@ -21,39 +21,6 @@ #include <arch/io.h> #include <arch/romcc_io.h>
- -#if CONFIG_CONSOLE_POST == 1 - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - -#ifndef CONFIG_TTYS0_DIV -#if ((115200%CONFIG_TTYS0_BAUD) != 0) -#error Bad ttys0 baud rate -#endif -#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD) -#endif // CONFIG_TTYS0_DIV - -#define UART_LCS CONFIG_TTYS0_LCS - -#endif // CONFIG_CONSOLE_POST == 1 - - static void sb800_enable_rom(void) { u32 word; @@ -68,7 +35,7 @@ */ dword = pci_io_read_config32(dev, 0x44); //dword |= (1<<6) | (1<<29) | (1<<30) ; - /*Turn on all of LPC IO Port decode enable */ + /* Turn on all of LPC IO Port decode enable */ dword = 0xffffffff; pci_io_write_config32(dev, 0x44, dword);