First shot at factoring SMM code into generic parts and southbridge specific parts.
This should help to reduce the code duplication for Rudolf's K8/VIA SMM
implementation...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>

Index: src/southbridge/intel/i82801gx/i82801gx_smihandler.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_smihandler.c	(revision 0)
+++ src/southbridge/intel/i82801gx/i82801gx_smihandler.c	(revision 0)
@@ -0,0 +1,412 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+//#include "chip.h"
+
+// Future TODO: Move to i82801gx directory
+#include "../../../northbridge/intel/i945/ich7.h"
+
+#define DEBUG_SMI
+
+#define ACPI_DISABLE	0x1e
+#define ACPI_ENABLE	0xe1
+
+
+/* I945 */
+#define SMRAM		0x9d
+#define   D_OPEN	(1 << 6)
+#define   D_CLS		(1 << 5)
+#define   D_LCK		(1 << 4)
+#define   G_SMRANE	(1 << 3)
+#define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+
+/* ICH7 */
+#define PM1_STS		0x00
+#define PM1_EN		0x02
+#define PM1_CNT		0x04
+#define PM1_TMR		0x08
+#define PROC_CNT	0x10
+#define LV2		0x14
+#define LV3		0x15
+#define LV4		0x16
+#define PM2_CNT		0x20 // mobile only
+#define GPE0_STS	0x28
+#define GPE0_EN		0x2c
+#define SMI_EN		0x30
+#define   EL_SMI_EN	 (1 << 25) // Intel Quick Resume Technology
+#define   INTEL_USB2_EN	 (1 << 18) // Intel-Specific USB2 SMI logic
+#define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define   PERIODIC_EN	 (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define   TCO_EN	 (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define   MCSMI_EN	 (1 << 11) // Trap microcontroller range access
+#define   BIOS_RLS	 (1 <<  7) // asserts SCI on bit set
+#define   SWSMI_TMR_EN	 (1 <<  6) // start software smi timer on bit set
+#define   APMC_EN	 (1 <<  5) // Writes to APM_CNT cause SMI#
+#define   SLP_SMI_EN	 (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
+#define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
+#define   BIOS_EN	 (1 <<  2) // Assert SMI# on setting GBL_RLS bit
+#define   EOS		 (1 <<  1) // End of SMI (deassert SMI#)
+#define   GBL_SMI_EN	 (1 <<  0) // SMI# generation at all?
+#define SMI_STS		0x34
+#define ALT_GP_SMI_EN	0x38
+#define ALT_GP_SMI_STS	0x3a
+#define GPE_CNTL	0x42
+#define DEVACT_STS	0x44
+#define SS_CNT		0x50
+#define C3_RES		0x54
+
+#include "i82801gx_nvs.h"
+
+/* While we read PMBASE dynamically in case it changed, let's
+ * initialize it with a sane value
+ */
+static u16 pmbase = DEFAULT_PMBASE;
+
+/**
+ * @brief read and clear PM1_STS 
+ * @return PM1_STS register
+ */
+static u16 reset_pm1_status(void)
+{
+	u16 reg16;
+	
+	reg16 = inw(pmbase + PM1_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outw(reg16, pmbase + PM1_STS);
+	
+	return reg16;
+}
+
+static void dump_pm1_status(u16 pm1_sts)
+{
+	printk_debug("PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk_debug("WAK ");
+	if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk_debug("RTC ");
+	if (pm1_sts & (1 <<  8)) printk_debug("PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk_debug("GBL ");
+	if (pm1_sts & (1 <<  4)) printk_debug("BM ");
+	if (pm1_sts & (1 <<  0)) printk_debug("TMROF ");
+	printk_debug("\n");
+}
+
+/**
+ * @brief read and clear SMI_STS 
+ * @return SMI_STS register
+ */
+static u32 reset_smi_status(void)
+{
+	u32 reg32;
+	
+	reg32 = inl(pmbase + SMI_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32, pmbase + SMI_STS);
+	
+	return reg32;
+}
+
+static void dump_smi_status(u32 smi_sts)
+{
+	printk_debug("SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk_debug("SPI ");
+	if (smi_sts & (1 << 25)) printk_debug("EL_SMI ");
+	if (smi_sts & (1 << 21)) printk_debug("MONITOR ");
+	if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk_debug("PERIODIC ");
+	if (smi_sts & (1 << 13)) printk_debug("TCO ");
+	if (smi_sts & (1 << 12)) printk_debug("DEVMON ");
+	if (smi_sts & (1 << 11)) printk_debug("MCSMI ");
+	if (smi_sts & (1 << 10)) printk_debug("GPI ");
+	if (smi_sts & (1 <<  9)) printk_debug("GPE0 ");
+	if (smi_sts & (1 <<  8)) printk_debug("PM1 ");
+	if (smi_sts & (1 <<  6)) printk_debug("SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk_debug("APM ");
+	if (smi_sts & (1 <<  4)) printk_debug("SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk_debug("LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk_debug("BIOS ");
+	printk_debug("\n");
+}
+
+
+/**
+ * @brief read and clear GPE0_STS
+ * @return GPE0_STS register
+ */
+static u32 reset_gpe0_status(void)
+{
+	u32 reg32;
+	
+	reg32 = inl(pmbase + GPE0_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32, pmbase + GPE0_STS);
+	
+	return reg32;
+}
+
+static void dump_gpe0_status(u32 gpe0_sts)
+{
+	int i;
+	printk_debug("GPE0_STS: ");
+	for (i=31; i<= 16; i--) {
+		if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16));
+	}
+	if (gpe0_sts & (1 << 14)) printk_debug("USB4 ");
+	if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk_debug("USB3 ");
+	if (gpe0_sts & (1 << 11)) printk_debug("PME ");
+	if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk_debug("PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk_debug("RI ");
+	if (gpe0_sts & (1 <<  7)) printk_debug("SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk_debug("TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk_debug("AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk_debug("USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk_debug("USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk_debug("HOT_PLUG ");
+	if (gpe0_sts & (1 <<  0)) printk_debug("THRM ");
+	printk_debug("\n");
+}
+
+
+/**
+ * @brief read and clear TCOx_STS 
+ * @return TCOx_STS registers
+ */
+static u32 reset_tco_status(void)
+{
+	u32 tcobase = pmbase + 0x60;
+	u32 reg32;
+	
+	reg32 = inl(tcobase + 0x04);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32 & ~(1<<18), tcobase + 0x04); //  Don't clear BOOT_STS before SECOND_TO_STS
+	if (reg32 & (1 << 18))
+		outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
+	
+	return reg32;
+}
+
+
+static void dump_tco_status(u32 tco_sts)
+{
+	printk_debug("TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk_debug("BOOT ");
+	if (tco_sts & (1 << 17)) printk_debug("SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk_debug("INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk_debug("DMISERR ");
+	if (tco_sts & (1 << 10)) printk_debug("DMISMI ");
+	if (tco_sts & (1 <<  9)) printk_debug("DMISCI ");
+	if (tco_sts & (1 <<  8)) printk_debug("BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk_debug("NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk_debug("TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk_debug("TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk_debug("SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk_debug("NMI2SMI ");
+	printk_debug("\n");
+}
+
+
+/* We are using PCIe accesses for now
+ *  1. the chipset can do it
+ *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
+ */
+#include "../../../northbridge/intel/i945/pcie_config.c"
+
+void southbridge_io_trap_handler(int smif)
+{
+	u8 reg8;
+	global_nvs_t *gnvs = (global_nvs_t *)0xc00;
+
+	printk_debug("SMI function trap 0x%x: ", smif);
+
+
+	switch (smif) {
+	case 0x32:
+		printk_debug("OS Init\n");
+		break;
+	case 0xd6:
+		printk_debug("Get Brightness\n");
+		outb(0x17, 0x66);
+		reg8 = inb(0x62);
+		gnvs->brtl = reg8;
+		break;
+	default:
+		printk_debug("Unknown function\n");
+		break;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+}
+
+/**
+ * @brief Set the EOS bit
+ */
+void southbridge_smi_set_eos(void)
+{
+	u8 reg8;
+
+	reg8 = inb(pmbase + SMI_EN);
+	reg8 |= EOS;
+	outb(reg8, pmbase + SMI_EN);
+}
+
+/**
+ * @brief Interrupt handler for SMI#
+ *
+ * @param smm_revision revision of the smm state save map
+ */
+
+void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+{
+	u8 reg8;
+	u16 pmctrl;
+	u16 pm1_sts;
+	u32 smi_sts, gpe0_sts, tco_sts;
+
+	pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+	printk_spew("SMI#: pmbase = 0x%04x\n", pmbase);
+
+	/* We need to clear the SMI status registers, or we won't see what's
+	 * happening in the following calls.
+	 */
+	smi_sts = reset_smi_status();
+	dump_smi_status(smi_sts);
+
+	if (smi_sts & (1 << 21)) { // MONITOR
+		global_nvs_t *gnvs = (global_nvs_t *)0xc00;
+		int i;
+		u32 reg32;
+
+		reg32 = RCBA32(0x1e00); // TRSR - Trap Status Register
+#if 0
+		/* Comment in for some useful debug */
+		for (i=0; i<4; i++) {
+			if (reg32 & (1 << i)) {
+				printk_debug("  io trap #%d\n", i);
+			}
+		}
+#endif
+		RCBA32(0x1e00) = reg32; // TRSR
+
+		reg32 = RCBA32(0x1e10);
+
+		if ((reg32 & 0xfffc) != 0x808) {
+			printk_debug("  trapped io address = 0x%x\n", reg32 & 0xfffc);
+			printk_debug("  AHBE = %x\n", (reg32 >> 16) & 0xf);
+			printk_debug("  read/write: %s\n", (reg32 & (1 << 24)) ? "read" :
+				"write");
+		}
+
+		if (!(reg32 & (1 << 24))) {
+			/* Write Cycle */
+			reg32 = RCBA32(0x1e18);
+			printk_debug("  iotrap written data = 0x%08x\n", reg32);
+
+		}
+
+		if (gnvs->smif)
+			io_trap_handler(gnvs->smif); // call function smif
+	}
+
+	if (smi_sts & (1 << 13)) { // TCO
+		tco_sts = reset_tco_status();
+		dump_tco_status(tco_sts);
+
+		if (tco_sts & (1 << 8)) { // BIOSWR
+			u8 bios_cntl;
+
+			bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+
+			if (bios_cntl & 1) {
+				/* BWE is RW, so the SMI was caused by a
+				 * write to BWE, not by a write to the BIOS
+				 */
+
+				/* This is the place where we notice someone
+				 * is trying to tinker with the BIOS. We are
+				 * trying to be nice and just ignore it. A more
+				 * resolute answer would be to power down the
+				 * box.
+				 */
+				printk_debug("Switching back to RO\n");
+				pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+			} /* No else for now? */
+		}
+	}
+
+	if (smi_sts & (1 << 8)) { // PM1
+		pm1_sts = reset_pm1_status();
+		dump_pm1_status(pm1_sts);
+	}
+
+	if (smi_sts & (1 << 9)) { // GPE0
+		gpe0_sts = reset_gpe0_status();
+		dump_gpe0_status(gpe0_sts);
+	}
+
+	if (smi_sts & (1 << 5)) { // APM
+		/* Emulate B2 register as the FADT / Linux expects it */
+
+		reg8 = inb(0xb2);
+		switch (reg8) {
+		case ACPI_DISABLE:
+			pmctrl = inw(pmbase + 0x04);
+			pmctrl |= (1 << 0);
+			outw(pmctrl, pmbase + 0x04);
+			printk_debug("SMI#: ACPI disabled.\n");
+			break;
+		case ACPI_ENABLE:
+			pmctrl = inw(pmbase + 0x04);
+			pmctrl &= ~(1 << 0);
+			outw(pmctrl, pmbase + 0x04);
+			printk_debug("SMI#: ACPI enabled.\n");
+			break;
+		}
+	}
+
+	if (smi_sts & (1 << 4)) { // SLP_SMI
+		u32 reg32;
+		reg32 = inl(pmbase + 0x04);
+		printk_debug("SMI#: SLP = 0x%08x\n");
+		printk_debug("SMI#: Powering off.\n");
+		outl((6 << 10), pmbase + 0x04);
+		outl((1 << 13) | (6 << 10), pmbase + 0x04);
+		printk_debug("....\n");
+	}
+
+}
Index: src/southbridge/intel/i82801gx/smm.ld
===================================================================
--- src/southbridge/intel/i82801gx/smm.ld	(revision 3845)
+++ src/southbridge/intel/i82801gx/smm.ld	(working copy)
@@ -1,53 +0,0 @@
-
-/* Maximum number of CPUs/cores */
-CPUS = 4;
-
-SECTIONS
-{
-	/* This is the actual SMM handler. 
-	 *
-	 * We just put code, rodata, data and bss all in a row.
-	 */
-	. = 0xa0000;
-	.handler (.): {
-		/* Assembler stub */
-		*(.handler)
-
-		/* C code of the SMM handler */
-		*(.text);
-		*(.text.*);
-
-		/* C read-only data of the SMM handler */
-		. = ALIGN(16);
-		*(.rodata)
-		*(.rodata.*)
-
-		/* C read-write data of the SMM handler */
-		 . = ALIGN(4);
-		*(.data)
-
-		/* C uninitialized data of the SMM handler */
-		 . = ALIGN(4);
-		*(.bss)
-		*(.sbss)
-
-		/* What is this? */
-		*(COMMON)
-		 . = ALIGN(4);
-	}
-
-	/* We are using the ASEG interleaved to stuff the SMM handlers
-	 * for all CPU cores in there. The jump table redirects the execution
-	 * to the actual SMM handler
-	 */
-	. = 0xa8000 - (( CPUS - 1) * 0x400);
-	.jumptable : {
-		*(.jumptable)
-	}	
-
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.note.*)
-	}
-}
Index: src/southbridge/intel/i82801gx/smmhandler.S
===================================================================
--- src/southbridge/intel/i82801gx/smmhandler.S	(revision 3845)
+++ src/southbridge/intel/i82801gx/smmhandler.S	(working copy)
@@ -1,201 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/* NOTE: This handler assumes the SMM window goes from 0xa0000
- * to 0xaffff. In fact, at least on Intel Core CPUs (i945 chipset)
- * the SMM window is 128K big, covering 0xa0000 to 0xbffff.
- * So there is a lot of potential for growth in here. Let's stick
- * to 64k if we can though.
- */
-
-/*
- * +--------------------------------+ 0xaffff
- * |  Save State Map Node 0         |
- * |  Save State Map Node 1         |
- * |  Save State Map Node 2         |
- * |  Save State Map Node 3         |
- * |  ...                           |
- * +--------------------------------+ 0xaf000
- * |                                |
- * |                                |
- * |                                |
- * +--------------------------------+ 0xa8400
- * | SMM Entry Node 0 (+ stack)     | 
- * +--------------------------------+ 0xa8000
- * | SMM Entry Node 1 (+ stack)     | 
- * | SMM Entry Node 2 (+ stack)     | 
- * | SMM Entry Node 3 (+ stack)     | 
- * | ...                            |
- * +--------------------------------+ 0xa7400
- * |                                |
- * | SMM Handler                    |
- * |                                |
- * +--------------------------------+ 0xa0000
- *
- */
-
-#include <arch/asm.h>
-
-#define LAPIC_ID 0xfee00020
-
-/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG
- * at which smm_handler_start lives. At the moment the handler
- * lives right at 0xa0000, so the offset is 0. 
- */
-
-#define SMM_HANDLER_OFFSET 0x0000
-
-/* initially SMM is some sort of real mode. Let gcc know
- * how to treat the SMM handler stub
- */
-
-.section ".handler", "a", @progbits
-
-.code16
-
-/**
- * SMM code to enable protected mode and jump to the
- * C-written function void smi_handler(u32 smm_revision)
- *
- * All the bad magic is not all that bad after all.
- */
-smm_handler_start:
-	movw    $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx
-	data32  lgdt %cs:(%bx)
-
-	movl    %cr0, %eax
-	andl    $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
-	orl     $0x60000001, %eax /* CD, NW, PE = 1 */
-	movl    %eax, %cr0
-
-	/* Enable protected mode */
-	data32  ljmp    $0x08, $1f
-
-.code32
-1:
-	/* Use flat data segment */
-	movw    $0x10, %ax
-	movw    %ax, %ds
-	movw    %ax, %es
-	movw    %ax, %ss
-	movw    %ax, %fs
-	movw    %ax, %gs
-
-	/* Get this CPU's LAPIC ID */
-	movl $LAPIC_ID, %esi
-	movl (%esi), %ecx
-	shr  $24, %ecx
-	
-	/* calculate stack offset by multiplying the APIC ID
-	 * by 1024 (0x400), and save that offset in ebp.
-	 */
-	shl $10, %ecx
-	movl %ecx, %ebp
-
-	/* We put the stack for each core right above 
-	 * its SMM entry point. Core 0 starts at 0xa8000, 
-	 * we spare 0x10 bytes for the jump to be sure.
-	 */
-	movl $0xa8010, %eax
-	subl %ecx, %eax		/* subtract offset, see above */
-	movl %eax, %ebx		/* Save bottom of stack in ebx */
-
-#define SMM_STACK_SIZE	(0x400 - 0x10)
-	/* clear stack */
-	cld
-	movl	%eax, %edi
-	movl	$(SMM_STACK_SIZE >> 2), %ecx
-	xorl	%eax, %eax
-	rep	stosl
-
-	/* set new stack */
-	addl	$SMM_STACK_SIZE, %ebx
-	movl	%ebx, %esp
-
-	/* Get SMM revision */
-	movl $0xa8000 + 0x7efc, %ebx	/* core 0 address */
-	subl %ebp, %ebx			/* subtract core X offset */
-	movl (%ebx), %eax
-	pushl %eax
-
-	/* Call 32bit C handler */
-	call smi_handler
-
-	/* To return, just do rsm. It will "clean up" protected mode */
-	rsm
-
-.code16
-
-.align	4, 0xff
-
-smm_gdtptr16:
-	.word	smm_gdt_end - smm_gdt - 1
-	.long	smm_gdt - smm_handler_start + 0xa0000 + SMM_HANDLER_OFFSET
-
-.code32
-
-smm_gdt:
-	/* The first GDT entry can not be used. Keep it zero */
-	.long	0x00000000, 0x00000000
-
-	/* gdt selector 0x08, flat code segment */
-	.word	0xffff, 0x0000		
-	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */	
-
-	/* gdt selector 0x10, flat data segment */
-	.word	0xffff, 0x0000		
-	.byte	0x00, 0x93, 0xcf, 0x00
-
-smm_gdt_end:
-
-
-.section ".jumptable", "a", @progbits
-
-/* This is the SMM jump table. All cores use the same SMM handler
- * for simplicity. But SMM Entry needs to be different due to the 
- * save state area. The jump table makes sure all CPUs jump into the
- * real handler on SMM entry.
- */
-
-/* This code currently supports up to 4 CPU cores. If more than 4 CPU cores
- * shall be used, below table has to be updated, as well as smm.ld
- */
-
-/* GNU AS/LD will always generate code that assumes CS is 0xa000. In reality
- * CS will be set to SMM_BASE[19:4] though. Knowing that the smm handler is the
- * first thing in the ASEG, we do a far jump here, to set CS to 0xa000.
- */
-
-.code16
-jumptable:
-	/* core 3 */
-	ljmp $0xa000, $SMM_HANDLER_OFFSET 
-.align 1024, 0x00
-	/* core 2 */
-	ljmp $0xa000, $SMM_HANDLER_OFFSET 
-.align 1024, 0x00
-	/* core 1 */
-	ljmp $0xa000, $SMM_HANDLER_OFFSET 
-.align 1024, 0x00
-	/* core 0 */
-	ljmp $0xa000, $SMM_HANDLER_OFFSET
-.align 1024, 0x00
-
Index: src/southbridge/intel/i82801gx/Config.lb
===================================================================
--- src/southbridge/intel/i82801gx/Config.lb	(revision 3845)
+++ src/southbridge/intel/i82801gx/Config.lb	(working copy)
@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+uses HAVE_SMI_HANDLER
+
 config chip.h
 driver i82801gx.o
 driver i82801gx_ac97.o
@@ -33,34 +35,7 @@
 object i82801gx_reset.o
 object i82801gx_watchdog.o
 
-object i82801gx_smi.o
-object smmrelocate.S
-
-makerule smmhandler.o
-	depends	"$(TOP)/src/southbridge/intel/i82801gx/smmhandler.S" 
-	action	"@$(CC) -c $(CPU_OPT) $(CPPFLAGS) $(CFLAGS) -o $@ $<"
+if HAVE_SMI_HANDLER
+	object i82801gx_smi.o
+	smmobject i82801gx_smihandler.o
 end
-
-makerule smihandler.o
-	depends	"$(TOP)/src/southbridge/intel/i82801gx/smihandler.c" 
-	action	"@$(CC) -c $(CPU_OPT) $(CPPFLAGS) $(CFLAGS) -o $@ $<"
-end
-
-makerule smm.o
-	depends	"smmhandler.o smihandler.o printk.o vtxprintf.o $(LIBGCC_FILE_NAME)" 
-	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ smmhandler.o smihandler.o printk.o vtxprintf.o $(LIBGCC_FILE_NAME)"
-end
-
-makerule smm
-	depends	"smm.o $(TOP)/src/southbridge/intel/i82801gx/smm.ld ldoptions" 
-	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/southbridge/intel/i82801gx/smm.ld smm.o"
-	action 	"$(CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
-	action  "$(OBJCOPY) -O binary smm.elf smm"
-end
-
-makerule smm_bin.c
-	depends "smm"
-	action "(echo 'unsigned char smm[] = {'; od -vtx1 smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c smm |awk '{print $$1;}' ; echo ';')  > smm_bin.c"
-end
-
-object ./smm_bin.o
Index: src/southbridge/intel/i82801gx/smihandler.c
===================================================================
--- src/southbridge/intel/i82801gx/smihandler.c	(revision 3845)
+++ src/southbridge/intel/i82801gx/smihandler.c	(working copy)
@@ -1,551 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <console/console.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/smm.h>
-#include "chip.h"
-
-// Future TODO: Move to i82801gx directory
-#include "../../../northbridge/intel/i945/ich7.h"
-
-#define DEBUG_SMI
-
-#define ACPI_DISABLE	0x1e
-#define ACPI_ENABLE	0xe1
-
-/* I945 */
-#define SMRAM		0x9d
-#define   D_OPEN	(1 << 6)
-#define   D_CLS		(1 << 5)
-#define   D_LCK		(1 << 4)
-#define   G_SMRANE	(1 << 3)
-#define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
-
-/* ICH7 */
-#define PM1_STS		0x00
-#define PM1_EN		0x02
-#define PM1_CNT		0x04
-#define PM1_TMR		0x08
-#define PROC_CNT	0x10
-#define LV2		0x14
-#define LV3		0x15
-#define LV4		0x16
-#define PM2_CNT		0x20 // mobile only
-#define GPE0_STS	0x28
-#define GPE0_EN		0x2c
-#define SMI_EN		0x30
-#define   EL_SMI_EN	 (1 << 25) // Intel Quick Resume Technology
-#define   INTEL_USB2_EN	 (1 << 18) // Intel-Specific USB2 SMI logic
-#define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
-#define   PERIODIC_EN	 (1 << 14) // SMI on PERIODIC_STS in SMI_STS
-#define   TCO_EN	 (1 << 13) // Enable TCO Logic (BIOSWE et al)
-#define   MCSMI_EN	 (1 << 11) // Trap microcontroller range access
-#define   BIOS_RLS	 (1 <<  7) // asserts SCI on bit set
-#define   SWSMI_TMR_EN	 (1 <<  6) // start software smi timer on bit set
-#define   APMC_EN	 (1 <<  5) // Writes to APM_CNT cause SMI#
-#define   SLP_SMI_EN	 (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
-#define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
-#define   BIOS_EN	 (1 <<  2) // Assert SMI# on setting GBL_RLS bit
-#define   EOS		 (1 <<  1) // End of SMI (deassert SMI#)
-#define   GBL_SMI_EN	 (1 <<  0) // SMI# generation at all?
-#define SMI_STS		0x34
-#define ALT_GP_SMI_EN	0x38
-#define ALT_GP_SMI_STS	0x3a
-#define GPE_CNTL	0x42
-#define DEVACT_STS	0x44
-#define SS_CNT		0x50
-#define C3_RES		0x54
-
-#include "i82801gx_nvs.h"
-
-/* While we read PMBASE dynamically in case it changed, let's
- * initialize it with a sane value
- */
-static u16 pmbase = DEFAULT_PMBASE;
-
-typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
-
-/* SMI multiprocessing semaphore */
-static volatile smi_semaphore smi_handler_status = SMI_UNLOCKED;
-
-static int smi_obtain_lock(void)
-{
-	u8 ret = SMI_LOCKED;
-
-	asm volatile (
-		"movb %2, %%al\n"
-		"xchgb %%al, %1\n"
-		"movb %%al, %0\n"
-		: "=g" (ret), "=m" (smi_handler_status)
-		: "g" (SMI_LOCKED)
-		: "eax"
-	);
-
-	return (ret == SMI_UNLOCKED);
-}
-
-static void smi_release_lock(void)
-{
-	asm volatile (
-		"movb %1, %%al\n"
-		"xchgb %%al, %0\n"
-		: "=m" (smi_handler_status)
-		: "g" (SMI_UNLOCKED)
-		: "eax"
-	);
-}
-
-#define LAPIC_ID 0xfee00020
-static inline __attribute__((always_inline)) unsigned long nodeid(void)
-{
-	return (*((volatile unsigned long *)(LAPIC_ID)) >> 24);
-}
-
-
-/**
- * @brief read and clear PM1_STS 
- * @return PM1_STS register
- */
-static u16 reset_pm1_status(void)
-{
-	u16 reg16;
-	
-	reg16 = inw(pmbase + PM1_STS);
-	/* set status bits are cleared by writing 1 to them */
-	outw(reg16, pmbase + PM1_STS);
-	
-	return reg16;
-}
-
-static void dump_pm1_status(u16 pm1_sts)
-{
-	printk_debug("PM1_STS: ");
-	if (pm1_sts & (1 << 15)) printk_debug("WAK ");
-	if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK ");
-	if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR ");
-	if (pm1_sts & (1 << 10)) printk_debug("RTC ");
-	if (pm1_sts & (1 <<  8)) printk_debug("PWRBTN ");
-	if (pm1_sts & (1 <<  5)) printk_debug("GBL ");
-	if (pm1_sts & (1 <<  4)) printk_debug("BM ");
-	if (pm1_sts & (1 <<  0)) printk_debug("TMROF ");
-	printk_debug("\n");
-}
-
-/**
- * @brief read and clear SMI_STS 
- * @return SMI_STS register
- */
-static u32 reset_smi_status(void)
-{
-	u32 reg32;
-	
-	reg32 = inl(pmbase + SMI_STS);
-	/* set status bits are cleared by writing 1 to them */
-	outl(reg32, pmbase + SMI_STS);
-	
-	return reg32;
-}
-
-static void dump_smi_status(u32 smi_sts)
-{
-	printk_debug("SMI_STS: ");
-	if (smi_sts & (1 << 26)) printk_debug("SPI ");
-	if (smi_sts & (1 << 25)) printk_debug("EL_SMI ");
-	if (smi_sts & (1 << 21)) printk_debug("MONITOR ");
-	if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI ");
-	if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 ");
-	if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 ");
-	if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI ");
-	if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI ");
-	if (smi_sts & (1 << 14)) printk_debug("PERIODIC ");
-	if (smi_sts & (1 << 13)) printk_debug("TCO ");
-	if (smi_sts & (1 << 12)) printk_debug("DEVMON ");
-	if (smi_sts & (1 << 11)) printk_debug("MCSMI ");
-	if (smi_sts & (1 << 10)) printk_debug("GPI ");
-	if (smi_sts & (1 <<  9)) printk_debug("GPE0 ");
-	if (smi_sts & (1 <<  8)) printk_debug("PM1 ");
-	if (smi_sts & (1 <<  6)) printk_debug("SWSMI_TMR ");
-	if (smi_sts & (1 <<  5)) printk_debug("APM ");
-	if (smi_sts & (1 <<  4)) printk_debug("SLP_SMI ");
-	if (smi_sts & (1 <<  3)) printk_debug("LEGACY_USB ");
-	if (smi_sts & (1 <<  2)) printk_debug("BIOS ");
-	printk_debug("\n");
-}
-
-
-/**
- * @brief read and clear GPE0_STS
- * @return GPE0_STS register
- */
-static u32 reset_gpe0_status(void)
-{
-	u32 reg32;
-	
-	reg32 = inl(pmbase + GPE0_STS);
-	/* set status bits are cleared by writing 1 to them */
-	outl(reg32, pmbase + GPE0_STS);
-	
-	return reg32;
-}
-
-static void dump_gpe0_status(u32 gpe0_sts)
-{
-	int i;
-	printk_debug("GPE0_STS: ");
-	for (i=31; i<= 16; i--) {
-		if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16));
-	}
-	if (gpe0_sts & (1 << 14)) printk_debug("USB4 ");
-	if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 ");
-	if (gpe0_sts & (1 << 12)) printk_debug("USB3 ");
-	if (gpe0_sts & (1 << 11)) printk_debug("PME ");
-	if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW ");
-	if (gpe0_sts & (1 <<  9)) printk_debug("PCI_EXP ");
-	if (gpe0_sts & (1 <<  8)) printk_debug("RI ");
-	if (gpe0_sts & (1 <<  7)) printk_debug("SMB_WAK ");
-	if (gpe0_sts & (1 <<  6)) printk_debug("TCO_SCI ");
-	if (gpe0_sts & (1 <<  5)) printk_debug("AC97 ");
-	if (gpe0_sts & (1 <<  4)) printk_debug("USB2 ");
-	if (gpe0_sts & (1 <<  3)) printk_debug("USB1 ");
-	if (gpe0_sts & (1 <<  2)) printk_debug("HOT_PLUG ");
-	if (gpe0_sts & (1 <<  0)) printk_debug("THRM ");
-	printk_debug("\n");
-}
-
-
-/**
- * @brief read and clear TCOx_STS 
- * @return TCOx_STS registers
- */
-static u32 reset_tco_status(void)
-{
-	u32 tcobase = pmbase + 0x60;
-	u32 reg32;
-	
-	reg32 = inl(tcobase + 0x04);
-	/* set status bits are cleared by writing 1 to them */
-	outl(reg32 & ~(1<<18), tcobase + 0x04); //  Don't clear BOOT_STS before SECOND_TO_STS
-	if (reg32 & (1 << 18))
-		outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
-	
-	return reg32;
-}
-
-
-static void dump_tco_status(u32 tco_sts)
-{
-	printk_debug("TCO_STS: ");
-	if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV ");
-	if (tco_sts & (1 << 18)) printk_debug("BOOT ");
-	if (tco_sts & (1 << 17)) printk_debug("SECOND_TO ");
-	if (tco_sts & (1 << 16)) printk_debug("INTRD_DET ");
-	if (tco_sts & (1 << 12)) printk_debug("DMISERR ");
-	if (tco_sts & (1 << 10)) printk_debug("DMISMI ");
-	if (tco_sts & (1 <<  9)) printk_debug("DMISCI ");
-	if (tco_sts & (1 <<  8)) printk_debug("BIOSWR ");
-	if (tco_sts & (1 <<  7)) printk_debug("NEWCENTURY ");
-	if (tco_sts & (1 <<  3)) printk_debug("TIMEOUT ");
-	if (tco_sts & (1 <<  2)) printk_debug("TCO_INT ");
-	if (tco_sts & (1 <<  1)) printk_debug("SW_TCO ");
-	if (tco_sts & (1 <<  0)) printk_debug("NMI2SMI ");
-	printk_debug("\n");
-}
-
-
-/* ********************* smi_util ************************* */
-
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define UART_IIR 0x02
-#define UART_FCR 0x02
-#define UART_LCR 0x03
-#define UART_MCR 0x04
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define UART_MSR 0x06
-#define UART_SCR 0x07
-
-static int uart_can_tx_byte(void)
-{
-	return inb(TTYS0_BASE + UART_LSR) & 0x20;
-}
-
-static void uart_wait_to_tx_byte(void)
-{
-	while(!uart_can_tx_byte()) 
-	;
-}
-
-static void uart_wait_until_sent(void)
-{
-	while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
-	; 
-}
-
-static void uart_tx_byte(unsigned char data)
-{
-	uart_wait_to_tx_byte();
-	outb(data, TTYS0_BASE + UART_TBR);
-	/* Make certain the data clears the fifos */
-	uart_wait_until_sent();
-}
-
-void console_tx_flush(void)
-{
-	uart_wait_to_tx_byte();
-}
-
-void console_tx_byte(unsigned char byte)
-{
-	if (byte == '\n')
-		uart_tx_byte('\r');
-	uart_tx_byte(byte);
-}
-
-/* We are using PCIe accesses for now
- *  1. the chipset can do it
- *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-#include "../../../northbridge/intel/i945/pcie_config.c"
-
-/* ********************* smi_util ************************* */
-
-
-void io_trap_handler(int smif)
-{
-	u8 reg8;
-	global_nvs_t *gnvs = (global_nvs_t *)0xc00;
-
-	printk_debug("SMI function trap 0x%x: ", smif);
-
-
-	switch (smif) {
-	case 0x32:
-		printk_debug("OS Init\n");
-		break;
-	case 0xd6:
-		printk_debug("Get Brightness\n");
-		outb(0x17, 0x66);
-		reg8 = inb(0x62);
-		gnvs->brtl = reg8;
-		break;
-	default:
-		printk_debug("Unknown function\n");
-		break;
-	}
-
-	/* On success, the IO Trap Handler returns 0
-	 * On failure, the IO Trap Handler returns a value != 0
-	 *
-	 * For now, we force the return value to 0 and log all traps to
-	 * see what's going on.
-	 */
-	//gnvs->smif = 0;
-}
-
-/**
- * @brief Set the EOS bit
- */
-static void smi_set_eos(void)
-{
-	u8 reg8;
-	
-	reg8 = inb(pmbase + SMI_EN);
-	reg8 |= EOS;
-	outb(reg8, pmbase + SMI_EN);
-}
-
-/**
- * @brief Interrupt handler for SMI#
- *
- * @param smm_revision revision of the smm state save map
- */
-
-void smi_handler(u32 smm_revision)
-{
-	u8 reg8;
-	u16 pmctrl;
-	u16 pm1_sts;
-	u32 smi_sts, gpe0_sts, tco_sts;
-	unsigned int node;
-	smm_state_save_area_t state_save;
-
-	/* Are we ok to execute the handler? */
-	if (!smi_obtain_lock())
-		return;
-
-	node=nodeid();
-
-#ifdef DEBUG_SMI
-	console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
-#else
-	console_loglevel = 1;
-#endif
-
-	printk_debug("\nSMI# #%d\n", node);
-
-	switch (smm_revision) {
-	case 0x00030007:
-		state_save.type = LEGACY;
-		state_save.legacy_state_save = (legacy_smm_state_save_area_t *)
-			(0xa8000 + 0x7e00 - (node * 0x400));
-		break;
-	case 0x00030100:
-		state_save.type = EM64T;
-		state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
-			(0xa8000 + 0x7d00 - (node * 0x400));
-		break;
-	default:
-		printk_debug("smm_revision: 0x%08x\n", smm_revision);
-		printk_debug("SMI# not supported on your CPU\n");
-		/* Don't release lock, so no further SMI will happen,
-		 * if we don't handle it anyways.
-		 */
-		return;
-	}
-
-	pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
-	printk_spew("SMI#: pmbase = 0x%04x\n", pmbase);
-	
-	/* We need to clear the SMI status registers, or we won't see what's
-	 * happening in the following calls.
-	 */
-	smi_sts = reset_smi_status();
-	dump_smi_status(smi_sts);
-
-	if (smi_sts & (1 << 21)) { // MONITOR
-		global_nvs_t *gnvs = (global_nvs_t *)0xc00;
-		int i;
-		u32 reg32;
-
-		reg32 = RCBA32(0x1e00); // TRSR - Trap Status Register
-#if 0
-		/* Comment in for some useful debug */
-		for (i=0; i<4; i++) {
-			if (reg32 & (1 << i)) {
-				printk_debug("  io trap #%d\n", i);
-			}
-		}
-#endif
-		RCBA32(0x1e00) = reg32; // TRSR
-
-		reg32 = RCBA32(0x1e10);
-
-		if ((reg32 & 0xfffc) != 0x808) {
-			printk_debug("  trapped io address = 0x%x\n", reg32 & 0xfffc);
-			printk_debug("  AHBE = %x\n", (reg32 >> 16) & 0xf);
-			printk_debug("  read/write: %s\n", (reg32 & (1 << 24)) ? "read" :
-				"write");
-		}
-
-		if (!(reg32 & (1 << 24))) {
-			/* Write Cycle */
-			reg32 = RCBA32(0x1e18);
-			printk_debug("  iotrap written data = 0x%08x\n", reg32);
-
-		}
-
-		if (gnvs->smif)
-			io_trap_handler(gnvs->smif); // call function smif
-	}
-
-	if (smi_sts & (1 << 13)) { // TCO
-		tco_sts = reset_tco_status();
-		dump_tco_status(tco_sts);
-
-		if (tco_sts & (1 << 8)) { // BIOSWR
-			u8 bios_cntl;
-
-			bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
-
-			if (bios_cntl & 1) {
-				/* BWE is RW, so the SMI was caused by a
-				 * write to BWE, not by a write to the BIOS
-				 */
-
-				/* This is the place where we notice someone
-				 * is trying to tinker with the BIOS. We are
-				 * trying to be nice and just ignore it. A more
-				 * resolute answer would be to power down the
-				 * box.
-				 */
-				printk_debug("Switching back to RO\n");
-				pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
-			} /* No else for now? */
-		}
-	}
-
-	if (smi_sts & (1 << 8)) { // PM1
-		pm1_sts = reset_pm1_status();
-		dump_pm1_status(pm1_sts);
-	}
-
-	if (smi_sts & (1 << 9)) { // GPE0
-		gpe0_sts = reset_gpe0_status();
-		dump_gpe0_status(gpe0_sts);
-	}
-
-	if (smi_sts & (1 << 5)) { // APM
-		/* Emulate B2 register as the FADT / Linux expects it */
-
-		reg8 = inb(0xb2);
-		switch (reg8) {
-		case ACPI_DISABLE:
-			pmctrl = inw(pmbase + 0x04);
-			pmctrl |= (1 << 0);
-			outw(pmctrl, pmbase + 0x04);
-			printk_debug("SMI#: ACPI disabled.\n");
-			break;
-		case ACPI_ENABLE:
-			pmctrl = inw(pmbase + 0x04);
-			pmctrl &= ~(1 << 0);
-			outw(pmctrl, pmbase + 0x04);
-			printk_debug("SMI#: ACPI enabled.\n");
-			break;
-		}
-	}
-
-	if (smi_sts & (1 << 4)) { // SLP_SMI
-		u32 reg32;
-		reg32 = inl(pmbase + 0x04);
-		printk_debug("SMI#: SLP = 0x%08x\n");
-		printk_debug("SMI#: Powering off.\n");
-		outl((6 << 10), pmbase + 0x04);
-		outl((1 << 13) | (6 << 10), pmbase + 0x04);
-		printk_debug("....\n");
-	}
-
-
-	smi_release_lock();
-
-	/* De-assert SMI# signal to allow another SMI */
-	smi_set_eos();
-}
Index: src/southbridge/intel/i82801gx/i82801gx_lpc.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_lpc.c	(revision 3845)
+++ src/southbridge/intel/i82801gx/i82801gx_lpc.c	(working copy)
@@ -197,6 +197,8 @@
 	/* TODO */
 }
 
+
+#if HAVE_SMI_HANDLER
 static void i82801gx_lock_smm(struct device *dev)
 {
 	void smm_lock(void);
@@ -243,6 +245,7 @@
 	printk_debug("Done.\n");
 #endif
 }
+#endif
 
 static void lpc_init(struct device *dev)
 {
@@ -276,7 +279,9 @@
 
 	setup_i8259();
 
+#if HAVE_SMI_HANDLER
 	i82801gx_lock_smm(dev);
+#endif
 }
 
 static void i82801gx_lpc_read_resources(device_t dev)
Index: src/southbridge/intel/i82801gx/smmrelocate.S
===================================================================
--- src/southbridge/intel/i82801gx/smmrelocate.S	(revision 3845)
+++ src/southbridge/intel/i82801gx/smmrelocate.S	(working copy)
@@ -1,168 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/asm.h>
-#include "../../../../src/northbridge/intel/i945/ich7.h"
-
-#undef DEBUG_SMM_RELOCATION
-//#define DEBUG_SMM_RELOCATION
-
-#define LAPIC_ID 0xfee00020
-
-.global smm_relocation_start
-.global smm_relocation_end
-
-/* initially SMM is some sort of real mode. */
-.code16
-
-/**
- * This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 )
- *
- * Why 0x400? It is a safe value to cover the save state area per CPU. On
- * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel
- * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes
- * bigger, effectively sizing our data structures 0x300 bytes.
- *
- * LAPICID	SMBASE		SMM Entry 	SAVE STATE
- *    0		0xa0000		0xa8000		0xafd00
- *    1		0x9fc00		0xa7c00		0xaf900
- *    2		0x9f800		0xa7800		0xaf500
- *    3		0x9f400		0xa7400		0xaf100
- *    4		0x9f000		0xa7000		0xaed00
- *    5		0x9ec00		0xa6c00		0xae900
- *    6		0x9e800		0xa6800		0xae500
- *    7		0x9e400		0xa6400		0xae100
- *    8		0x9e000		0xa6000		0xadd00
- *    9		0x9dc00		0xa5c00		0xad900
- *   10		0x9d800		0xa5800		0xad500
- *   11		0x9d400		0xa5400		0xad100
- *   12		0x9d000		0xa5000		0xacd00
- *   13		0x9cc00		0xa4c00		0xac900
- *   14		0x9c800		0xa4800		0xac500
- *   15		0x9c400		0xa4400		0xac100
- *    .		   .		   .		   .
- *    .		   .		   .		   .
- *    .		   .		   .		   .
- *   31		0x98400		0xa0400		0xa8100
- *
- * With 32 cores, the SMM handler would need to fit between
- * 0xa0000-0xa0400 and the stub plus stack would need to go
- * at 0xa8000-0xa8100 (example for core 0). That is not enough.
- *
- * This means we're basically limited to 16 cpu cores before 
- * we need to use the TSEG/HSEG for the actual SMM handler plus stack.
- * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG.
- *
- * If we figure out the documented values above are safe to use,
- * we could pack the structure above even more, so we could use the
- * scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs
- * in the ASEG.
- *
- * Note: Some versions of Pentium M need their SMBASE aligned to 32k.
- * On those the above only works for up to 2 cores. But for now we only
- * care fore Core (2) Duo/Solo
- *
- */
-
-smm_relocation_start:
-	/* Check revision to see if AMD64 style SMM_BASE
-	 *   Intel Core Solo/Duo:  0x30007
-	 *   Intel Core2 Solo/Duo: 0x30100
-	 *   AMD64:                0x3XX64
-	 * This check does not make much sense, unless someone ports
-	 * SMI handling to AMD64 CPUs.
-	 */
-
-	mov $0x38000 + 0x7efc, %ebx
-	addr32 mov (%ebx), %al
-	cmp $0x64, %al
-	je 1f
- 
-	mov $0x38000 + 0x7ef8, %ebx
-	jmp smm_relocate
-1:
-	mov $0x38000 + 0x7f00, %ebx
-
-smm_relocate:
-	/* Get this CPU's LAPIC ID */
-	movl $LAPIC_ID, %esi
-	addr32 movl (%esi), %ecx
-	shr  $24, %ecx
-	
-	/* calculate offset by multiplying the 
-	 * apic ID by 1024 (0x400)
-	 */
-	movl %ecx, %edx
-	shl $10, %edx
-
-	movl $0xa0000, %eax
-	subl %edx, %eax	/* subtract offset, see above */
-
-	addr32 movl %eax, (%ebx)
-
-
-	/* The next section of code is hardware specific */
-
-	/* Clear SMI status */
-	movw $(DEFAULT_PMBASE + 0x34), %dx
-	inw %dx, %ax
-	outw %ax, %dx
-
-	/* Clear PM1 status */
-	movw $(DEFAULT_PMBASE + 0x00), %dx
-	inw %dx, %ax
-	outw %ax, %dx
-
-	/* Set EOS bit so other SMIs can occur */
-	movw $(DEFAULT_PMBASE + 0x30), %dx
-	inl %dx, %eax
-	orl $(1 << 1), %eax
-	outl %eax, %dx
-
-	/* End of hardware specific section. */
-#ifdef DEBUG_SMM_RELOCATION
-	/* print [SMM-x] so we can determine if CPUx went to SMM */
-	movw $TTYS0_BASE, %dx
-	mov $'[', %al
-	outb %al, %dx
-	mov $'S', %al
-	outb %al, %dx
-	mov $'M', %al
-	outb %al, %dx
-	outb %al, %dx
-	movb $'-', %al
-	outb %al, %dx
-	/* calculate ascii of cpu number. More than 9 cores? -> FIXME */
-	movb %cl, %al
-	addb $'0', %al 
-	outb %al, %dx
-	mov $']', %al
-	outb %al, %dx
-	mov $'\r', %al
-	outb %al, %dx
-	mov $'\n', %al
-	outb %al, %dx
-#endif
-
-	/* That's it. return */
-	rsm
-smm_relocation_end:
-
Index: src/cpu/via/model_c3/Config.lb
===================================================================
--- src/cpu/via/model_c3/Config.lb	(revision 3845)
+++ src/cpu/via/model_c3/Config.lb	(working copy)
@@ -26,5 +26,6 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 driver model_c3_init.o
Index: src/cpu/via/model_c7/Config.lb
===================================================================
--- src/cpu/via/model_c7/Config.lb	(revision 3845)
+++ src/cpu/via/model_c7/Config.lb	(working copy)
@@ -26,5 +26,6 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 driver model_c7_init.o
Index: src/cpu/amd/model_gx1/Config.lb
===================================================================
--- src/cpu/amd/model_gx1/Config.lb	(revision 3845)
+++ src/cpu/amd/model_gx1/Config.lb	(working copy)
@@ -3,4 +3,5 @@
 dir /cpu/x86/mmx
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 driver model_gx1_init.o
Index: src/cpu/amd/model_gx2/Config.lb
===================================================================
--- src/cpu/amd/model_gx2/Config.lb	(revision 3845)
+++ src/cpu/amd/model_gx2/Config.lb	(working copy)
@@ -3,6 +3,7 @@
 dir /cpu/x86/mmx
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 driver model_gx2_init.o
 object cpubug.o
-object vsmsetup.o
\ No newline at end of file
+object vsmsetup.o
Index: src/cpu/amd/model_fxx/Config.lb
===================================================================
--- src/cpu/amd/model_fxx/Config.lb	(revision 3845)
+++ src/cpu/amd/model_fxx/Config.lb	(working copy)
@@ -12,6 +12,7 @@
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
 dir /cpu/x86/pae
+dir /cpu/x86/smm
 dir /cpu/amd/mtrr
 dir /cpu/amd/dualcore
 dir /cpu/amd/microcode
Index: src/cpu/amd/model_lx/Config.lb
===================================================================
--- src/cpu/amd/model_lx/Config.lb	(revision 3845)
+++ src/cpu/amd/model_lx/Config.lb	(working copy)
@@ -3,6 +3,7 @@
 dir /cpu/x86/mmx
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 driver model_lx_init.o
 object cpubug.o
-object vsmsetup.o
\ No newline at end of file
+object vsmsetup.o
Index: src/cpu/amd/model_10xxx/Config.lb
===================================================================
--- src/cpu/amd/model_10xxx/Config.lb	(revision 3845)
+++ src/cpu/amd/model_10xxx/Config.lb	(working copy)
@@ -31,6 +31,7 @@
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
 dir /cpu/x86/pae
+dir /cpu/x86/smm
 dir /cpu/amd/mtrr
 dir /cpu/amd/quadcore
 dir /cpu/amd/microcode
Index: src/cpu/x86/smm/Config.lb
===================================================================
--- src/cpu/x86/smm/Config.lb	(revision 0)
+++ src/cpu/x86/smm/Config.lb	(revision 0)
@@ -0,0 +1,47 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+uses HAVE_SMI_HANDLER
+
+if HAVE_SMI_HANDLER
+	object smmrelocate.S
+
+	smmobject smmhandler.S
+	smmobject smihandler.o
+
+	makerule smm.o
+		depends	"$(SMM-OBJECTS) printk.o vtxprintf.o $(LIBGCC_FILE_NAME)" 
+		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $(SMM-OBJECTS) printk.o vtxprintf.o $(LIBGCC_FILE_NAME)"
+	end
+
+	makerule smm
+		depends	"smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions" 
+		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o"
+		action 	"$(CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
+		action  "$(OBJCOPY) -O binary smm.elf smm"
+	end
+
+	makerule smm_bin.c
+		depends "smm"
+		action "(echo 'unsigned char smm[] = {'; od -vtx1 smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c smm |awk '{print $$1;}' ; echo ';')  > smm_bin.c"
+	end
+
+	object ./smm_bin.o
+end
Index: src/cpu/x86/smm/smihandler.c
===================================================================
--- src/cpu/x86/smm/smihandler.c	(revision 0)
+++ src/cpu/x86/smm/smihandler.c	(revision 0)
@@ -0,0 +1,203 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+
+void southbridge_smi_set_eos(void);
+
+#define DEBUG_SMI
+
+typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
+
+/* SMI multiprocessing semaphore */
+static volatile smi_semaphore smi_handler_status = SMI_UNLOCKED;
+
+static int smi_obtain_lock(void)
+{
+	u8 ret = SMI_LOCKED;
+
+	asm volatile (
+		"movb %2, %%al\n"
+		"xchgb %%al, %1\n"
+		"movb %%al, %0\n"
+		: "=g" (ret), "=m" (smi_handler_status)
+		: "g" (SMI_LOCKED)
+		: "eax"
+	);
+
+	return (ret == SMI_UNLOCKED);
+}
+
+static void smi_release_lock(void)
+{
+	asm volatile (
+		"movb %1, %%al\n"
+		"xchgb %%al, %0\n"
+		: "=m" (smi_handler_status)
+		: "g" (SMI_UNLOCKED)
+		: "eax"
+	);
+}
+
+#define LAPIC_ID 0xfee00020
+static inline __attribute__((always_inline)) unsigned long nodeid(void)
+{
+	return (*((volatile unsigned long *)(LAPIC_ID)) >> 24);
+}
+
+/* ********************* smi_util ************************* */
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+static int uart_can_tx_byte(void)
+{
+	return inb(TTYS0_BASE + UART_LSR) & 0x20;
+}
+
+static void uart_wait_to_tx_byte(void)
+{
+	while(!uart_can_tx_byte()) 
+	;
+}
+
+static void uart_wait_until_sent(void)
+{
+	while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
+	; 
+}
+
+static void uart_tx_byte(unsigned char data)
+{
+	uart_wait_to_tx_byte();
+	outb(data, TTYS0_BASE + UART_TBR);
+	/* Make certain the data clears the fifos */
+	uart_wait_until_sent();
+}
+
+void console_tx_flush(void)
+{
+	uart_wait_to_tx_byte();
+}
+
+void console_tx_byte(unsigned char byte)
+{
+	if (byte == '\n')
+		uart_tx_byte('\r');
+	uart_tx_byte(byte);
+}
+
+/* ********************* smi_util ************************* */
+
+
+void io_trap_handler(int smif)
+{
+	southbridge_io_trap_handler(smif);
+}
+
+/**
+ * @brief Set the EOS bit
+ */
+static void smi_set_eos(void)
+{
+	southbridge_smi_set_eos();
+}
+
+/**
+ * @brief Interrupt handler for SMI#
+ *
+ * @param smm_revision revision of the smm state save map
+ */
+
+void smi_handler(u32 smm_revision)
+{
+	u8 reg8;
+	u16 pmctrl;
+	u16 pm1_sts;
+	u32 smi_sts, gpe0_sts, tco_sts;
+	unsigned int node;
+	smm_state_save_area_t state_save;
+
+	/* Are we ok to execute the handler? */
+	if (!smi_obtain_lock())
+		return;
+
+	node=nodeid();
+
+#ifdef DEBUG_SMI
+	console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
+#else
+	console_loglevel = 1;
+#endif
+
+	printk_debug("\nSMI# #%d\n", node);
+
+	switch (smm_revision) {
+	case 0x00030007:
+		state_save.type = LEGACY;
+		state_save.legacy_state_save = (legacy_smm_state_save_area_t *)
+			(0xa8000 + 0x7e00 - (node * 0x400));
+		break;
+	case 0x00030100:
+		state_save.type = EM64T;
+		state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
+			(0xa8000 + 0x7d00 - (node * 0x400));
+		break;
+	case 0x00030064:
+		state_save.type = AMD64;
+		state_save.amd64_state_save = (amd64_smm_state_save_area_t *)
+			(0xa8000 + 0x7e00 - (node * 0x400));
+		break;
+	default:
+		printk_debug("smm_revision: 0x%08x\n", smm_revision);
+		printk_debug("SMI# not supported on your CPU\n");
+		/* Don't release lock, so no further SMI will happen,
+		 * if we don't handle it anyways.
+		 */
+		return;
+	}
+
+	southbridge_smi_handler(node, &state_save);
+
+	smi_release_lock();
+
+	/* De-assert SMI# signal to allow another SMI */
+	smi_set_eos();
+}
Index: src/cpu/x86/smm/smm.ld
===================================================================
--- src/cpu/x86/smm/smm.ld	(revision 0)
+++ src/cpu/x86/smm/smm.ld	(revision 0)
@@ -0,0 +1,53 @@
+
+/* Maximum number of CPUs/cores */
+CPUS = 4;
+
+SECTIONS
+{
+	/* This is the actual SMM handler. 
+	 *
+	 * We just put code, rodata, data and bss all in a row.
+	 */
+	. = 0xa0000;
+	.handler (.): {
+		/* Assembler stub */
+		*(.handler)
+
+		/* C code of the SMM handler */
+		*(.text);
+		*(.text.*);
+
+		/* C read-only data of the SMM handler */
+		. = ALIGN(16);
+		*(.rodata)
+		*(.rodata.*)
+
+		/* C read-write data of the SMM handler */
+		 . = ALIGN(4);
+		*(.data)
+
+		/* C uninitialized data of the SMM handler */
+		 . = ALIGN(4);
+		*(.bss)
+		*(.sbss)
+
+		/* What is this? */
+		*(COMMON)
+		 . = ALIGN(4);
+	}
+
+	/* We are using the ASEG interleaved to stuff the SMM handlers
+	 * for all CPU cores in there. The jump table redirects the execution
+	 * to the actual SMM handler
+	 */
+	. = 0xa8000 - (( CPUS - 1) * 0x400);
+	.jumptable : {
+		*(.jumptable)
+	}	
+
+	/DISCARD/ : {
+		*(.comment)
+		*(.note)
+		*(.note.*)
+	}
+}
Index: src/cpu/x86/smm/smmhandler.S
===================================================================
--- src/cpu/x86/smm/smmhandler.S	(revision 0)
+++ src/cpu/x86/smm/smmhandler.S	(revision 0)
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* NOTE: This handler assumes the SMM window goes from 0xa0000
+ * to 0xaffff. In fact, at least on Intel Core CPUs (i945 chipset)
+ * the SMM window is 128K big, covering 0xa0000 to 0xbffff.
+ * So there is a lot of potential for growth in here. Let's stick
+ * to 64k if we can though.
+ */
+
+/*
+ * +--------------------------------+ 0xaffff
+ * |  Save State Map Node 0         |
+ * |  Save State Map Node 1         |
+ * |  Save State Map Node 2         |
+ * |  Save State Map Node 3         |
+ * |  ...                           |
+ * +--------------------------------+ 0xaf000
+ * |                                |
+ * |                                |
+ * |                                |
+ * +--------------------------------+ 0xa8400
+ * | SMM Entry Node 0 (+ stack)     | 
+ * +--------------------------------+ 0xa8000
+ * | SMM Entry Node 1 (+ stack)     | 
+ * | SMM Entry Node 2 (+ stack)     | 
+ * | SMM Entry Node 3 (+ stack)     | 
+ * | ...                            |
+ * +--------------------------------+ 0xa7400
+ * |                                |
+ * | SMM Handler                    |
+ * |                                |
+ * +--------------------------------+ 0xa0000
+ *
+ */
+
+#include <arch/asm.h>
+
+#define LAPIC_ID 0xfee00020
+
+/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG
+ * at which smm_handler_start lives. At the moment the handler
+ * lives right at 0xa0000, so the offset is 0. 
+ */
+
+#define SMM_HANDLER_OFFSET 0x0000
+
+/* initially SMM is some sort of real mode. Let gcc know
+ * how to treat the SMM handler stub
+ */
+
+.section ".handler", "a", @progbits
+
+.code16
+
+/**
+ * SMM code to enable protected mode and jump to the
+ * C-written function void smi_handler(u32 smm_revision)
+ *
+ * All the bad magic is not all that bad after all.
+ */
+smm_handler_start:
+	movw    $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx
+	data32  lgdt %cs:(%bx)
+
+	movl    %cr0, %eax
+	andl    $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
+	orl     $0x60000001, %eax /* CD, NW, PE = 1 */
+	movl    %eax, %cr0
+
+	/* Enable protected mode */
+	data32  ljmp    $0x08, $1f
+
+.code32
+1:
+	/* Use flat data segment */
+	movw    $0x10, %ax
+	movw    %ax, %ds
+	movw    %ax, %es
+	movw    %ax, %ss
+	movw    %ax, %fs
+	movw    %ax, %gs
+
+	/* Get this CPU's LAPIC ID */
+	movl $LAPIC_ID, %esi
+	movl (%esi), %ecx
+	shr  $24, %ecx
+	
+	/* calculate stack offset by multiplying the APIC ID
+	 * by 1024 (0x400), and save that offset in ebp.
+	 */
+	shl $10, %ecx
+	movl %ecx, %ebp
+
+	/* We put the stack for each core right above 
+	 * its SMM entry point. Core 0 starts at 0xa8000, 
+	 * we spare 0x10 bytes for the jump to be sure.
+	 */
+	movl $0xa8010, %eax
+	subl %ecx, %eax		/* subtract offset, see above */
+	movl %eax, %ebx		/* Save bottom of stack in ebx */
+
+#define SMM_STACK_SIZE	(0x400 - 0x10)
+	/* clear stack */
+	cld
+	movl	%eax, %edi
+	movl	$(SMM_STACK_SIZE >> 2), %ecx
+	xorl	%eax, %eax
+	rep	stosl
+
+	/* set new stack */
+	addl	$SMM_STACK_SIZE, %ebx
+	movl	%ebx, %esp
+
+	/* Get SMM revision */
+	movl $0xa8000 + 0x7efc, %ebx	/* core 0 address */
+	subl %ebp, %ebx			/* subtract core X offset */
+	movl (%ebx), %eax
+	pushl %eax
+
+	/* Call 32bit C handler */
+	call smi_handler
+
+	/* To return, just do rsm. It will "clean up" protected mode */
+	rsm
+
+.code16
+
+.align	4, 0xff
+
+smm_gdtptr16:
+	.word	smm_gdt_end - smm_gdt - 1
+	.long	smm_gdt - smm_handler_start + 0xa0000 + SMM_HANDLER_OFFSET
+
+.code32
+
+smm_gdt:
+	/* The first GDT entry can not be used. Keep it zero */
+	.long	0x00000000, 0x00000000
+
+	/* gdt selector 0x08, flat code segment */
+	.word	0xffff, 0x0000		
+	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */	
+
+	/* gdt selector 0x10, flat data segment */
+	.word	0xffff, 0x0000		
+	.byte	0x00, 0x93, 0xcf, 0x00
+
+smm_gdt_end:
+
+
+.section ".jumptable", "a", @progbits
+
+/* This is the SMM jump table. All cores use the same SMM handler
+ * for simplicity. But SMM Entry needs to be different due to the 
+ * save state area. The jump table makes sure all CPUs jump into the
+ * real handler on SMM entry.
+ */
+
+/* This code currently supports up to 4 CPU cores. If more than 4 CPU cores
+ * shall be used, below table has to be updated, as well as smm.ld
+ */
+
+/* GNU AS/LD will always generate code that assumes CS is 0xa000. In reality
+ * CS will be set to SMM_BASE[19:4] though. Knowing that the smm handler is the
+ * first thing in the ASEG, we do a far jump here, to set CS to 0xa000.
+ */
+
+.code16
+jumptable:
+	/* core 3 */
+	ljmp $0xa000, $SMM_HANDLER_OFFSET 
+.align 1024, 0x00
+	/* core 2 */
+	ljmp $0xa000, $SMM_HANDLER_OFFSET 
+.align 1024, 0x00
+	/* core 1 */
+	ljmp $0xa000, $SMM_HANDLER_OFFSET 
+.align 1024, 0x00
+	/* core 0 */
+	ljmp $0xa000, $SMM_HANDLER_OFFSET
+.align 1024, 0x00
+
Index: src/cpu/x86/smm/smmrelocate.S
===================================================================
--- src/cpu/x86/smm/smmrelocate.S	(revision 0)
+++ src/cpu/x86/smm/smmrelocate.S	(revision 0)
@@ -0,0 +1,168 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/asm.h>
+#include "../../../../src/northbridge/intel/i945/ich7.h"
+
+#undef DEBUG_SMM_RELOCATION
+//#define DEBUG_SMM_RELOCATION
+
+#define LAPIC_ID 0xfee00020
+
+.global smm_relocation_start
+.global smm_relocation_end
+
+/* initially SMM is some sort of real mode. */
+.code16
+
+/**
+ * This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 )
+ *
+ * Why 0x400? It is a safe value to cover the save state area per CPU. On
+ * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel
+ * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes
+ * bigger, effectively sizing our data structures 0x300 bytes.
+ *
+ * LAPICID	SMBASE		SMM Entry 	SAVE STATE
+ *    0		0xa0000		0xa8000		0xafd00
+ *    1		0x9fc00		0xa7c00		0xaf900
+ *    2		0x9f800		0xa7800		0xaf500
+ *    3		0x9f400		0xa7400		0xaf100
+ *    4		0x9f000		0xa7000		0xaed00
+ *    5		0x9ec00		0xa6c00		0xae900
+ *    6		0x9e800		0xa6800		0xae500
+ *    7		0x9e400		0xa6400		0xae100
+ *    8		0x9e000		0xa6000		0xadd00
+ *    9		0x9dc00		0xa5c00		0xad900
+ *   10		0x9d800		0xa5800		0xad500
+ *   11		0x9d400		0xa5400		0xad100
+ *   12		0x9d000		0xa5000		0xacd00
+ *   13		0x9cc00		0xa4c00		0xac900
+ *   14		0x9c800		0xa4800		0xac500
+ *   15		0x9c400		0xa4400		0xac100
+ *    .		   .		   .		   .
+ *    .		   .		   .		   .
+ *    .		   .		   .		   .
+ *   31		0x98400		0xa0400		0xa8100
+ *
+ * With 32 cores, the SMM handler would need to fit between
+ * 0xa0000-0xa0400 and the stub plus stack would need to go
+ * at 0xa8000-0xa8100 (example for core 0). That is not enough.
+ *
+ * This means we're basically limited to 16 cpu cores before 
+ * we need to use the TSEG/HSEG for the actual SMM handler plus stack.
+ * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG.
+ *
+ * If we figure out the documented values above are safe to use,
+ * we could pack the structure above even more, so we could use the
+ * scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs
+ * in the ASEG.
+ *
+ * Note: Some versions of Pentium M need their SMBASE aligned to 32k.
+ * On those the above only works for up to 2 cores. But for now we only
+ * care fore Core (2) Duo/Solo
+ *
+ */
+
+smm_relocation_start:
+	/* Check revision to see if AMD64 style SMM_BASE
+	 *   Intel Core Solo/Duo:  0x30007
+	 *   Intel Core2 Solo/Duo: 0x30100
+	 *   AMD64:                0x3XX64
+	 * This check does not make much sense, unless someone ports
+	 * SMI handling to AMD64 CPUs.
+	 */
+
+	mov $0x38000 + 0x7efc, %ebx
+	addr32 mov (%ebx), %al
+	cmp $0x64, %al
+	je 1f
+ 
+	mov $0x38000 + 0x7ef8, %ebx
+	jmp smm_relocate
+1:
+	mov $0x38000 + 0x7f00, %ebx
+
+smm_relocate:
+	/* Get this CPU's LAPIC ID */
+	movl $LAPIC_ID, %esi
+	addr32 movl (%esi), %ecx
+	shr  $24, %ecx
+	
+	/* calculate offset by multiplying the 
+	 * apic ID by 1024 (0x400)
+	 */
+	movl %ecx, %edx
+	shl $10, %edx
+
+	movl $0xa0000, %eax
+	subl %edx, %eax	/* subtract offset, see above */
+
+	addr32 movl %eax, (%ebx)
+
+
+	/* The next section of code is hardware specific */
+
+	/* Clear SMI status */
+	movw $(DEFAULT_PMBASE + 0x34), %dx
+	inw %dx, %ax
+	outw %ax, %dx
+
+	/* Clear PM1 status */
+	movw $(DEFAULT_PMBASE + 0x00), %dx
+	inw %dx, %ax
+	outw %ax, %dx
+
+	/* Set EOS bit so other SMIs can occur */
+	movw $(DEFAULT_PMBASE + 0x30), %dx
+	inl %dx, %eax
+	orl $(1 << 1), %eax
+	outl %eax, %dx
+
+	/* End of hardware specific section. */
+#ifdef DEBUG_SMM_RELOCATION
+	/* print [SMM-x] so we can determine if CPUx went to SMM */
+	movw $TTYS0_BASE, %dx
+	mov $'[', %al
+	outb %al, %dx
+	mov $'S', %al
+	outb %al, %dx
+	mov $'M', %al
+	outb %al, %dx
+	outb %al, %dx
+	movb $'-', %al
+	outb %al, %dx
+	/* calculate ascii of cpu number. More than 9 cores? -> FIXME */
+	movb %cl, %al
+	addb $'0', %al 
+	outb %al, %dx
+	mov $']', %al
+	outb %al, %dx
+	mov $'\r', %al
+	outb %al, %dx
+	mov $'\n', %al
+	outb %al, %dx
+#endif
+
+	/* That's it. return */
+	rsm
+smm_relocation_end:
+
Index: src/cpu/intel/model_f2x/Config.lb
===================================================================
--- src/cpu/intel/model_f2x/Config.lb	(revision 3845)
+++ src/cpu/intel/model_f2x/Config.lb	(working copy)
@@ -7,6 +7,7 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 dir /cpu/intel/hyperthreading
 driver model_f2x_init.o
Index: src/cpu/intel/model_f3x/Config.lb
===================================================================
--- src/cpu/intel/model_f3x/Config.lb	(revision 3845)
+++ src/cpu/intel/model_f3x/Config.lb	(working copy)
@@ -7,6 +7,7 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 dir /cpu/intel/hyperthreading
 driver model_f3x_init.o
Index: src/cpu/intel/ep80579/Config.lb
===================================================================
--- src/cpu/intel/ep80579/Config.lb	(revision 3845)
+++ src/cpu/intel/ep80579/Config.lb	(working copy)
@@ -26,5 +26,6 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 driver ep80579_init.o
Index: src/cpu/intel/model_6dx/Config.lb
===================================================================
--- src/cpu/intel/model_6dx/Config.lb	(revision 3845)
+++ src/cpu/intel/model_6dx/Config.lb	(working copy)
@@ -5,5 +5,6 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 driver model_6dx_init.o
Index: src/cpu/intel/model_f4x/Config.lb
===================================================================
--- src/cpu/intel/model_f4x/Config.lb	(revision 3845)
+++ src/cpu/intel/model_f4x/Config.lb	(working copy)
@@ -7,6 +7,7 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 dir /cpu/intel/hyperthreading
 driver model_f4x_init.o
Index: src/cpu/intel/model_6ex/Config.lb
===================================================================
--- src/cpu/intel/model_6ex/Config.lb	(revision 3845)
+++ src/cpu/intel/model_6ex/Config.lb	(working copy)
@@ -8,6 +8,7 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 dir /cpu/intel/hyperthreading
 driver model_6ex_init.o
Index: src/cpu/intel/model_6fx/Config.lb
===================================================================
--- src/cpu/intel/model_6fx/Config.lb	(revision 3845)
+++ src/cpu/intel/model_6fx/Config.lb	(working copy)
@@ -8,6 +8,7 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 dir /cpu/intel/hyperthreading
 driver model_6fx_init.o
Index: src/cpu/intel/model_6xx/Config.lb
===================================================================
--- src/cpu/intel/model_6xx/Config.lb	(revision 3845)
+++ src/cpu/intel/model_6xx/Config.lb	(working copy)
@@ -5,5 +5,6 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 driver model_6xx_init.o
Index: src/cpu/intel/model_69x/Config.lb
===================================================================
--- src/cpu/intel/model_69x/Config.lb	(revision 3845)
+++ src/cpu/intel/model_69x/Config.lb	(working copy)
@@ -5,5 +5,6 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 driver model_69x_init.o
Index: src/cpu/intel/model_f0x/Config.lb
===================================================================
--- src/cpu/intel/model_f0x/Config.lb	(revision 3845)
+++ src/cpu/intel/model_f0x/Config.lb	(working copy)
@@ -7,5 +7,6 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 driver model_f0x_init.o
Index: src/cpu/intel/model_f1x/Config.lb
===================================================================
--- src/cpu/intel/model_f1x/Config.lb	(revision 3845)
+++ src/cpu/intel/model_f1x/Config.lb	(working copy)
@@ -7,5 +7,6 @@
 dir /cpu/x86/sse
 dir /cpu/x86/lapic
 dir /cpu/x86/cache
+dir /cpu/x86/smm
 dir /cpu/intel/microcode
 driver model_f1x_init.o
Index: util/newconfig/config.g
===================================================================
--- util/newconfig/config.g	(revision 3845)
+++ util/newconfig/config.g	(working copy)
@@ -226,6 +226,9 @@
 		# driver files added by 'driver' directive
 		self.driverrules = {}
 
+		# smm object files added by 'smmobject' directive
+		self.smmobjectrules = {}
+
 		# loader scripts added by 'ldscript' directive
 		self.ldscripts = []
 
@@ -344,6 +347,9 @@
 	def adddriverrule(self, name):
 		self.addobjectdriver(self.driverrules, name)
 
+	def addsmmobjectrule(self, name):
+		self.addobjectdriver(self.smmobjectrules, name)
+
 	def getinitobjectrules(self):
 		return self.initobjectrules
 
@@ -371,6 +377,15 @@
 			return o
 		fatal("No such driver rule \"%s\"" % name)
 
+	def getsmmobjectrules(self):
+		return self.smmobjectrules
+
+	def getsmmobjectrule(self, name):
+		o = getdict(self.smmobjectrules, name)
+		if (o):
+			return o
+		fatal("No such smm object rule \"%s\"" % name)
+
 	def addldscript(self, path):
 		self.ldscripts.append(path)
 
@@ -1370,6 +1385,10 @@
 	global curimage
 	curimage.adddriverrule(driver_name)
 
+def addsmmobject(object_name):
+	global curimage
+	curimage.addsmmobjectrule(object_name)
+
 def target(name):
         global target_dir, target_name
 	print "Configuring TARGET %s" % name
@@ -1593,6 +1612,7 @@
     token PRINT:		'print'
     token REGISTER:		'register'
     token ROMIMAGE:		'romimage'
+    token SMMOBJECT:		'smmobject'
     token SOUTHBRIDGE:		'southbridge'
     token SUPERIO:		'superio'
     token TARGET:		'target'
@@ -1693,6 +1713,10 @@
 
     rule driver<<C>>:	DRIVER DIRPATH		{{ if (C): adddriver(DIRPATH)}}
 
+    rule smmobject<<C>>:
+    			SMMOBJECT DIRPATH	{{ if (C): addsmmobject(DIRPATH)}}
+
+
     rule dir<<C>>:	DIR DIRPATH 		{{ if (C): dodir(DIRPATH, 'Config.lb') }}
 
     rule default<<C>>:	DEFAULT ID EQ value	{{ if (C): setdefault(ID, value, 0) }}
@@ -1826,6 +1850,7 @@
 		| 	prtstmt<<C>>		{{ return prtstmt }}
 		|	register<<C>> 		{{ return register }}
 		|	device<<C>>		{{ return device }}
+		|	smmobject<<C>>		{{ return smmobject }}
 
     # ENTRY for parsing Config.lb file
     rule cfgfile:	(uses<<1>>)* 
@@ -2028,6 +2053,13 @@
 		file.write("OBJECTS += %s\n" % (obj_name))
 		file.write("SOURCES += %s\n" % (obj_source))
 
+	for srule, smm in image.getsmmobjectrules().items():
+		s_name = smm[0]
+		s_source = smm[1]
+		file.write("SMM-OBJECTS += %s\n" % (s_name))
+		file.write("SOURCES += %s\n" % (s_source))
+
+
 	# for chip_target.c
 	file.write("OBJECTS += static.o\n")
 	file.write("SOURCES += static.c\n")
@@ -2104,6 +2136,23 @@
 		file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
 		#file.write("%s\n" % objrule[2])
 
+	file.write("\n# smmobjectrules:\n")
+	for irule, smm in image.getsmmobjectrules().items():
+		source = topify(smm[1])
+		type = smm[2]
+		if (type  == 'S'):
+			# for .S, .o depends on .s
+			file.write("%s: %s.s\n" % (smm[0], smm[3]))
+        		file.write("\t$(CC) -c $(CPU_OPT) -o $@ $<\n")
+			# and .s depends on .S
+			file.write("%s.s: %s\n" % (smm[3], source))
+			# Note: next 2 lines are ONE output line!
+        		file.write("\t$(CPP) $(CPPFLAGS) $< ")
+			file.write(">$@.new && mv $@.new $@\n")
+		else:
+			file.write("%s: %s\n" % (smm[0], source))
+			file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")
+
 	# special rule for chip_target.c
 	file.write("static.o: static.c\n")
 	file.write("\t$(CC) -c $(CFLAGS) -o $@ $<\n")