Index: svn/mainboard/emulation/qemu-x86/dts
===================================================================
--- svn.orig/mainboard/emulation/qemu-x86/dts
+++ svn/mainboard/emulation/qemu-x86/dts
@@ -21,21 +21,25 @@
 /{
 	mainboard_vendor = "Emulation";
 	mainboard_name = "QEMU x86";
-	mainboard_pci_subsystem_vendor = "0x15ad";
-	mainboard_pci_subsystem_device = "0x1976";
+	subsystem_vendor = "0x15ad";
+	subsystem_device = "0x1976";
 	device_operations = "qemuvga_pci_ops_dev";
 	cpus {};
 	domain@0 {
 		/config/("northbridge/intel/i440bxemulation/domain");
-		bus@0 {
-			pci@0,0 {
-			};
-			pci@1,1 {
-				/config/("southbridge/intel/i82371eb/ide");
-				subsystem_vendor = "0x15ad";
-				subsystem_device = "0x1976";
-				on_mainboard;
-			};
+		pci@0,0 {
+			/config/("northbridge/intel/i440bxemulation/northbridge");
 		};
+		pci@1,0 {
+			/config/("southbridge/intel/i82371eb/isa");
+		};
+		pci@1,1 {
+			/config/("southbridge/intel/i82371eb/ide");
+		};
+		pci@1,3 {
+			/config/("southbridge/intel/i82371eb/acpi");
+		};
+		/* PCI 2.0 and 3.0 are plugged in. */
+		/* 2.0 is the Cirrus VGA card.  3.0 is a nic. */
 	};
 };
Index: svn/southbridge/intel/i82371eb/acpi
===================================================================
--- /dev/null
+++ svn/southbridge/intel/i82371eb/acpi
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "i82371eb_acpi";
+};
Index: svn/southbridge/intel/i82371eb/ide
===================================================================
--- svn.orig/southbridge/intel/i82371eb/ide
+++ svn/southbridge/intel/i82371eb/ide
@@ -19,7 +19,7 @@
  */
 
 {
-	ide0_enable = "0";
-	ide1_enable = "0";
+	ide0_enable = "1";
+	ide1_enable = "1";
 	device_operations = "i82371eb_ide";
 };
Index: svn/southbridge/intel/i82371eb/isa
===================================================================
--- /dev/null
+++ svn/southbridge/intel/i82371eb/isa
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "i82371eb_isa";
+};
Index: svn/northbridge/intel/i440bxemulation/i440bx.c
===================================================================
--- svn.orig/northbridge/intel/i440bxemulation/i440bx.c
+++ svn/northbridge/intel/i440bxemulation/i440bx.c
@@ -56,11 +56,22 @@ static int inb_cmos(int port)
 	return inb(0x71);
 }
 
-static void pci_domain_set_resources(struct device *dev)
+static void no_op(struct device *dev)
 {
-	struct device *mc_dev;
+}
+
+static void i440bx_read_resources(struct device *dev)
+{
+	struct resource *res;
 	u32 tolmk;		/* Top of low mem, Kbytes. */
 	int idx;
+
+	/* I/O resource. */
+	res = new_resource(dev, 0);
+	res->base = 0x1000UL;
+	res->limit = 0xFFFFUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
+
 	/* read large mem memory descriptor
 	   for <16 MB read the more detailed small mem descriptor
 	   all values in kbytes */
@@ -68,18 +79,58 @@ static void pci_domain_set_resources(str
 	if (tolmk <= 16 * 1024) {
 		tolmk = (inb_cmos(0x31)<<8) |inb_cmos(0x30);
 	}
-	printk(BIOS_WARNING, "Ignoring chipset specified RAM size. Using dts "
-		"settings of %d kB instead.\n", tolmk);
-	mc_dev = dev->link[0].children;
-	if (mc_dev) {
-		idx = 10;
-		/* 0 .. 640 kB */
-		ram_resource(dev, idx++, 0, 640);
-		/* Hole for VGA (0xA0000-0xAFFFF) graphics and text mode
-		 * graphics (0xB8000-0xBFFFF) */
-		/* 768 kB .. Systop (in KB) */
-		ram_resource(dev, idx++, 768, tolmk - 768);
-	}
+
+	printk(BIOS_WARNING, "Using CMOS settings of %d kB RAM.\n", tolmk);
+	idx = 10;
+
+	/* 0 .. 640 kB */
+	ram_resource(dev, idx++, 0, 640);
+
+	/* Hole for VGA (0xA0000-0xAFFFF) graphics and text mode
+	 * graphics (0xB8000-0xBFFFF) */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0xA0000UL;
+	res->size = 0x20000UL;
+	res->limit = 0xBFFFUL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	/* 768 kB .. Systop (in KB) */
+	ram_resource(dev, idx++, 768, tolmk - 768);
+}
+
+static void i440bx_domain_read_resources(struct device *dev)
+{
+	struct resource *res;
+
+	/* Initialize the domain's I/O space constraints. */
+	res = new_resource(dev, 0);
+	res->base = 0x1000UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
+
+	/* Initialize the system-wide memory resources constraints. */
+	res = new_resource(dev, 1);
+	res->limit = 0xffffffffULL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
+
+	/* Reserve space for the APIC. */
+	res = new_resource(dev, 2);
+	res->base = 0xfec00000UL;
+	res->size = 0x100000UL;
+	res->limit = 0xffffffffULL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED;
+
+	/* Reserve space for the APIC. */
+	res = new_resource(dev, 2);
+	res->base = 0xfee00000UL;
+	res->size = 0x10000UL;
+	res->limit = 0xffffffffULL;
+	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED;
+}
+
+static void i440bx_domain_set_resources(struct device *dev)
+{
 	phase4_set_resources(&dev->link[0]);
 }
 
@@ -90,10 +141,24 @@ struct device_operations i440bx_domain =
 		{.pci_domain = {.vendor = 0x8086,.device = 0x7190}}},
 	.constructor		 = default_device_constructor,
 	.phase3_scan		 = pci_domain_scan_bus,
-	.phase4_read_resources	 = pci_domain_read_resources,
-	.phase4_set_resources	 = pci_domain_set_resources,
+	.phase4_read_resources	 = i440bx_domain_read_resources,
+	.phase4_set_resources	 = i440bx_domain_set_resources,
 	.phase5_enable_resources = enable_childrens_resources,
-	.phase6_init		 = 0,
+	.phase6_init		 = no_op,
+	.ops_pci_bus		 = &pci_cf8_conf1,
+
+};
+
+/* Here are the operations for the northbridge. */
+struct device_operations i440bx_northbridge = {
+	.id = {.type = DEVICE_ID_PCI,
+		{.pci = {.vendor = 0x8086,.device = 0x1237}}},
+	.constructor		 = default_device_constructor,
+	.phase3_scan		 = NULL,
+	.phase4_read_resources	 = i440bx_read_resources,
+	.phase4_set_resources	 = pci_set_resources,
+	.phase5_enable_resources = no_op,
+	.phase6_init		 = no_op,
 	.ops_pci_bus		 = &pci_cf8_conf1,
 
 };
Index: svn/northbridge/intel/i440bxemulation/northbridge
===================================================================
--- /dev/null
+++ svn/northbridge/intel/i440bxemulation/northbridge
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+{
+	device_operations = "i440bx_northbridge";
+};
Index: svn/northbridge/intel/i440bxemulation/i440bx.h
===================================================================
--- svn.orig/northbridge/intel/i440bxemulation/i440bx.h
+++ svn/northbridge/intel/i440bxemulation/i440bx.h
@@ -92,6 +92,4 @@
 #define PAM5    0x5e
 #define PAM6    0x5f
 
-unsigned int i440bx_scan_root_bus(struct device *root, unsigned int max);
-
 #endif /* NORTHBRIDGE_INTEL_I440BXEMULATION_I440BX_H */
