[coreboot] Re: How to add NUVOTON NCT6776F support with serial port logic enabled ???

[Shreesh Chhabbi]

Hi,

Is the serial port where you are trying to capture logs, coming out of Nuvoton controller or the Atom Processor? 
If serial port is coming out of Nuvoton:
Usually the controller connected on LPC to the main processor is accessed via IO ports. Controller needs to have code change to support this. If you have Intel CRB's reference code for main processor and controller, you could look for supported commands to EC. I have encountered post code print on the seven segment displays via EC from main processor. But serial console is always directly from main processor.
If serial port is coming out of main processor:
The UART controller is seen as a PCI device to the CPU. You need to enumerate this and initialize and use it for dumping bytes onto serial console (available in Intel CRB reference code usually).

Thanks,
Shreesh Chhabbi
Sr. Software Engineer
Ircona (www.ircona.com)

-----Original Message-----
From: [e-mail]  
Sent: Friday 17 May 2019 16:02
To: [e-mail]
Subject: [coreboot] How to add NUVOTON NCT6776F support with serial port logic enabled ???

There is a Lanner FW-7573 platform based on the Intel Rangeley Atom C2000 series processor.
To work with the Serial port in this platform, the NUVOTON NCT6776F chip is connected via the LPC bus to the processor.
I just can’t get Serial port working for debuging. I take as a basis intel littleplains board.  I tried to add NCT6776F support following the example of other boards - without success. There is no output to the console, and in Linux, the superiotool program does not see the NCT6776F.

On the official version of the BIOS I loaded linux OS and took a dump.  (superiotool r => Found Nuvoton NCT6776F/D (C) (id=0xc333) at 0x4e) )

How to add NUVOTON NCT6776F support with serial port logic enabled ???

in devicetree.cb I add:

device pci 1f.0 on # LPC bridge
    			chip superio/nuvoton/nct6776
    				device pnp 4e.0 off end		# Floppy
    				device pnp 4e.1 off end		# Parallel port
    				device pnp 4e.2 on		# COM1
    					io 0x60 = 0x3f8
    					irq 0x70 = 4
    				end
    				device pnp 4e.3 off end		# COM2, IR
    				device pnp 4e.5 off end		# Keyboard
    				device pnp 4e.6 off end		# CIR
    				device pnp 4e.7 off end		# GPIO6
    				device pnp 4e.107 off end	# GPIO7
    				device pnp 4e.207 off end	# GPIO8
    				device pnp 4e.307 off end	# GPIO9
    				device pnp 4e.8 off end		# WDT
    				device pnp 4e.108 off end	# GPIO0
    				device pnp 4e.208 off end	# GPIOA
    				device pnp 4e.308 off end	# GPIOBASE
    				device pnp 4e.109 off end	# GPIO1
    				device pnp 4e.209 off end	# GPIO2
    				device pnp 4e.309 off end	# GPIO3
    				device pnp 4e.409 off end	# GPIO4
    				device pnp 4e.509 off end	# GPIO5
    				device pnp 4e.609 off end	# GPIO6
    				device pnp 4e.709 off end	# GPIO7
    				device pnp 4e.a on end		# ACPI
    				device pnp 4e.b off end		# HWM, front pannel LED
    				device pnp 4e.d off end		# VID
    				device pnp 4e.e off end		# CIR WAKE-UP
    				device pnp 4e.f off end		# GPIO
    				device pnp 4e.14 off end	# SVID
    				device pnp 4e.16 off end	# Deep sleep
    				device pnp 4e.17 off end	# GPIOA
    			end
    		end # LPC bridge

In superio.asl i add:

#undef SUPERIO_DEV		
#undef SUPERIO_PNP_BASE

#define SUPERIO_DEV		        SIO0
#define SUPERIO_PNP_BASE	0x4e
#define NCT6776_SHOW_PP
#define NCT6776_SHOW_SP1
#define NCT6776_SHOW_KBC
#define NCT6776_SHOW_HWM
#define NCT6776_SHOW_GPIO

#include <superio/nuvoton/nct6776/acpi/superio.asl>

in romstage.c add function mainboard_config_superio:

void mainboard_config_superio(void)
{
    /* Enable UART */
    nuvoton_pnp_enter_conf_state(GLOBAL_DEV);

/* Select SIO pin states. */  As in Dump........
    pnp_write_config(GLOBAL_DEV, 0x13, 0xff);
    pnp_write_config(GLOBAL_DEV, 0x14, 0xff);
    pnp_write_config(GLOBAL_DEV, 0x1b, 0x53);
    pnp_write_config(GLOBAL_DEV, 0x1c, 0x80);
        pnp_write_config(GLOBAL_DEV, 0x24, 0x24);
    pnp_write_config(GLOBAL_DEV, 0x27, 0xc0);
    pnp_write_config(GLOBAL_DEV, 0x2b, 0x03);
    pnp_write_config(GLOBAL_DEV, 0x2a, 0x00);
    pnp_write_config(GLOBAL_DEV, 0x2c, 0x80);

/* Power RAM in S3. */
    //pnp_set_logical_device(ACPI_DEV);
    //pnp_write_config(ACPI_DEV, 0xe4, 0x10);

pnp_set_logical_device(SERIAL_DEV);

nuvoton_pnp_exit_conf_state(GLOBAL_DEV);

nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } _______________________________________________
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