On 10/26/06, Tom Sylla <firstname.lastname@example.org
Please refer to Chapter 10 "Memory Cache Control" in the Intel manual
you mentioned. Find the Table called "Cache Operating Modes" (Table
10-5 in current version). The way it works is described well in that
table. For CD=1, "Read hits access the cache; read misses do not cause
replacement." and "Write hits update the cache". So that means
anything that is a "hit" acts just like RAM. Nothing too fancy. You
just have to make sure that the area you want to "hit" gets pre-loaded
before you turn the cache back off again.
this is the 'can you read carefully' test that I flunked. It is obvious once you read it, except I missed it for
5 years :-) Once Eswar pointed it out it was obvious.