Edit devicetree.cb and set: register "max_mem_clock_mhz" = "666"
I suppose there is one. I don't know. I want to investigate. I will certainly try again by adding the patches suggested by Kyosti. As soon as I can get the MRC blob to work, I can make some better guesses about what is going wrong (I tried so many various things already) by having some reference points.
At the moment, I want to make a first public commit for the W520, but with the RAM issues (only stable with the MCU at 666), and no native video init, and the power consumption issues, I'm not sure how helpful it will be.
Yeah, the blob. I don't like blob, but I like to have the option of something that works if I need to investigate why something else is not working. Or just for an initial release.
This change was committed on Apr. 5th, 2012 into the main coreboot git repository. In fact, if you going to look into directory:
…/src/northbridge/intel/
Please, find the line 213: void sdram_initialize(struct
And then, the line 245: entry = (unsigned long)cbfs_
_______
Yup, this was the MRC blob and the commit you are referring to, back then in April 5th, 2012. This was the MRC SNB BIOS blob developed (my best guess) by some BIOS CCG group for Coreboot/Google. And I also guess, this one was reverse engineered by two of Google people (Vladimir Serbinenko somehow comes to my mind). ;-)
Kyosti, my best guess is that you can find this patch/original SNB MRC blob API code, and blob itself, can you (since Charlotte++ would like to experiment with it)?
Thank you all for refreshing my old, patchy, full of black holes brain, giving me the hope that I can (much) better organize huge DATA info scattered all over my mind! :-)
Zoran