Index: src/include/cpu/amd/gx2def.h
===================================================================
--- src/include/cpu/amd/gx2def.h	(revision 6218)
+++ src/include/cpu/amd/gx2def.h	(working copy)
@@ -77,7 +77,6 @@
 #define	GL1_GLCP	3
 #define	GL1_PCI		4
 #define	GL1_FG		5
-#define GL1_VIP		5
 #define GL1_AES		6
 
 #define	MSR_GLIU0	(GL0_GLIU0	<< 29) + (1 << 28)	/* 1000xxxx - To get on GeodeLink one bit has to be set */
@@ -91,7 +90,6 @@
 #define	MSR_GLCP	(GL1_GLCP << 26) + MSR_GLIU1		/* 4C00xxxx */
 #define	MSR_PCI		(GL1_PCI << 26) + MSR_GLIU1		/* 5000xxxx */
 #define	MSR_FG		(GL1_FG << 26) + MSR_GLIU1		/* 5400xxxx */
-#define MSR_VIP		((GL1_VIP << 26) + MSR_GLIU1)		/* 5400xxxx */
 #define MSR_AES		((GL1_AES << 26) + MSR_GLIU1)		/* 5800xxxx */
 
 /* South Bridge */
@@ -386,14 +384,10 @@
 
 /* FooGlue GLIU1 port 5 */
 #define	FG_GLD_MSR_CAP		(MSR_FG + 0x2000)
+#define	FG_GLD_MSR_CONFIG	(MSR_FG + 0x2001)
 #define	FG_GLD_MSR_PM		(MSR_FG + 0x2004)
 #define	FG_GIO_MSR_SEL		(MSR_FG + 0x2010)
-
-/* VIP GLIU1 port 5 */
-#define VIP_GLD_MSR_CAP		(MSR_VIP + 0x2000)
-#define VIP_GLD_MSR_CONFIG	(MSR_VIP + 0x2001)
-#define VIP_GLD_MSR_PM		(MSR_VIP + 0x2004)
-#define VIP_BIST		(MSR_VIP + 0x2005)
+#define	FG_BIST			(MSR_FG + 0x2005)
 
 /* AES GLIU1 port 6 */
 #define AES_GLD_MSR_CAP		(MSR_AES + 0x2000)
@@ -429,22 +423,75 @@
 
 #define MSR_GL0	(GL1_GLIU0 << 29)
 
-/* Set up desc addresses from 20 - 3f */
+/* Set up desc addresses from 20 - E8 */
 /* This is chip specific! */
+//remove after MSRINIT is gone
 #define MSR_GLIU0_BASE1		(MSR_GLIU0 + 0x20)	/* BM */
 #define MSR_GLIU0_BASE2		(MSR_GLIU0 + 0x21)	/* BM */
 #define MSR_GLIU0_SHADOW	(MSR_GLIU0 + 0x2C)	/* SCO should only be SC */
 #define MSR_GLIU0_SYSMEM	(MSR_GLIU0 + 0x28)	/* RO should only be R */
-#define MSR_GLIU0_SMM		(MSR_GLIU0 + 0x26)	/* BMO */
-#define MSR_GLIU0_DMM		(MSR_GLIU0 + 0x27)	/* BMO */
 
 #define MSR_GLIU1_BASE1		(MSR_GLIU1 + 0x20)	/* BM */
 #define MSR_GLIU1_BASE2		(MSR_GLIU1 + 0x21)	/* BM */
 #define MSR_GLIU1_SHADOW	(MSR_GLIU1 + 0x2D)	/* SCO should only be SC */
 #define MSR_GLIU1_SYSMEM	(MSR_GLIU1 + 0x29)	/* RO should only be R */
-#define MSR_GLIU1_SMM		(MSR_GLIU1 + 0x23)	/* BM */
-#define MSR_GLIU1_DMM		(MSR_GLIU1 + 0x24)	/* BM */
-#define MSR_GLIU1_FPU_TRAP	(MSR_GLIU1 + 0x0E3)	/* FooGlue F0 for FPU */
+
+#define GLIU0_P2D_BM_0		(MSR_GLIU0 + 0x20)	/* BASE1 */
+#define GLIU0_P2D_BM_1		(MSR_GLIU0 + 0x21)	/* BASE2 */
+#define GLIU0_P2D_BM_2		(MSR_GLIU0 + 0x22)
+#define GLIU0_P2D_BM_3		(MSR_GLIU0 + 0x23)
+#define GLIU0_P2D_BM_4		(MSR_GLIU0 + 0x24)
+#define GLIU0_P2D_BM_5		(MSR_GLIU0 + 0x25)
+
+#define GLIU0_P2D_BMO_0		(MSR_GLIU0 + 0x26)	/* SMM */
+#define GLIU0_P2D_BMO_1		(MSR_GLIU0 + 0x27)	/* DMM */
+
+#define GLIU0_P2D_R_0		(MSR_GLIU0 + 0x28)	/* SYSMEM */
+
+#define GLIU0_P2D_RO_0		(MSR_GLIU0 + 0x29)
+#define GLIU0_P2D_RO_1		(MSR_GLIU0 + 0x2A)
+#define GLIU0_P2D_RO_2		(MSR_GLIU0 + 0x2B)
+
+#define GLIU0_P2D_SC_0		(MSR_GLIU0 + 0x2C)	/* SHADOW */
+
+#define GLIU0_IOD_BM_0		(MSR_GLIU0 + 0xE0)
+#define GLIU0_IOD_BM_1		(MSR_GLIU0 + 0xE1)
+#define GLIU0_IOD_BM_2		(MSR_GLIU0 + 0xE2)
+
+#define GLIU0_IOD_SC_0		(MSR_GLIU0 + 0xE3)
+#define GLIU0_IOD_SC_1		(MSR_GLIU0 + 0xE4)
+#define GLIU0_IOD_SC_2		(MSR_GLIU0 + 0xE5)
+#define GLIU0_IOD_SC_3		(MSR_GLIU0 + 0xE6)
+#define GLIU0_IOD_SC_4		(MSR_GLIU0 + 0xE7)
+#define GLIU0_IOD_SC_5		(MSR_GLIU0 + 0xE8)
+
+#define GLIU1_P2D_BM_0		(MSR_GLIU1 + 0x20)	/* BASE1 */
+#define GLIU1_P2D_BM_1		(MSR_GLIU1 + 0x21)	/* BASE2 */
+#define GLIU1_P2D_BM_2		(MSR_GLIU1 + 0x22)
+#define GLIU1_P2D_BM_3		(MSR_GLIU1 + 0x23)	/* SMM */
+#define GLIU1_P2D_BM_4		(MSR_GLIU1 + 0x24)	/* DMM */
+#define GLIU1_P2D_BM_5		(MSR_GLIU1 + 0x25)
+#define GLIU1_P2D_BM_6		(MSR_GLIU1 + 0x26)
+#define GLIU1_P2D_BM_7		(MSR_GLIU1 + 0x27)
+#define GLIU1_P2D_BM_8		(MSR_GLIU1 + 0x28)
+
+#define GLIU1_P2D_R_0		(MSR_GLIU1 + 0x29)	/* SYSMEM */
+#define GLIU1_P2D_R_1		(MSR_GLIU1 + 0x2A)
+#define GLIU1_P2D_R_2		(MSR_GLIU1 + 0x2B)
+#define GLIU1_P2D_R_3		(MSR_GLIU1 + 0x2C)
+
+#define GLIU1_P2D_SC_0		(MSR_GLIU1 + 0x2D)	/* SHADOW */
+
+#define GLIU1_IOD_BM_0		(MSR_GLIU1 + 0xE0)
+#define GLIU1_IOD_BM_1		(MSR_GLIU1 + 0xE1)
+#define GLIU1_IOD_BM_2		(MSR_GLIU1 + 0xE2)
+
+#define GLIU1_IOD_SC_0		(MSR_GLIU1 + 0xE3)	/* FooGlue F0 for FPU */
+#define GLIU1_IOD_SC_1		(MSR_GLIU1 + 0xE4)
+#define GLIU1_IOD_SC_2		(MSR_GLIU1 + 0xE5)
+#define GLIU1_IOD_SC_3		(MSR_GLIU1 + 0xE6)
+#define GLIU1_IOD_SC_4		(MSR_GLIU1 + 0xE7)
+#define GLIU1_IOD_SC_5		(MSR_GLIU1 + 0xE8)
 
 /* definitions that are "once you are mostly up, start VSA" type things */
 #define SMM_OFFSET		0x40400000
Index: src/northbridge/amd/gx2/northbridgeinit.c
===================================================================
--- src/northbridge/amd/gx2/northbridgeinit.c	(revision 6218)
+++ src/northbridge/amd/gx2/northbridgeinit.c	(working copy)
@@ -23,25 +23,25 @@
 };
 
 struct gliutable gliu0table[] = {
-	{.desc_name=MSR_GLIU0_BASE1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=  0x0FFF80},			/* 0-7FFFF to MC */
-	{.desc_name=MSR_GLIU0_BASE2,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},	/* 80000-9ffff to Mc */
-	{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=  0x03},		/* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
-	{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=MSR_GLIU0_DMM,    .desc_type= BMO_DMM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=MSR_GLIU0_SMM,    .desc_type= BMO_SMM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU0_P2D_BM_0,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=  0x0FFF80},			/* 0-7FFFF to MC */
+	{.desc_name=GLIU0_P2D_BM_1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},	/* 80000-9ffff to Mc */
+	{.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=  0x03},		/* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
+	{.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU0_P2D_BMO_1,    .desc_type= BMO_DMM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU0_P2D_BMO_0,    .desc_type= BMO_SMM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
 	{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
 	{.desc_name=GL_END,           .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };
 
 struct gliutable gliu1table[] = {
-	{.desc_name=MSR_GLIU1_BASE1,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},		/* 0-7FFFF to MC */
-	{.desc_name=MSR_GLIU1_BASE2,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},	/* 80000-9ffff to Mc */
-	{.desc_name=MSR_GLIU1_SHADOW,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03},		/* C0000-Fffff split to MC and PCI (sub decode) */
-	{.desc_name=MSR_GLIU1_SYSMEM,.desc_type=  R_SYSMEM,.hi=  MSR_GL0,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=MSR_GLIU1_DMM,.desc_type=  BM_DMM,.hi=  MSR_GL0,.lo=  0x0},				/* Catch and fix dynamicly. */
-	{.desc_name=MSR_GLIU1_SMM,.desc_type=  BM_SMM,.hi=  MSR_GL0,.lo=  0x0},				/* Catch and fix dynamicly. */
+	{.desc_name=GLIU1_P2D_BM_0,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},		/* 0-7FFFF to MC */
+	{.desc_name=GLIU1_P2D_BM_1,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},	/* 80000-9ffff to Mc */
+	{.desc_name=GLIU1_P2D_SC_0,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03},		/* C0000-Fffff split to MC and PCI (sub decode) */
+	{.desc_name=GLIU1_P2D_R_0,.desc_type=  R_SYSMEM,.hi=  MSR_GL0,.lo=  0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=GLIU1_P2D_BM_4,.desc_type=  BM_DMM,.hi=  MSR_GL0,.lo=  0x0},				/* Catch and fix dynamicly. */
+	{.desc_name=GLIU1_P2D_BM_3,.desc_type=  BM_SMM,.hi=  MSR_GL0,.lo=  0x0},				/* Catch and fix dynamicly. */
 	{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
-	{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type=  SCIO,.hi=  (GL1_GLCP << 29) + 0x0,.lo=  0x033000F0}, /* FooGlue FPU 0xF0 */
+	{.desc_name=GLIU1_IOD_SC_0,.desc_type=  SCIO,.hi=  (GL1_GLCP << 29) + 0x0,.lo=  0x033000F0}, /* FooGlue FPU 0xF0 */
 	{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };
 
@@ -98,7 +98,7 @@
 	{GP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0010}},		/* Graphics Priority. */
 	{GLPCI_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0027}},		/* GLPCI Priority + PID */
 	{GLCP_GLD_MSR_CONF,		{.hi=0x00,.lo=0x0001}},		/* GLCP Priority + PID */
-	{VIP_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0622}},		/* VIP PID */
+	{FG_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0622}},		/* FG PID */
 	{AES_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0013}},		/* AES PID */
 	{0x0FFFFFFFF, 			{0x0FFFFFFFF, 0x0FFFFFFFF}},	/* END */
 };
@@ -511,7 +511,7 @@
 static uint64_t getShadow(void)
 {
 	msr_t msr;
-	msr = rdmsr(MSR_GLIU0_SHADOW);
+	msr = rdmsr(GLIU0_P2D_SC_0);
 	return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
 }
 
