Hi,

I am bringing up a new board using coreboot as the bios.

 

Hardware:

-           Based on Intel Valley Island design (which has TPE)

-          No TPM

 

Coreboot:

-          Source coreboot 4.4 release

-          Using code based on Bayley bay (Intel FSP)

-          FSP: Gold3

-          Using a bios based on Valley Island for the non-coreboot sections

 

The board boots, goes through romstage and then freezes early in the ramstage (before enabling any devices): see output below

To me it seems there may be a hardware issue (new board, I am suspecting memory) but I thought I would ask as someone may have seen something similar.

 

1)      Could the non coreboot part of the bios chip cause this.

2)      Is there a way to check memory at the rom stage.

3)      Is there any information on the memory map of the bios chip.

4)      Is there a way to check other devices at the romstage or early ram stage.

 

I have tried skipping the “Enumeratin busses” section but it just crashes at the next stage (I guess I cannot really expect ti to get very far without its busses).

 

Note: I am new to coreboot and bios development in general.

Any help, suggestion appreciated.

 

Output Log:

--------------------------------------

coreboot-099d78c-dirty Thu May 12 05:41:22 UTC 2016 romstage starting...

RTC Init

POST: 0x44

POST: 0x47

POST: 0x48

Starting the Intel FSP (early_init)

PM1_STS = 0x100 PM1_CNT = 0x0 GEN_PMCON1 = 0x45008

prev_sleep_state = S5

Configure Default UPD Data

PcdMrcInitSPDAddr1:             0xa0 (default)

PcdMrcInitSPDAddr2:             0xa2 (default)

PcdSataMode:            0x01 (set)

PcdLpssSioEnablePciMode:                0x01 (default)

PcdMrcInitMmioSize:             0x800 (default)

PcdIgdDvmt50PreAlloc:           0x02 (default)

PcdApertureSize:                0x02 (default)

PcdGttSize:             0x02 (default)

SerialDebugPortAddress:         0x3f8 (default)

SerialDebugPortType:            0x01 (default)

PcdMrcDebugMsg:         0x00 (default)

PcdSccEnablePciMode:            0x01 (default)

IgdRenderStandby:               0x00 (default)

TxeUmaEnable:           0x00 (default)

PcdOsSelection:         0x04 (default)

PcdEMMC45DDR50Enabled:          0x01 (default)

PcdEMMC45HS200Enabled:          0x00 (default)

PcdEMMC45RetuneTimerValue:              0x08 (default)

PcdEnableIgd:           0x00 (default)

AutoSelfRefreshEnable:          0x00 (default)

APTaskTimeoutCnt:               0x00 (default)

GTT Size:               2 MB

Tseg Size:              8 MB

Aperture Size:          256 MB

IGD Memory Size:        64 MB

MMIO Size:              2048 MB

MIPI/ISP:               Disabled

Sdio:                   Enabled

Sdcard:                 Enabled

SATA:                   Enabled

SIO Dma 0:              Enabled

SIO I2C0:               Enabled

SIO I2C1:               Enabled

SIO I2C2:               Enabled

SIO I2C3:               Enabled

SIO I2C4:               Enabled

SIO I2C5:               Enabled

SIO I2C6:               Enabled

Azalia:                 Enabled

SIO Dma1:               Enabled

Pwm0:                   Enabled

Pwm1:                   Enabled

Hsuart0:                Enabled

Hsuart1:                Enabled

Spi:                    Enabled

Lpe:                    Disabled

eMMC Mode:              eMMC 4.5

SATA Mode:              AHCI

Xhci:                   Enabled

CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)

CBFS: Locating 'mrc.cache'

CBFS: Found @ offset fec0 size 10000

find_current_mrc_cache_local: No valid fast boot cache found.

FSP MRC cache not present.

POST: 0x92

POST: 0x4a

romstage_main_continue status: 0  hob_list_ptr: 7ae20000

FSP Status: 0x0

PM1_STS = 0x101 PM1_CNT = 0x0 GEN_PMCON1 = 0x1001808

romstage_main_continue: prev_sleep_state = S0

Baytrail Chip Variant: Bay Trail-I (ISG/embedded)

MRC v0.100

2 channels of DDR3 @ 1333MHz

POST: 0x4b

POST: 0x4c

POST: 0x4d

CBMEM:

IMD: root @ 7adff000 254 entries.

IMD: root @ 7adfec00 62 entries.

POST: 0x4e

POST: 0x4f

CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)

CBFS: Locating 'fallback/ramstage'

CBFS: Found @ offset 46380 size d5be

 

 

coreboot-099d78c-dirty Thu May 12 05:41:22 UTC 2016 ramstage starting...

POST: 0x39

Moving GDT to 7adfe9c0...ok

POST: 0x80

POST: 0x70

BS: BS_PRE_DEVICE times (us): entry 0 run 1168 exit 0

POST: 0x71

CBFS: 'Master Header Locator' located CBFS at [100:1fffc0)

CBFS: Locating 'cpu_microcode_blob.bin'

CBFS: Found @ offset 1ff00 size 26400

microcode: sig=0x30679 pf=0x1 revision=0x901

CPUID: 00030679

Cores: 4

Revision ID: 11

Stepping: D0

msr(17) = 0000000090041743

msr(ce) = 0000060000001700

BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 30606 exit 0

POST: 0x72

Enumerating buses...

Show all devs... Before device enumeration.

Root Dev

----------------------------