On Thu, Mar 4, 2010 at 8:26 AM, Joseph Smith <joe@settoplinux.org> wrote:

I would not worry about the microcode updates right now. CAR for Intel 6bx is coming real soon and the microcode updates will be included :-)

CAN'T WAIT! :D Then I can say goodbye to the messiness that is romcc, lol.

**********You are setting alot more than just dra here, I would rename this function something like sdram_setup_registers().

Good point. Eventually I wanted to name it sdram_initalize() just like i830, but there are a couple other references to the current names elsewhere. One step at a time I guess.

************I also noticed you did not use the memory initialize each row/side code from the i830. That code is extremely important for multiple memory sticks. Besides that everything else looks really good, great work!

There were some code that send RAM commands to the modules in the BX code. I just kept them around, thinking that this code in i830 may be specific to i830.

Mark, the problem you saw might be MBFS and MBSC not being set properly. I have reversed how the factory BIOS programmed them and have the code in my working copy. I'll see if that makes a difference. We are still hardcoded to CAS3 latency. One step at a time again I guess.

On another front, with the board running factory BIOS, I dumped the BX's config space (lspci -s 0:0:0.0 -xxx) with various DIMM configurations, especially with two sticks in DIMM0&1, DIMM2&3, and 3 sticks. These three scenarios are where most of the logics are. I can post them if anyone wants to look at them. All my RAMs are double sided, one 128MB and the others are 256MB.

To figure out how this gets coded for the 3-slot P2B, Someone would need to reverse the vendor bios for that board or do same as above.

Also, P3B-F has 4 DIMM slots as well.

Thanks
Keith