Kerry Sheh (shekairui@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562
-gerrit
commit 3203aa050b753dd1bf931fba462369cada510501 Author: Kerry Sheh shekairui@gmail.com Date: Tue Jan 31 20:42:20 2012 +0800
SIO: Add smsc/sch4037 superio support
Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 Signed-off-by: Kerry Sheh kerry.she@amd.com Signed-off-by: Kerry Sheh shekairui@gmail.com --- src/superio/smsc/Kconfig | 3 + src/superio/smsc/Makefile.inc | 2 + src/superio/smsc/sch4037/Makefile.inc | 20 +++ src/superio/smsc/sch4037/chip.h | 34 ++++ src/superio/smsc/sch4037/sch4037.h | 227 +++++++++++++++++++++++++ src/superio/smsc/sch4037/sch4037_early_init.c | 71 ++++++++ src/superio/smsc/sch4037/superio.c | 123 +++++++++++++ 7 files changed, 480 insertions(+), 0 deletions(-)
diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 7378d18..ddd5b96 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -39,3 +40,5 @@ config SUPERIO_SMSC_KBC1100 bool config SUPERIO_SMSC_SMSCSUPERIO bool +config SUPERIO_SMSC_SCH4037 + bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 68d4d56..bfdc68e 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2012 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -28,3 +29,4 @@ subdirs-y += lpc47n227 subdirs-y += sio10n268 subdirs-y += kbc1100 subdirs-y += smscsuperio +subdirs-y += sch4037 diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc new file mode 100644 index 0000000..8f36f2a --- /dev/null +++ b/src/superio/smsc/sch4037/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c diff --git a/src/superio/smsc/sch4037/chip.h b/src/superio/smsc/sch4037/chip.h new file mode 100644 index 0000000..3223750 --- /dev/null +++ b/src/superio/smsc/sch4037/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_CHIP_H +#define SUPERIO_SCH_4037_CHIP_H + +#include <pc80/keyboard.h> +#include <uart8250.h> + +struct chip_operations; +extern struct chip_operations superio_smsc_sch4037_ops; + +struct superio_smsc_sch4037_config { + + struct pc_keyboard keyboard; +}; + +#endif //SUPERIO_SCH_4037_CHIP_H \ No newline at end of file diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h new file mode 100644 index 0000000..f429723 --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037.h @@ -0,0 +1,227 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_4037_H +#define SUPERIO_SCH_4037_H + +/* BITS Define */ +#ifndef BIT0 +#define BIT0 0x0000000000000001ull +#endif +#ifndef BIT1 +#define BIT1 0x0000000000000002ull +#endif +#ifndef BIT2 +#define BIT2 0x0000000000000004ull +#endif +#ifndef BIT3 +#define BIT3 0x0000000000000008ull +#endif +#ifndef BIT4 +#define BIT4 0x0000000000000010ull +#endif +#ifndef BIT5 +#define BIT5 0x0000000000000020ull +#endif +#ifndef BIT6 +#define BIT6 0x0000000000000040ull +#endif +#ifndef BIT7 +#define BIT7 0x0000000000000080ull +#endif +#ifndef BIT8 +#define BIT8 0x0000000000000100ull +#endif +#ifndef BIT9 +#define BIT9 0x0000000000000200ull +#endif +#ifndef BIT10 +#define BIT10 0x0000000000000400ull +#endif +#ifndef BIT11 +#define BIT11 0x0000000000000800ull +#endif +#ifndef BIT12 +#define BIT12 0x0000000000001000ull +#endif +#ifndef BIT13 +#define BIT13 0x0000000000002000ull +#endif +#ifndef BIT14 +#define BIT14 0x0000000000004000ull +#endif +#ifndef BIT15 +#define BIT15 0x0000000000008000ull +#endif +#ifndef BIT16 +#define BIT16 0x0000000000010000ull +#endif +#ifndef BIT17 +#define BIT17 0x0000000000020000ull +#endif +#ifndef BIT18 +#define BIT18 0x0000000000040000ull +#endif +#ifndef BIT19 +#define BIT19 0x0000000000080000ull +#endif +#ifndef BIT20 +#define BIT20 0x0000000000100000ull +#endif +#ifndef BIT21 +#define BIT21 0x0000000000200000ull +#endif +#ifndef BIT22 +#define BIT22 0x0000000000400000ull +#endif +#ifndef BIT23 +#define BIT23 0x0000000000800000ull +#endif +#ifndef BIT24 +#define BIT24 0x0000000001000000ull +#endif +#ifndef BIT25 +#define BIT25 0x0000000002000000ull +#endif +#ifndef BIT26 +#define BIT26 0x0000000004000000ull +#endif +#ifndef BIT27 +#define BIT27 0x0000000008000000ull +#endif +#ifndef BIT28 +#define BIT28 0x0000000010000000ull +#endif +#ifndef BIT29 +#define BIT29 0x0000000020000000ull +#endif +#ifndef BIT30 +#define BIT30 0x0000000040000000ull +#endif +#ifndef BIT31 +#define BIT31 0x0000000080000000ull +#endif +#ifndef BIT32 +#define BIT32 0x0000000100000000ull +#endif +#ifndef BIT33 +#define BIT33 0x0000000200000000ull +#endif +#ifndef BIT34 +#define BIT34 0x0000000400000000ull +#endif +#ifndef BIT35 +#define BIT35 0x0000000800000000ull +#endif +#ifndef BIT36 +#define BIT36 0x0000001000000000ull +#endif +#ifndef BIT37 +#define BIT37 0x0000002000000000ull +#endif +#ifndef BIT38 +#define BIT38 0x0000004000000000ull +#endif +#ifndef BIT39 +#define BIT39 0x0000008000000000ull +#endif +#ifndef BIT40 +#define BIT40 0x0000010000000000ull +#endif +#ifndef BIT41 +#define BIT41 0x0000020000000000ull +#endif +#ifndef BIT42 +#define BIT42 0x0000040000000000ull +#endif +#ifndef BIT43 +#define BIT43 0x0000080000000000ull +#endif +#ifndef BIT44 +#define BIT44 0x0000100000000000ull +#endif +#ifndef BIT45 +#define BIT45 0x0000200000000000ull +#endif +#ifndef BIT46 +#define BIT46 0x0000400000000000ull +#endif +#ifndef BIT47 +#define BIT47 0x0000800000000000ull +#endif +#ifndef BIT48 +#define BIT48 0x0001000000000000ull +#endif +#ifndef BIT49 +#define BIT49 0x0002000000000000ull +#endif +#ifndef BIT50 +#define BIT50 0x0004000000000000ull +#endif +#ifndef BIT51 +#define BIT51 0x0008000000000000ull +#endif +#ifndef BIT52 +#define BIT52 0x0010000000000000ull +#endif +#ifndef BIT53 +#define BIT53 0x0020000000000000ull +#endif +#ifndef BIT54 +#define BIT54 0x0040000000000000ull +#endif +#ifndef BIT55 +#define BIT55 0x0080000000000000ull +#endif +#ifndef BIT56 +#define BIT56 0x0100000000000000ull +#endif +#ifndef BIT57 +#define BIT57 0x0200000000000000ull +#endif +#ifndef BIT58 +#define BIT58 0x0400000000000000ull +#endif +#ifndef BIT59 +#define BIT59 0x0800000000000000ull +#endif +#ifndef BIT60 +#define BIT60 0x1000000000000000ull +#endif +#ifndef BIT61 +#define BIT61 0x2000000000000000ull +#endif +#ifndef BIT62 +#define BIT62 0x4000000000000000ull +#endif +#ifndef BIT63 +#define BIT63 0x8000000000000000ull +#endif + +#define SCH4037_FDD 0 /* FDD */ +#define SCH4037_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH4037_RTC 6 /* RTC */ +#define SCH4037_KBC 7 /* KBC */ +#define SCH4037_HWM 8 /* HWM */ +#define SCH4037_RUNTIME 0x0A /* Runtime */ +#define SCH4037_XBUS 0x0B /* X-BUS */ + +#endif //SUPERIO_SCH_4037_H diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c new file mode 100644 index 0000000..1ff7aba --- /dev/null +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/romcc_io.h> +#include "sch4037.h" + +static inline void pnp_enter_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + unsigned port = dev>>8; + outb(0xaa, port); +} + +static inline void sch4037_early_init(unsigned port) +{ + device_t dev; + + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /*Auto power management*/ + pnp_write_config (dev, 0x22, BIT3+BIT4+BIT5 ); + pnp_write_config (dev, 0x23, 0 ); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV (port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enabled High speed, disabled MIDI support. */ + pnp_write_config (dev, 0xF0, 0x02); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV (port, SCH4037_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); + +} + diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c new file mode 100644 index 0000000..af4040f --- /dev/null +++ b/src/superio/smsc/sch4037/superio.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC KBC1100 Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <device/smbus.h> +#include <string.h> +#include <bitops.h> +#include <uart8250.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include "chip.h" +#include "sch4037.h" + +/* Forward declarations */ +static void enable_dev(device_t dev); +static void sch4037_pnp_set_resources(device_t dev); +static void sch4037_pnp_enable_resources(device_t dev); +static void sch4037_pnp_enable(device_t dev); +static void sch4037_init(device_t dev); + +static void pnp_enter_conf_state(device_t dev); +static void pnp_exit_conf_state(device_t dev); + +struct chip_operations superio_smsc_sch4037_ops = { + CHIP_NAME("SMSC SCH4037 Super I/O") + .enable_dev = enable_dev, +}; + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = sch4037_pnp_set_resources, + .enable_resources = sch4037_pnp_enable_resources, + .enable = sch4037_pnp_enable, + .init = sch4037_init, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(device_t dev) +{ + printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +static void sch4037_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void sch4037_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + + if(dev->enabled) { + pnp_set_enable(dev, 1); + } + else { + pnp_set_enable(dev, 0); + } + pnp_exit_conf_state(dev); +} + +static void sch4037_init(device_t dev) +{ + struct superio_smsc_sch4037_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + + case SCH4037_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x55, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +}