Index: src/southbridge/nvidia/ck804/ck804_early_smbus.c =================================================================== --- src/southbridge/nvidia/ck804/ck804_early_smbus.c (revision 5993) +++ src/southbridge/nvidia/ck804/ck804_early_smbus.c (working copy) @@ -18,36 +18,63 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include +#include +#include +#include +#include +#include + #include "ck804_smbus.h" +#include "ck804_early_smbus.h" +#define SMBUS_BAR_BASE 0x20 #define SMBUS_IO_BASE 0x1000 +#define SMBUS_IO_SIZE 0x0040 -static void enable_smbus(void) +#define SMBUS_BAR(x) (SMBUS_BAR_BASE + 4 * (x)) +#define SMBUS_BASE(x) (SMBUS_IO_BASE + SMBUS_IO_SIZE * (x)) + +void enable_smbus(void) { device_t dev; - dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0); + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_NVIDIA, + PCI_DEVICE_ID_NVIDIA_CK804_SMB), 0); if (dev == PCI_DEV_INVALID) die("SMBus controller not found\n"); - print_debug("SMBus controller enabled\n"); - /* Set SMBus I/O base. */ - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); + pci_write_config32(dev, SMBUS_BAR(0), SMBUS_BASE(0) | 1); + pci_write_config32(dev, SMBUS_BAR(1), SMBUS_BASE(1) | 1); /* Set SMBus I/O space enable. */ pci_write_config16(dev, 0x4, 0x01); /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + outb(inb(SMBUS_BASE(0) + SMBHSTSTAT), SMBUS_BASE(0) + SMBHSTSTAT); + outb(inb(SMBUS_BASE(1) + SMBHSTSTAT), SMBUS_BASE(1) + SMBHSTSTAT); + + print_debug("SMBus controller enabled\n"); } -static int smbus_read_byte(unsigned device, unsigned address) +int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address) { - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); + return do_smbus_read_byte(SMBUS_BASE(bus), device, address); } -static inline int smbus_write_byte(unsigned device, unsigned address, +int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address, unsigned char val) { - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); + return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val); } + +int smbus_read_byte(unsigned device, unsigned address) +{ + return ck804_smbus_read_byte(0, device, address); +} + +int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +{ + return ck804_smbus_write_byte(0, device, address, val); +} Index: src/southbridge/nvidia/ck804/ck804_early_smbus.h =================================================================== --- src/southbridge/nvidia/ck804/ck804_early_smbus.h (revision 0) +++ src/southbridge/nvidia/ck804/ck804_early_smbus.h (revision 0) @@ -0,0 +1,5 @@ +int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned); +int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char); +void enable_smbus(void); +int smbus_read_byte(unsigned int, unsigned int); +int smbus_write_byte(unsigned int, unsigned int, unsigned char); Index: src/southbridge/nvidia/ck804/Makefile.inc =================================================================== --- src/southbridge/nvidia/ck804/Makefile.inc (revision 5993) +++ src/southbridge/nvidia/ck804/Makefile.inc (working copy) @@ -16,6 +16,7 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c romstage-y += ck804_enable_usbdebug.c +romstage-y += ck804_early_smbus.c chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds Index: src/mainboard/tyan/s2891/romstage.c =================================================================== --- src/mainboard/tyan/s2891/romstage.c (revision 5993) +++ src/mainboard/tyan/s2891/romstage.c (working copy) @@ -19,7 +19,7 @@ #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.c" +#include "southbridge/nvidia/ck804/ck804_early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Index: src/mainboard/tyan/s2892/romstage.c =================================================================== --- src/mainboard/tyan/s2892/romstage.c (revision 5993) +++ src/mainboard/tyan/s2892/romstage.c (working copy) @@ -19,7 +19,7 @@ #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.c" +#include "southbridge/nvidia/ck804/ck804_early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Index: src/mainboard/tyan/s2895/romstage.c =================================================================== --- src/mainboard/tyan/s2895/romstage.c (revision 5993) +++ src/mainboard/tyan/s2895/romstage.c (working copy) @@ -18,7 +18,7 @@ #include #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.c" +#include "southbridge/nvidia/ck804/ck804_early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Index: src/mainboard/msi/ms7135/romstage.c =================================================================== --- src/mainboard/msi/ms7135/romstage.c (revision 5993) +++ src/mainboard/msi/ms7135/romstage.c (working copy) @@ -46,7 +46,7 @@ #include #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.c" +#include "southbridge/nvidia/ck804/ck804_early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Index: src/mainboard/sunw/ultra40/romstage.c =================================================================== --- src/mainboard/sunw/ultra40/romstage.c (revision 5993) +++ src/mainboard/sunw/ultra40/romstage.c (working copy) @@ -20,7 +20,7 @@ #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.c" +#include "southbridge/nvidia/ck804/ck804_early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" Index: src/mainboard/asus/a8n_e/romstage.c =================================================================== --- src/mainboard/asus/a8n_e/romstage.c (revision 5993) +++ src/mainboard/asus/a8n_e/romstage.c (working copy) @@ -45,7 +45,7 @@ #include #include #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.c" +#include "southbridge/nvidia/ck804/ck804_early_smbus.h" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c"