Hi Jose,and I do similar to you under romstage.c -> mainboard_early_init:outb(0x55, 0x2e);outb(0x05, 0x0a3f); /* GP50= RI_2 : in /outb(0x05, 0x0a40); / GP51= DCD_2 : in /outb(0x05, 0x0a41); / GP52= RXD_2 : in /outb(0x04, 0x0a42); / GP53= TXD_2 : out /outb(0x05, 0x0a43); / GP54= DSR_2 : in /outb(0x04, 0x0a44); / GP55= RTS_2 : out /outb(0x05, 0x0a45); / GP56= CTS_2 : in /outb(0x04, 0x0a46); / GP57= DTR_2 : out */outb(0xaa, 0x2e);but It doesn't work.Also I set the same code under mainboard.c -> mainboard_init butneither work.You should not copy my code for the two major reasons:
SCH5545 and SCH3114 are very different. GPIO configuration on SCH5545 is not accessible from SuperIO. Thecode I have written communicates with Environmental Controller (ARCcoprocessor) which resides inside the SCH5545, because only the EC hadaccess to those registers. The SCH5545 did not have GPIO configregisters in the Runtime Registers block.This will obviously not work.Any advice on this? because I cannot find any information on thedatasheet on how to set those registers and I suppose I just have toset to the 0xa00 base address + register.I suggest to look at TABLE 26-3 in the datasheet of your partand using these runtime registers definitions, write the right code thatwill set the GPIOs up for UARTs. Just use the appropriate 0xa00 base +REG OFFSET from the table and you should be allright. For simplicity youmay also compare these registers to reference values from originalfirmware (but with care! sometimes firmware vendors tend to make stupidmistakes).Thank you,Jose Trujillo.Best regards,coreboot mailing list -- coreboot@coreboot.orgTo unsubscribe send an email to coreboot-leave@coreboot.org