coreboot

coreboot@coreboot.org

6 participants
39687 discussions

basic support for AMD APU
by Tom Psyborg 20 Jan '21

20 Jan '21

Hi Is there any basic code in coreboot tree for recent AMD APUs ? Specifically Bristol Ridge FX-9830P is of my interest, how much work is needed to get laptop booting it?

2 1

Proper way to obtain GbE.bin for Denverton atom
by Balaji Sivakumar 20 Jan '21

20 Jan '21

Hello Everyone, I am currently working on a custom Denverton board similar to the Intel Harcuvar board. I am working to enable the Intel Lan controller, Did anyone generate the GbE.binary(firmware) for the Intel Lan controller of denverton atom or should i check with Intel for binary? We are using flash descriptor and ME binaries integrated into the coreboot, similar way i am working to integrate the GbE binary as well part of coreboot to properly initialize the Lan controller. -- Thanks, Balaji

2 2

Documentation update
by bzt 18 Jan '21

18 Jan '21

Hi everyone, Is there any chance to get this trivial commit merged? https://review.coreboot.org/c/coreboot/+/45829 I've added description of missing payloads and links to Documentation/payloads.md Low priority, but would be nice to have. Thanks, bzt

1 0

Questions about Supermicro X10SL7-F potential with coreboot
by wellywood2018＠gmail.com 17 Jan '21

17 Jan '21

Hi everyone, I have a motherboard (Supermicro X10SL7-F) that appears to be very similar to the supported board X10SLM+-F I would like comment on whether anyone thinks running coreboot on this board would be possible! And if so what work would need to be done to make it a reality. 1. Board description: Vendor: Supermicro Board name: X10SL7-F CPU: Intel Xeon E3-1231 v3 (Haswell) Northbridge: ? Southbridge: Intel C222 Express PCH This board also contains a built-in LSI 2308 disk controller providing 8 SAS2 ports 2. Output of lspci -tvnn on Ubuntu Server 18.04.5: -[0000:00]-+-00.0 Intel Corporation Xeon E3-1200 v3 Processor DRAM Controller [8086:0c08] +-01.0-[01]-- +-01.1-[02]----00.0 LSI Logic / Symbios Logic SAS2308 PCI-Express Fusion-MPT SAS-2 [1000:0086] +-14.0 Intel Corporation 8 Series/C220 Series Chipset Family USB xHCI [8086:8c31] +-1a.0 Intel Corporation 8 Series/C220 Series Chipset Family USB EHCI #2 [8086:8c2d] +-1c.0-[03-04]----00.0-[04]----00.0 ASPEED Technology, Inc. ASPEED Graphics Family [1a03:2000] +-1c.2-[05]----00.0 Intel Corporation I210 Gigabit Network Connection [8086:1533] +-1c.3-[06]----00.0 Intel Corporation I210 Gigabit Network Connection [8086:1533] +-1d.0 Intel Corporation 8 Series/C220 Series Chipset Family USB EHCI #1 [8086:8c26] +-1f.0 Intel Corporation C222 Series Chipset Family Server Essential SKU LPC Controller [8086:8c52] +-1f.2 Intel Corporation 8 Series/C220 Series Chipset Family 6-port SATA Controller 1 [AHCI mode] [8086:8c02] +-1f.3 Intel Corporation 8 Series/C220 Series Chipset Family SMBus Controller [8086:8c22] \-1f.6 Intel Corporation 8 Series Chipset Family Thermal Management Controller [8086:8c24] 3. Output of superiotool -dV on Ubuntu Server 18.04.5: superiotool r6637 Probing for Nuvoton Super I/O at 0x2e... Found Nuvoton NCT6776F (C) (id=0xc333) at 0x2e Register dump: idx 10 11 13 14 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 2a 2b 2c 2d 2e 2f val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff def ff ff 00 00 ff ff ff ff f0 78 00 00 ff ff c3 33 ff 00 64 00 MM 00 00 c0 00 81 00 00 MM LDN 0x00 (FDC) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val ff ff ff ff ff ff ff ff ff ff def 01 03 f0 06 02 0e 00 ff 00 00 LDN 0x01 (Parallel Port) idx 30 60 61 70 74 f0 val ff ff ff ff ff ff def 01 03 78 07 04 3f LDN 0x02 (UART A) idx 30 60 61 70 f0 f2 val ff ff ff ff ff ff def 01 03 f8 04 00 00 LDN 0x03 (UART B, IR) idx 30 60 61 70 f0 f1 f2 val ff ff ff ff ff ff ff def 01 02 f8 03 00 00 00 LDN 0x05 (Keyboard Controller) idx 30 60 61 62 63 70 72 f0 val ff ff ff ff ff ff ff ff def 00 00 00 00 00 00 00 83 LDN 0x06 (CIR) idx 30 60 61 70 f0 f1 f2 f3 val ff ff ff ff ff ff ff ff def 00 00 00 00 08 09 32 00 LDN 0x07 (GPIO6, GPIO7, GPIO8, GPIO9) idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee f4 f5 f6 f7 f8 val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff def 03 ff 00 00 00 ef 00 00 00 ff 00 00 00 00 00 00 ff 00 00 00 00 LDN 0x08 (WDT1, GPIO0, GPIO1, GPIOA) idx 30 60 61 e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff def 02 00 00 ff 00 00 00 ef ff 00 00 00 00 00 00 00 LDN 0x09 (GPIO2, GPIO3, GPIO4, GPIO5) idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ee f0 f1 f2 f4 f5 f6 f7 fe val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff def 04 df 00 00 00 ff 00 00 00 00 00 00 00 00 ff 00 00 ff 00 00 00 00 LDN 0x0a (ACPI) idx e0 e1 e2 e3 e4 e5 e6 e7 e9 ee f0 f2 f3 f4 f6 f7 fe val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff def 01 00 00 00 00 02 1c 00 00 00 00 00 00 00 00 c0 00 LDN 0x0b (Hardware Monitor, Front Panel LED) idx 30 60 61 62 63 70 e0 e1 e2 f0 f1 f2 f5 f6 f7 f8 f9 fa val ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff def 00 00 00 00 00 00 7f 7f ff 00 00 00 10 00 87 47 00 00 LDN 0x0d (VID) idx e0 e1 e2 e3 e4 e5 e6 e9 ee ef f0 f4 f5 val ff ff ff ff ff ff ff ff ff ff ff ff ff def 00 00 00 00 00 00 00 00 88 00 00 00 00 LDN 0x0e (CIR WAKE-UP) idx 30 60 61 70 val ff ff ff ff def 00 00 00 00 LDN 0x0f (GPIO Push-Pull or Open-drain) idx e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 val ff ff ff ff ff ff ff ff ff ff ff ff ff def ff df ff fe f6 ff ff d3 ff 9f 00 00 00 LDN 0x14 (SVID) idx e0 e1 e3 e4 val ff ff ff ff def 00 80 00 00 LDN 0x16 (Deep Sleep) idx 30 e0 e1 e2 val ff ff ff ff def 20 20 04 05 LDN 0x17 (GPIOA) idx e0 e1 e2 e3 e4 e5 val ff ff ff ff ff ff def 01 00 00 00 01 00 4. Output of flashrom -p internal -V on Ubuntu Server 18.04.5: flashrom v0.9.9-r1954 on Linux 4.15.0-112-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.3.1, GCC 5.3.1 20160424, little endian Command line (3 args): flashrom -p internal -V Calibrating delay loop... OS timer resolution is 1 usecs, 3692M loops per second, 10 myus = 9 us, 100 myus = 118 us, 1000 myus = 1031 us, 10000 myus = 9740 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Main Server Chassis" DMI string system-manufacturer: "Supermicro" DMI string system-product-name: "X10SL7-F" DMI string system-version: "0123456789" DMI string baseboard-manufacturer: "Supermicro" DMI string baseboard-product-name: "X10SL7-F" DMI string baseboard-version: "1.01 " Found chipset "Intel C222" with PCI ID 8086:8c52. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap: enabled (A16(+) inverted) 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007fb3b1769000 + 0x3800 0x04: 0xf008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x50: 0x00005a5b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x5a, BRRA 0x5b 0x54: 0x000f0000 FREG0: Warning: Flash Descriptor region (0x00000000-0x0000ffff) is read-only. 0x58: 0x0fff0500 FREG1: BIOS region (0x00500000-0x00ffffff) is read-write. 0x5C: 0x04ff0020 FREG2: Warning: Management Engine region (0x00020000-0x004fffff) is locked. 0x60: 0x001f0010 FREG3: Gigabit Ethernet region (0x00010000-0x0001ffff) is read-write. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0x80 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0x91: 0xf94010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=1 0x94: 0x0006 (PREOP) 0x96: 0x003b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x00009f9f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x80802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xD0: 0x50444653 (FPB) OK. The following protocols are supported: FWH, SPI. Found Micron/Numonyx/ST flash chip "N25Q128..3E" (16384 kB, SPI) mapped at physical address 0x00000000ff000000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Top/Bottom (TB) is top Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Found Micron/Numonyx/ST flash chip "N25Q128..3E" (16384 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). No operations were specified. Restoring MMIO space at 0x7fb3b176c8a0 Restoring PCI config space for 00:1f:0 reg 0xdc Segmentation fault (core dumped) 5. https://www.supermicro.com/en/products/motherboard/X10SL7-F

1 0

[RFC] Amendment to our coding style about text blocks
by Nico Huber 16 Jan '21

16 Jan '21

Hi coreboot folks, I've just pushed a small RFC commit for our coding style: https://review.coreboot.org/c/coreboot/+/49542 From the commit message: It seems since the increase of the code line length to 96 chars, many developers felt encouraged to increase the line length of running text as well. However, text blocks wider than 72 chars are generally harder to read. Let's try to add a sane rule about it. The addition: +This does not apply to running text, e.g. block comments. For text +blocks, the usual limit of 72 chars is strongly encouraged to increase +readability. This may be counted additionally to any indentation, but +the overall line length should not exceed 96 chars. So, that's what it's about. I'd like to see all sorts of opinions on the matter. Maybe there is a reason to deviate from common typesetting rules that I just don't see yet. Generally, I'd prefer to not treat all text like code. Nico

1 0

Help needed: LPC memory mapping / ITE EC H2RAM
by Michael Niewöhner 16 Jan '21

16 Jan '21

Hi all, I'm currently trying to get EC to host memory mapping (H2RAM-HLPC) working on a Clevo L141CU. This will be used by ACPI for the EC ram OpRegion. The EC is an ITE IT5570E. If you don't have access to the datasheet, look for IT8528 or similiar, which is mostly identical irt. memory mapping registers (and many others, too). On vendor firmware, I can access the two EC ram regions at addresses 0xfe700100, 0xfe700380 via /dev/mem (using dd or memtool md 0xfe700100+0x100 for example). The PCH LGMR register has the value 0xfe700001. The address is within the PCH reserved range (0xfc800000-0xfe7fffff). Possible addresses are 0xf[ef]XX_X000, according to the datasheet. Free/unused ranges on CNP should be 0xFE036000-0xFE0AFFFF, 0xFE0D0000-0xFE0FFFFF, 0xFE400000-0xFE5FFFFF and 0xFE600000-0xFE7FFFFF (temp address range for FSP), so there shouldn't be any conflict. EC/superio registers are set as follows: EC: HCTRL2R (0x1036) = 0x80 -> HBREN = 1 -> "1: The host memory cycle is decoded" HRAMWC (0x105A) = 0x03 -> H2RAM memory cycles, H2RAM window 0 and 1 enabled HRAMW0BA (0x105B) = 0x10 -> window 0 starts at 0x100 HRAMW0BA (0x105C) = 0x38 -> window 1 starts at 0x380 HRAMW0AAS (0x105D) = 0x04 -> window 0: no read/write lock, size = 256 bytes HRAMW1AAS (0x105E) = 0x03 -> window 1: no read/write lock, size = 128 bytes SIO LDN 0x0f: 0xF5 = 0x00 -> HLPCRAMBA[15:12] = 0x00 0xF6 = 0x70 -> HLPCRAMBA[23:16] = 0x70 0xFC = 0x00 -> HLPCRAMBA[32:24] = 0xFE -> LGMR address is 0xfe700000 The EC registers are initialized by the EC firmware. No change was needed. The superio registers hand to be configured after enabling the logical device. Unfortunately, mapping doesn't work with coreboot for unknown reasons. Dumping the region only returns 0xff's. I tested both, reading in coreboot and on Linux, just to be sure there's no OS ressource issue. I also tried to change the mapping address. While I successfully tested changing the address to various values on vendor fw by changing LGMR and the SIO registers (0xfe0b0000, 0xfe701000, 0xfe701000, 0xfE600000, ...), I had no success with coreboot. I was able to dump the EC ram windows through the I2EC data/index programming on both vendor fw and coreboot, so I am sure, the ram windows are initialized and filled with sensible data. Any ideas, what could be wrong here? Kind regards Michael / c0d3z3r0

2 1

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 15 Jan '21

15 Jan '21

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1443794: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/amd/picasso/agesa_acpi.c: 555 in gen_crat_memory_entries() ________________________________________________________________________________________________________ *** CID 1443794: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/amd/picasso/agesa_acpi.c: 555 in gen_crat_memory_entries() 549 dram_limit_reg = data_fabric_read_reg32(0, DF_DRAM_LIMIT(dram_map_idx), 550 IOMS0_FABRIC_ID); 551 memory_length = 552 ((dram_limit_reg & DRAM_LIMIT_ADDR) >> DRAM_LIMIT_ADDR_SHFT) + 1 553 - ((dram_base_reg & DRAM_BASE_ADDR) >> DRAM_BASE_ADDR_SHFT); 554 memory_length = memory_length << 28; >>> CID 1443794: Integer handling issues (OVERFLOW_BEFORE_WIDEN) >>> Potentially overflowing expression "(dram_base_reg & 0xfffff000U) << 16" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). 555 memory_base = (dram_base_reg & DRAM_BASE_ADDR) 556 << (28 - DRAM_BASE_ADDR_SHFT); 557 558 if (memory_base == 0) { 559 current = 560 create_crat_memory_entry(0, 0ull, 0xa0000ull, current); ** CID 1443793: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/amd/picasso/agesa_acpi.c: 573 in gen_crat_memory_entries() ________________________________________________________________________________________________________ *** CID 1443793: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/amd/picasso/agesa_acpi.c: 573 in gen_crat_memory_entries() 567 dram_hole_ctl = data_fabric_read_reg32(0, D18F0_DRAM_HOLE_CTL, 568 IOMS0_FABRIC_ID); 569 hole_base = (dram_hole_ctl & DRAM_HOLE_CTL_BASE); 570 size_below_hole = hole_base - memory_base; 571 current = create_crat_memory_entry(0, memory_base, 572 size_below_hole, current); >>> CID 1443793: Integer handling issues (OVERFLOW_BEFORE_WIDEN) >>> Potentially overflowing expression "((dram_limit_reg & 0xfffff000U) >> 12) + 1U - 16U << 28" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned). 573 memory_length = (((dram_limit_reg & DRAM_LIMIT_ADDR) 574 >> DRAM_LIMIT_ADDR_SHFT) 575 + 1 - 0x10) 576 << 28; 577 memory_base = 0x100000000; 578 new_entries++; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 0

Tooling of choice for coordinating and running the coreboot leadership meeting
by Patrick Georgi 15 Jan '21

15 Jan '21

Hi everybody, when announcing today's leadership meeting on IRC I got some replies to the tune of "oh no, Google!" as the meeting minutes are recorded on Google Docs and the meeting itself is held using Google Meet. Note that both are set up to be usable without a Google account, so the impact on users should be limited. That said, if that's a real concern that prevents people from participating who otherwise would like to chime in, we need a solution. To avoid spending too much time on something that may not actually be a problem, I'm asking you: 1. To consider if you care about the leadership meeting (otherwise, please don't create extra work to prove a point about "big tech", software licenses or whatever) 2. If using these two tools for this specific purpose is a problem for you 3. What your ideal alternative solution would look like 4. How your solution would be implemented 5. Present the result of 4 to the list :-) Note that this project, its developers, contributors and maintainers aren't in the business of managing servers or communication suites (although we spend a fair amount of time and money on running coreboot.org to ensure people can contribute with little restrictions: apart from that meeting, everything we do is self-hosted!) so a proposal should be low maintenance for us. This means: running the meeting must not be a hassle (we tried a fair amount of open tools for running the calls: jitsi, mumble and several others, and they fell flat, for example because they sent video streams from everybody to everybody. n^2 traffic growth isn't great), available for the long term (if you offer to run the necessary services for us that's nice, but we'd prefer not to have to change routines again 3 months down the road because your priorities shifted, so any such offer should give us the impression that it's available for the foreseeable future) and not just exchanging one "troublesome" vendor for another (I guess we'll see what "troublesome" means to people in the community.) As for capacity: The meetings take one hour every 14 days. Today's meeting had 17 participants and I think some meetings had a few more folks joining. Those are discussions not presentations, so high-latency streaming options (such as PeerTube's new live stream feature) won't work. Thanks, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

2 1

Questions about ASRock H110M-DVS
by magiccat1＠protonmail.com 14 Jan '21

14 Jan '21

Hi all, I read on Coreboot webpage that this board is in almost full working state https://doc.coreboot.org/mainboard/asrock/h110m-dvs.html . The CPU supported by this board is Kaby Lake which is quite fast for applications. I have a question about the flash chip. The documentation says the flash chip is Macronix MX25L6473E, but is putting in w25q64fvaig flash chip will work too? What about other similar chips, such as GD25B64BPIG? Also, for this board, there are a few variants Asrock Intel H110M-DGS, -DVS, and -HDV. Can I use -DGS for this board? In the documentation, integrated graphics init with libgfxinit (see Known issues) , and VGA is not working. In summary integrated graphics not working, but if I put on a PCIe graphic card, coreboot will work? Also, for this line: I should fill in the actual macaddress ./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" For this line, what does this line do? make olddefconfig Thank you so much,

1 0

question about Coreboot
by ramon g 13 Jan '21

13 Jan '21

Hello, I search on the internet about coreboot and Qubes os. I use a Lenovo ThinkPadT460P i7 16 gb and i have install Qubes OS. Is there a compatible version of Coreboor for a Lenovo ThinkPadT460P i7. I found the X220 and X230. Ramon

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot