coreboot

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39687 discussions

Coreboot on newer hardware after some hardware mods?
by maxime.corne＠protonmail.com 12 Apr '21

12 Apr '21

Hello everyone, I know this question had been asked many times, but is it possible to have Coreboot on modern hardware? After looking at a video ([https://www.youtube.com/watch?v=Tt3bXZXsrE4](https://www.youtube.com/watch?…) I learned that some people were able to put coreboot on recent thinkpads by soldering a new BIOS chip. After some research on the Internet, I found out coreboot couldn’t be port to modern hardware because of an Intel technology which encrypt the bios (I might be wrong, if so, sorry). On the other end, companies like System76 are able to ship modern processor with Coreboot. I’d be more than happy to tinker with my hardware, so how you would you do to put coreboot on a recent thinkpad by replacing the bios chip? Thanks in advance.

3 3

HP compaq 8200 compatability
by ppbruhuwu＠protonmail.ch 12 Apr '21

12 Apr '21

Hello so i was talking to my friend about coreboot but i saw that only the SFF version of the compaq 8200 was compatible and so i wanted to know why that is? Also will coreboot be available for the compaq 8200 in the future? Sent with [ProtonMail](https://protonmail.com) Secure Email.

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 10 Apr '21

10 Apr '21

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 4 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 4 of 4 defect(s) ** CID 1452260: (CONSTANT_EXPRESSION_RESULT) /src/northbridge/intel/x4x/raminit_ddr23.c: 1850 in power_settings() /src/northbridge/intel/x4x/raminit_ddr23.c: 1851 in power_settings() ________________________________________________________________________________________________________ *** CID 1452260: (CONSTANT_EXPRESSION_RESULT) /src/northbridge/intel/x4x/raminit_ddr23.c: 1850 in power_settings() 1844 mchbar_clrsetbits32(0x24, 0xe0000000, 0x60000000); 1845 mchbar_clrsetbits32(0x44, 0x1fef0000, 0x6b0000); 1846 mchbar_write16(0x115, reg1); 1847 mchbar_clrsetbits32(0x117, 0xffffff, reg2); 1848 mchbar_write8(0x124, 0x7); 1849 /* not sure if dummy reads are needed */ >>> CID 1452260: (CONSTANT_EXPRESSION_RESULT) >>> "*((u16 volatile *)0xfed1412a) & -65536 /* ~((uint16_t)~0) */" is always 0 regardless of the values of its operands. This occurs as the bitwise first operand of "|". 1850 mchbar_clrsetbits16(0x12a, ~0, 0x80); 1851 mchbar_clrsetbits8(0x12c, ~0, 0xa0); 1852 mchbar_clrbits16(0x174, 1 << 15); 1853 mchbar_clrsetbits16(0x188, 0x1f00, 0x1f00); 1854 mchbar_clrbits8(0x18c, 1 << 3); 1855 mchbar_setbits8(0x192, 1); /src/northbridge/intel/x4x/raminit_ddr23.c: 1851 in power_settings() 1845 mchbar_clrsetbits32(0x44, 0x1fef0000, 0x6b0000); 1846 mchbar_write16(0x115, reg1); 1847 mchbar_clrsetbits32(0x117, 0xffffff, reg2); 1848 mchbar_write8(0x124, 0x7); 1849 /* not sure if dummy reads are needed */ 1850 mchbar_clrsetbits16(0x12a, ~0, 0x80); >>> CID 1452260: (CONSTANT_EXPRESSION_RESULT) >>> "*((u8 volatile *)0xfed1412c) & -256 /* ~((uint8_t)~0) */" is always 0 regardless of the values of its operands. This occurs as the bitwise first operand of "|". 1851 mchbar_clrsetbits8(0x12c, ~0, 0xa0); 1852 mchbar_clrbits16(0x174, 1 << 15); 1853 mchbar_clrsetbits16(0x188, 0x1f00, 0x1f00); 1854 mchbar_clrbits8(0x18c, 1 << 3); 1855 mchbar_setbits8(0x192, 1); 1856 mchbar_setbits8(0x193, 0xf); ** CID 1452259: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/northbridge/intel/ironlake/quickpath.c: 694 in late_quickpath_init() ________________________________________________________________________________________________________ *** CID 1452259: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/northbridge/intel/ironlake/quickpath.c: 694 in late_quickpath_init() 688 mchbar_write32(0x1274, 0x0); 689 690 if (deven & 8) { 691 mchbar_write16(0x1214, 0x320); 692 mchbar_write32(0x1600, 0x40000000); 693 mchbar_clrsetbits32(0x11f4, ~0, 1 << 28); >>> CID 1452259: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "*((u16 volatile *)0xfed11230) & -65536 /* ~((uint16_t)~0) */" is always 0 regardless of the values of its operands. This occurs as the bitwise first operand of "|". 694 mchbar_clrsetbits16(0x1230, ~0, 1 << 15); 695 mchbar_write32(0x1400, 0x13040020); 696 mchbar_write32(0x1404, 0xe090120); 697 mchbar_write32(0x1408, 0x5120220); 698 mchbar_write32(0x140c, 0x5120330); 699 mchbar_write32(0x1410, 0xe090220); ** CID 1452258: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/northbridge/intel/ironlake/raminit.c: 3103 in chipset_init() ________________________________________________________________________________________________________ *** CID 1452258: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/northbridge/intel/ironlake/raminit.c: 3103 in chipset_init() 3097 3098 dmi_setup(); 3099 3100 mchbar_write16(0x1170, 0xa880); 3101 mchbar_write8(0x11c1, 1 << 0); 3102 mchbar_write16(0x1170, 0xb880); >>> CID 1452258: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "*((u8 volatile *)0xfed11210) & -256 /* ~((uint8_t)~0) */" is always 0 regardless of the values of its operands. This occurs as the bitwise first operand of "|". 3103 mchbar_clrsetbits8(0x1210, ~0, 0x84); 3104 3105 if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { 3106 /* 0 for 32MB */ 3107 gfxsize = 0; 3108 } ** CID 1452257: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/northbridge/intel/ironlake/raminit.c: 3076 in dmi_setup() ________________________________________________________________________________________________________ *** CID 1452257: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/northbridge/intel/ironlake/raminit.c: 3076 in dmi_setup() 3070 3071 static void dmi_setup(void) 3072 { 3073 gav(dmibar_read8(0x254)); 3074 dmibar_write8(0x254, 1 << 0); 3075 dmibar_write16(0x1b8, 0x18f2); >>> CID 1452257: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "*((u16 volatile *)0xfed10048) & -65536 /* ~((uint16_t)~0) */" is always 0 regardless of the values of its operands. This occurs as the bitwise first operand of "|". 3076 mchbar_clrsetbits16(0x48, ~0, 1 << 1); 3077 3078 dmibar_setbits32(0xd68, 1 << 27); 3079 3080 outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000, 3081 DEFAULT_GPIOBASE | 0x38); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 0

x230 Thermal Polling Rate
by Nyx 09 Apr '21

09 Apr '21

What is the Lenovo x230's default thermal polling rate and is there a delay on resume? I've been looking through the source but not really sure what I am looking for since a thermal.asl doesn't seem to be referenced. Basically I have a system where I need to increase the polling rate frequency to 15 seconds otherwise it shuts down as it doesn't get the proper cpu temp on resume. Thanks

1 0

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 09 Apr '21

09 Apr '21

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1452250: Uninitialized variables (UNINIT) ________________________________________________________________________________________________________ *** CID 1452250: Uninitialized variables (UNINIT) /tests/lib/bootmem-test.c: 235 in init_memory_table_library() 229 struct lb_memory *lb_mem; 230 231 /* Allocate space for 10 lb_mem entries to be safe */ 232 lb_mem = malloc(sizeof(*lb_mem) + 10 * sizeof(struct lb_memory_range)); 233 234 /* We need to call this only to initialize library */ >>> CID 1452250: Uninitialized variables (UNINIT) >>> Using uninitialized value "lb_mem->size" when calling "bootmem_write_memory_table". 235 bootmem_write_memory_table(lb_mem); 236 free(lb_mem); 237 } 238 239 static void test_bootmem_add_range(void **state) 240 { ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 0

problem after "convert to ASL 2.0"
by Andrew A. I. 08 Apr '21

08 Apr '21

4 6

On handling vendorcode
by Patrick Georgi 08 Apr '21

08 Apr '21

Hi everybody, We recently landed a change (https://review.coreboot.org/51827) to be more selective which parts of src/vendorcode are checked for coding style because some areas are really coreboot code "by vendors". The original purpose of that subhierarchy was to isolate code we draw in from the outside to make every dev aware that the file they're touching has some upstream other than coreboot and that this code shouldn't be modified except to track that upstream. Any objections to moving the code out there that has no other upstream (e.g. src/vendorcode/google/chromeos or src/vendorcode/eltan, I think?) while moving in code from elsewhere in the tree that fits the "it has a foreign upstream" description (e.g. the lzma library)? Regards, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 06 Apr '21

06 Apr '21

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1452005: Memory - corruptions (OVERRUN) /tests/lib/malloc-test.c: 53 in setup_calloc_test() ________________________________________________________________________________________________________ *** CID 1452005: Memory - corruptions (OVERRUN) /tests/lib/malloc-test.c: 53 in setup_calloc_test() 47 48 return 0; 49 } 50 51 static int setup_calloc_test(void **state) 52 { >>> CID 1452005: Memory - corruptions (OVERRUN) >>> Overrunning buffer pointed to by "&_heap" of 1 bytes by passing it to a function which accesses it at byte offset 4194303 using argument "4194304UL". [Note: The source code implementation of the function has been overridden by a builtin model.] 53 memset(&_heap, 0xFF, TEST_HEAP_SZ); 54 return setup_test(state); 55 } 56 57 static void test_malloc_out_of_memory(void **state) 58 { ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 0

Re: CB:46587 - pirq_routing
by Mike Banon 06 Apr '21

06 Apr '21

Hi there Elyes, Your "getpir" idea really helped me to implement a set of CB:48427 "AMD good IRQ" patches. Thank you so much for your kind help! Wanted to thank you earlier but it got lost in drafts ;-)

1 0

[coreboot - Bug #304] (New) HP EliteBook 2560p fails to reboot on new kernels
by coreboot＠fe80.eu 03 Apr '21

03 Apr '21

Issue #304 has been reported by Iru Cai. ---------------------------------------- Bug #304: HP EliteBook 2560p fails to reboot on new kernels https://ticket.coreboot.org/issues/304 * Author: Iru Cai * Status: New * Priority: Normal * Assignee: Iru Cai * Category: * Target version: ---------------------------------------- My EliteBook 2560p fails to reboot on new kernels. We need to fix the ACPI of hp/kbc1126. After bisecting the kernel, I found this kernel commit is to blame: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?… commit d60cd06331a3566d3305b3c7b566e79edf4e2095 (HEAD, refs/bisect/bad) Author: Kai-Heng Feng <kai.heng.feng(a)canonical.com> Date: Fri Oct 30 15:06:57 2020 +0800 PM: ACPI: reboot: Use S5 for reboot I haven't tested with the OEM firmware yet. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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