coreboot

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39687 discussions

ApolloLake/GeminiLake Status?
by James Feeney 19 Jun '21

19 Jun '21

Back in 2017 there was some brief discussion of how to compile coreboot for apollolake, with some uncertainty about the IFWI segment. Does anyone know the current status of coreboot support for apollolake/geminilake? In particular, to replace a Chromebook boot rom? The coreboot configuration options are confusing in the sense that the intended outcome of particular settings is not explained. For instance, there is coreboot code compiled addressing the Intel FSP, but there are no FSP files generated in the resulting coreboot.rom. Working from a Chromebook bios upgrade image, it seems that many components might simply be copied from there, but then, there seems to be no tool to extract the complete IFWI segment from an existing bios image, except in pieces that would require reassembly. Is there some way that an existing IFWI segment can be extracted and used in another compiled coreboot image? Or, is there "security" code in the IFWI segment that will prevent a compatible working coreboot rom built in this way? James

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Re: Off Topic: Have spare used parts to give away
by James Feeney 18 Jun '21

18 Jun '21

Hey Clay Are your bricked motherboard and bent Ryzen still looking for a home? Send me an email - james(a)nurealm.net James

2 1

tyan mobo?
by Michael Di Domenico 14 Jun '21

14 Jun '21

what's the likely hood that i can get coreboot to run on a tyan gpu server? this one specifically: https://www.tyan.com/Barebones_FT77DB7109_B7109F77DV14HR-2T-NFZ

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coreboot-4.8.1 ... mce errors
by Sven Semmler 11 Jun '21

11 Jun '21

Hi, this is my first time posting here and it is quite possible that I've overlooked something obvious. In that case please just point me to whatever I should have read and accept my apologies. On my ThinkPad T430 running Coreboot-4.8.1 as part of an Heads install, I see these error messages when turning on the PC: mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank: 7: ee20000000 3110a mce: [Hardware Error]: TSC 0 ADDR fefe78c0 MISC 3880000086 mce: [Hardware Error]: PROCESSOR 0:306a9 TIME 1622589409 SOCKET 0 mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank: 8: ee20000000 3110a mce: [Hardware Error]: TSC 0 ADDR fefe7880 MISC 3880000086 mce: [Hardware Error]: PROCESSOR 0:306a9 TIME 1622589409 SOCKET 0 APIC 0 microcode 1f I do not think it is an issue with the actual RAM: [i7-3520M] [2x8GB Silicon Power Hynix] ... no error [i7-3632QM] [2x8GB Silicon Power Hynix] ... mce errors [i7-3520M] [2x8GB Crucial] ... no error [i7-3740QM] [2x8GB Crucial] ... mce errors While looking at this (but for other reasons) I replaced the original i7-3520M with a i7-3632QM and then went back to the original before ultimately settling with a i7-3740QM. I also went through three different sets of RAM, one of them obviously corrupt so I didn't even include it above. All this is to say that the above and some searching leads me to think this might be more of a software / timing issue maybe -- but I am far out of my depth. Hence my asking here for ideas and pointers what to do next. Thanks & Cheers, /Sven -- public key: https://www.svensemmler.org/2A632C537D744BC7.asc fingerprint: DA59 75C9 ABC4 0C83 3B2F 620B 2A63 2C53 7D74 4BC7

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 11 Jun '21

11 Jun '21

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1457506: Null pointer dereferences (REVERSE_INULL) /src/soc/amd/common/block/acpi/bert.c: 19 in acpi_soc_get_bert_region() ________________________________________________________________________________________________________ *** CID 1457506: Null pointer dereferences (REVERSE_INULL) /src/soc/amd/common/block/acpi/bert.c: 19 in acpi_soc_get_bert_region() 13 * BERT: [Firmware Bug]: table invalid. 14 */ 15 if (!bert_should_generate_acpi_table()) 16 return CB_ERR; 17 18 bert_errors_region(region, length); >>> CID 1457506: Null pointer dereferences (REVERSE_INULL) >>> Null-checking "region" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 19 if (!region) { 20 printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); 21 return CB_ERR; 22 } 23 24 return CB_SUCCESS; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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coreboot not starting on denverton_ns
by Sumo 10 Jun '21

10 Jun '21

Hi, Coreboot is not starting on denverton due to this commit: * 0f068a600e drivers/intel/fsp2_0: Fix the FSP-T position (found this by doing a manual git bisect using an old commit as reference, everything was working good around november 2020) Basically it crashes, nothing is shown in the console output. Any advice? Kind regards, Sumo

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ASUS F2A85-M PRO VGA BIOS binary extraction
by se7enge 09 Jun '21

09 Jun '21

Dear Coreboot Team, I am about to embark on a mission to install coreboot on an ASUS F2A85-M PRO (w/ AMD A10-6800k) desktop machine. Admittedly, I don't have much experience in this field and am not extremely technical; but I am willing to learn and put in the effort needed. My main question to you at this time is regarding the extraction of the VGA BIOS binary, in order to make the integrated GPU function as intended, and how one goes about doing it. I have downloaded the available .CAP (BIOS image?) file from the official Asus support page (https://www.asus.com/supportonly/F2A85-M%20PRO/HelpDesk_BIOS/) and I can see that on your own documentation page for the ASUS F2A85-M (https://doc.coreboot.org/mainboard/asus/f2a85-m.html) you have recommended that one should use 'MMTool Aptio' in order to load the image and extract the VGA binary. However, I have struggled to find any official download or support page for this tool and it does not appear to be in my official distro repository or the AUR either. I am therefore seemingly unable to get a hold of it and follow your documentation. Please could you advise on the best way to solve this problem so that I may successfully extract the needed binary and continue on to compile the coreboot ROM. Any support is much appreciated :) Kind regards, se7enge

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Off Topic: Have spare used parts to give away
by Clay Daniels 09 Jun '21

09 Jun '21

Now that I have rebuilt my machine after a bad flash which was my own fault, I have a few used parts that can be reused with some repair. I have a MSI X570-A Pro motherboard that needs re-flashing or "unbricking", and a AMD Ryzen 7 3700X processor that has bent pins that I think can be straightened. I was going to re-use the processor, but getting it loose from the cooling assembly did not go well. I also have the new fan & cooling assembly, with some extra thermal grease. Now that I've got my home-built machine up & running again, I'm not too proud to admit my mistakes, and wonder if at least the nice Ryzen 7 processor can find a new home. Clay Daniels Fort Worth, Texas

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tianocore only showing 2gb of 8gb installed ram
by J c 08 Jun '21

08 Jun '21

Any ideas? thanks https://www.reddit.com/r/coreboot/comments/nuf2qh/coreboot_wtianocore_on_t4… I have this problem too. ESC key shows 8GB, Memmap in efi shell shows 2gb. Osx says 8gb. Ubuntu says 2gb (macbookpro10,1) uefipayload.. do u need the hw_probe info? Can I ask in tiancore.buzilla ? fastly is down why the 6gb ram is reserved?? (Reserved 0000000100000000-000000027C5FFFFF 000000000017C600 000000000000000F`) 1558016 pages RT_Data 000000007FF41000-000000007FF41FFF 0000000000000001 800000000000000F BS_Data 000000007FF42000-000000007FF42FFF 0000000000000001 000000000000000F Reserved 0000000000000000-0000000000000FFF 0000000000000001 000000000000000F Reserved 00000000000A0000-00000000000FFFFF 0000000000000060 000000000000000F Reserved 000000007FF43000-00000000829FFFFF 0000000000002ABD 000000000000000F Reserved 00000000F0000000-00000000F3FFFFFF 0000000000004000 000000000000000F Reserved 00000000FED90000-00000000FED91FFF 0000000000000002 000000000000000F Reserved 0000000100000000-000000027C5FFFFF 000000000017C600 000000000000000F Reserved : 1,585,445 Pages (6,493,982,720 Bytes) LoaderCode: 580 Pages (2,375,680 Bytes) LoaderData: 0 Pages (0 Bytes) BS_Code : 1,239 Pages (5,074,944 Bytes) BS_Data : 8,252 Pages (33,800,192 Bytes) RT_Code : 77 Pages (315,392 Bytes) RT_Data : 239 Pages (978,944 Bytes) ACPI_Recl : 1 Pages (4,096 Bytes) ACPI_NVS : 2 Pages (8,192 Bytes) MMIO : 0 Pages (0 Bytes) MMIO_Port : 0 Pages (0 Bytes) PalCode : 0 Pages (0 Bytes) Available : 513,607 Pages (2,103,734,272 Bytes) Persistent: 0 Pages (0 Bytes) -------------- Total Memory: 2,046 MB (2,146,291,712 Bytes) (Grub 2 is fine, ubuntu detects 8gb) [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 [ 0.000000] BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable [ 0.000000] BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000007ff44fff] usable [ 0.000000] BIOS-e820: [mem 0x000000007ff45000-0x000000007fffffff] type 16 [ 0.000000] BIOS-e820: [mem 0x0000000080000000-0x00000000829fffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved [ 0.000000] BIOS-e820: [mem 0x00000000fed90000-0x00000000fed91fff] reserved [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000027c5fffff] usable [ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000027c5fffff] usable coreboot cbmem says 10. 0000000100000000-000000027c5fffff: RAM from uefipayload tianocore 8. 0000000100000000 - 000000027C5FFFFF [01] buildhob: base = 0x100000000, size = 0x17C600000, type = 0x0 ConvertPages: failed to find range 100000000 - 27C5FFFFF (I hope the enable tianocore logging in cbmem is useful here..)

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Re: link time optimization testing - Was: Re: asus/p2b - not enough space in cbfs for default build since i440bx bootblock console enable
by Branden Waldner 08 Jun '21

08 Jun '21

On 5/25/21, Paul Menzel <pmenzel(a)molgen.mpg.de> wrote: > Dear Branden, > > > Am 22.05.21 um 20:03 schrieb Branden Waldner: >> On 5/21/21, Arthur Heymans <arthur(a)aheymans.xyz> wrote: > >>> Thanks for sharing your findings. The flash is 256K big, which is quite >>> small these days. >>> When building coreboot with default settings but without a payload I >>> find >>> that there is 69K empty space left for payloads. >>> >>> Some future developments I have been working on might give a bit more >>> breathing space. >>> - I want to make romstage optional and include the sources in the >>> bootblock: That should shave off roughly 10K of romstage. >>> - I have compressing postcar working (maybe you can also disable the >>> postcar console to reduce size). That's also 2-3k size gains >>> at likely the const of a tiny bit of boot performance on this platform. >>> - I also have some WIP code to merge postcar into ramstage which would >>> save >>> 15k. >>> >>> Maybe on coreboot release 4.15 you will have a better time building a >>> fully >>> working image with the default configuration. > >> I didn't realize there was development going on to save rom space, >> that's good to know. > > I just built the asus/p2b from commit d981c490 (mb/google/mancomb: > Enable some PCIe power saving features) with the Debian sid/unstable > toolchain (gcc (Debian 10.2.1-6) 10.2.1 20210110). > > There, wasn’t enough space to add SeaBIOS’ configuration file to CBFS. > Not setting `INCLUDE_CONFIG_FILE`, there wasn’t any error, the coreboot > image built fine. > > ``` > FMAP REGION: COREBOOT > Name Offset Type Size Comp > cbfs master header 0x0 cbfs header 32 none > fallback/romstage 0x80 stage 17336 none > cpu_microcode_blob.bin 0x44c0 microcode 83968 none > fallback/ramstage 0x18d00 stage 53376 LZMA > (112168 decompressed) > build_info 0x25e00 raw 89 none > fallback/dsdt.aml 0x25e80 raw 5514 none > cmos_layout.bin 0x27440 cmos_layout 704 none > fallback/postcar 0x27740 stage 16888 none > fallback/payload 0x2b980 simple elf 69886 none > (empty) 0x3cac0 null 1956 none > bootblock 0x3d280 bootblock 11088 none > ``` > > Building with Jacob’s link time optimization changes [1], which he > thankfully rebased, saved 13 kB, so the configuration file would fit in > too. > > ``` > FMAP REGION: COREBOOT > Name Offset Type Size Comp > cbfs master header 0x0 cbfs header 32 none > fallback/romstage 0x80 stage 14752 none > cpu_microcode_blob.bin 0x3ac0 microcode 83968 none > fallback/ramstage 0x18300 stage 46277 LZMA > (95496 decompressed) > build_info 0x23840 raw 89 none > fallback/dsdt.aml 0x238c0 raw 5514 none > cmos_layout.bin 0x24e80 cmos_layout 704 none > fallback/postcar 0x25180 stage 14872 none > fallback/payload 0x28c00 simple elf 69886 none > (empty) 0x39d40 null 15012 none > bootblock 0x3d800 bootblock 9664 none > ``` > > (If you have a recovery option and some spare time, it’d be great if you > tested the LTO patches.) I could probably test them out, though I'm not sure I'll get around to it right away. Does the patch set require anything special? It looks like it just uses a Kconfig to add the choice to use the LTO compiler options. Does it work with the coreboot crossgcc or should I try using the system compiler on the build machine like you did (Debian sid x86_64), or maybe it would be best to try both? My recovery method isn't very good right now though. If I've got a boot failure I change the rom to a known good one and hot swap back to the chip with the bad rom to reflash it. It's pretty annoying, but I haven't messed up yet. I did try to get some (cheap) zif adapter sockets, but they didn't work out for me - not enough space and they don't seat in a socket, they seem to be meant to be soldered to a board, not used in a socket. I haven't had much luck in finding options for recovery. Ideally I'd like something like the dual switched bios in the old wiki but toggle-able electronically ie. gpio pin from spare router w/ Openwrt. That sounds like a lot of work though and I never managed to find much online as examples. > > Kind regards, > > Paul > > > [1]: https://review.coreboot.org/c/coreboot/+/40815/ > (whole series) > Branden

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