coreboot

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39687 discussions

Re: Build for F2A85-M Foobared, any ideas?
by Paul Menzel 17 Aug '21

17 Aug '21

Dear Keith, Am 16.08.21 um 12:39 schrieb Keith Emery: > I went one further and just deleted the whole working directory, > re-cloned coreboot and built using that exact configuration. All to > little avail. Please do not leave the other questions/requests unanswered. > How do I go about finding the exact commit that was used in the log? It’s in the path name or logs in the directory I referenced: 4.13-917-g192177d34d refers to commit hash 192177d34d. Kind regards, Paul PS: It’s common to interleaved style when replying (on mailing lists).

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SPI Flash console output
by Keith Emery 17 Aug '21

17 Aug '21

Does anybody happen to know when or why SPI Flash console output broke? I kind of need it. The build only fails when I enable said option. The error is as follows, name of home directory redacted: coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/bootblock/drivers/spi/spi-generic.o: in function `spi_setup_slave': coreboot/src/drivers/spi/spi-generic.c:118: undefined reference to `spi_ctrlr_bus_map_count' coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: coreboot/src/drivers/spi/spi-generic.c:119: undefined reference to `spi_ctrlr_bus_map' coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: coreboot/src/drivers/spi/spi-generic.c:119: undefined reference to `spi_ctrlr_bus_map' coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: coreboot/src/drivers/spi/spi-generic.c:121: undefined reference to `spi_ctrlr_bus_map' make: *** [src/arch/x86/Makefile.inc:90: build/cbfs/fallback/bootblock.debug] Error 1

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Denverton: NVMe not detected when serial console logs are disabled
by Sumo 16 Aug '21

16 Aug '21

Hi, The NVMe is not detected when serial console logs are disabled, I mean by setting both Coreboot log_level=Error (or less) and FSP PcdFspDebugPrintErrorLevel=NoDebug. Looks like the enumeration fails then further on the device is not listed in the UEFI FW (same issue shown in either CorebootPayloadPkg or UefiPayloadPkg). When Linux boots the device appears normally. The problem is fixed by adding a small delay inside dev_enumerate() - a 20ms delay at the very beginning of the function is enough. I'm wondering if there is a better solution for this, the device is already defined in the devicetree.cb (set as on). Maybe coreboot is too fast and the NVMe is still booting up - or the PCIe link is still training, not sure. Coreboot doesn't retry if the device is not detected right away? Kind regards, Sumo

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Stuck on Coreboot logo
by Leo Roberts 16 Aug '21

16 Aug '21

I don't know if you offer any support but I have inherited a HP G4 chromebook stuck on the Coreboot logo. The escape key does not work even with an external keyboard. Can you point me in the right direction? Thank you, Dr. Leo Roberts

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Build for F2A85-M Foobared, any ideas?
by Keith Emery 16 Aug '21

16 Aug '21

coreboot-4.14-1405-gad08265740-dirty Sun Aug 15 07:12:41 UTC 2021 bootblock starting (log level: 7)... CBFS: Found 'fallback/romstage' @0x30e00 size 0x4c910 in mcache @0x00034f7c BS: bootblock times (exec / console): total (unknown) / 12 ms coreboot-4.14-1405-gad08265740-dirty Sun Aug 15 07:12:41 UTC 2021 romstage starting (log level: 7)... APIC 00: CPU Family_Model = 00000663 APIC 00: ** Enter AmdInitReset [00020007] ASSERTION ERROR: file 'src/drivers/amd/agesa/state_machine.c', line 256 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 332 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c', line 70 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c', line 73 Fch OEM config in INIT RESET ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 768 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 926 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 817 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 926 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 768 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 926 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 817 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 926 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 768 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 926 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 817 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 926 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 768 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 926 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 817 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/common/amdlib.c', line 926 AmdInitReset() returned AGESA_SUCCESS APIC 00: Heap in LocalCache (2) at 0x00400000 APIC 00: ** Exit AmdInitReset [00020007] APIC 00: ** Enter AmdInitEarly [00020002] ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 332 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.c', line 205 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c', line 169 ASSERTION ERROR: file 'src/drivers/amd/agesa/state_machine.c', line 256 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 332 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 332 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 332 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/HT/htMain.c', line 562 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 483 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 872 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 483 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 872 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 735 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 483 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 261 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 872 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 727 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 728 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 735 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 483 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 261 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 872 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 727 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 728 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 735 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 483 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 261 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 872 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 727 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 728 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c', line 606 ASSERTION ERROR: file 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line 735

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Re: Question On External Display
by Rao G 12 Aug '21

12 Aug '21

Hi Nico, Thanks for your email & response. The problem originally I had was that on PortC, DP/HDMI did not work for the external display in the OS, In BIOS it looked good, so I configured PortC as an eDP interface then the external display started working in the OS. Now at runtime when there is no external display, the VBIOS is causing delay, so I want to disable PortC for eDP at runtime when there is no external display connected. So am trying to find which MMIO register gets set when there is external Display connected to DisplayPort Thanks Rao On Fri, Jul 30, 2021 at 3:29 PM Rao G <grao.v80(a)gmail.com> wrote: > Hi Nico, > > Thanks for your response, though I enabled Bits 29,28,27 in 0x61110h, the > values in 0x61114h returned 0, > I have configured the port as eDP in VBIOS not as HDMI/DP, will that > make a difference? > For eDP which MMIO register need to be checked? > > Thanks > Rao > > On Fri, Jul 30, 2021 at 2:47 PM Nico Huber <nico.h(a)gmx.de> wrote: > >> Hello Rao, >> >> On 30.07.21 13:53, Rao G wrote: >> > trying to see the MMIO or VBIOS data when a external display device is >> > plugged/unplugged with DP/HDMI interface, which MMIO register is set or >> > cleared >> >> I think you are looking at the right register (last one below). >> >> > >> > Any inputs are appreciated, some of the registers tried on Port B/Port C >> > are given below. when Display is connected and when Display is not >> > connected, both these instances >> > return the same data. Looking for register/bit that sets/clears when >> > external display is connected/disconnected >> > >> > printk(BIOS_DEBUG, "Intel Gfx BAR GTTMMADR\n"); >> > printk(BIOS_DEBUG, " DP_B %X\n", read32(bar+0x180000+0x64100)); >> > printk(BIOS_DEBUG, " DP_C %X\n", read32(bar+0x180000+0x64200)); >> > printk(BIOS_DEBUG, " HDMIC %X\n", read32(bar+0x180000+0x61160)); >> > printk(BIOS_DEBUG, " HDMIB %X\n", read32(bar+0x180000+0x61140)); >> > printk(BIOS_DEBUG, " Hotplug control %X\n", >> read32(bar+0x180000+0x61164)); >> > printk(BIOS_DEBUG, " pipeA control %X\n", read32(bar+0x180000+0x61204)); >> > printk(BIOS_DEBUG, " pipeB control %X\n", read32(bar+0x180000+0x61304)); >> > printk(BIOS_DEBUG, " porthot plug stat %X\n", >> read32(bar+0x180000+0x61114)); >> >> According to the datasheet, the bits in this register should change but >> only if enabled in PORT_HOTPLUG_EN (0x61110). >> >> Nico >> >> NB. There is also libgfxinit support under review [1]. In case you are >> trying to do some native graphics init ;) >> >> [1] https://review.coreboot.org/q/topic:%2522baytrail-libgfxinit%2522 >> >

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FsptUpd.h: No such file or directory - compilation terminated - Error 1
by James Feeney 06 Aug '21

06 Aug '21

$ cat defconfig ... CONFIG_ADD_FSP_BINARIES=y ... There is *no* "fspt.bin" file in this chromebook recovery bios file used as source. $ make ... src/soc/intel/apollolake/fspcar.c:3:10: fatal error: FsptUpd.h: No such file or directory #include <FsptUpd.h> ^~~~~~~~~~~ compilation terminated. make: *** [Makefile:379: build/bootblock/soc/intel/apollolake/fspcar.o] Error 1 What Makefile is that? There is no such line 379. $ find -name FsptUpd.h ... ./3rdparty/fsp/ApolloLakeFspBinPkg/Include/FsptUpd.h ... $ less src/soc/intel/alderlake/Kconfig ... config FSP_HEADER_PATH string "Location of FSP headers" default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" $ less src/drivers/intel/fsp2_0/Kconfig ... config FSP_T_FILE string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_FULL_FD depends on ADD_FSP_BINARIES depends on FSP_CAR default "\$(obj)/Fsp_T.fd" if FSP_FULL_FD help The path and filename of the Intel FSP-T binary for this platform. $ make nconfig ... > Generic Drivers ... (src/vendorcode/intel/fsp/fsp2_0/glk) Location of FSP headers How did that get there? Not me... $ ll src/vendorcode/intel/fsp/fsp2_0/glk total 116 drwxr-x--- 2 james james 4096 Oct 29 2020 . drwxr-x--- 9 james james 4096 Jun 14 19:04 .. -rw-r----- 1 james james 45977 Oct 29 2020 FspmUpd.h -rw-r----- 1 james james 57332 Oct 29 2020 FspsUpd.h -rw-r----- 1 james james 1967 Oct 29 2020 FspUpd.h Why is src/soc/intel/apollolake/fspcar.c being built here? It seems that no fspt.bin file is needed. James

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[coreboot - Bug #317] (New) "make savedefconfig" broken
by coreboot＠fe80.eu 04 Aug '21

04 Aug '21

Issue #317 has been reported by Wladislav Artsimovich. ---------------------------------------- Bug #317: "make savedefconfig" broken https://ticket.coreboot.org/issues/317 * Author: Wladislav Artsimovich * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- With Manjaro Linux and newest Updates, in coreboot git master, performing `make savedefconfig` without errors out with: ~~~ cp: missing destination file operand after '/home/gigi/coreboot-debug/Latest/.config' Try 'cp --help' for more information. make: *** [/home/gigi/coreboot-debug/Latest/util/kconfig/Makefile.inc:34: savedefconfig] Error 1 ~~~ System info: ~~~ System: Host: gigi-pc Kernel: 5.10.53-1-MANJARO x86_64 bits: 64 compiler: gcc v: 11.1.0 Desktop: Budgie 10.5.3 wm: budgie-wm dm: LightDM Distro: Manjaro Linux base: Arch Linux CPU: Info: Quad Core model: Intel Core2 Extreme Q9300 bits: 64 type: MCP arch: Penryn rev: A cache: L2: 6 MiB flags: lm nx pae sse sse2 sse3 sse4_1 ssse3 bogomips: 20277 Speed: 2533 MHz min/max: 1600/2534 MHz boost: enabled Core speeds (MHz): 1: 2533 2: 2534 3: 2534 4: 2534 Graphics: Device-1: Intel Mobile 4 Series Integrated Graphics vendor: Lenovo driver: i915 v: kernel bus-ID: 00:02.0 chip-ID: 8086:2a42 Display: x11 server: X.Org 1.20.11 compositor: budgie-wm driver: loaded: intel resolution: 1920x1200 s-dpi: 96 OpenGL: renderer: Mesa DRI Mobile Intel GM45 Express (CTG) v: 2.1 Mesa 21.1.5 direct render: Yes ~~~ -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

1 0

[coreboot - Bug #316] (New) [crossgcc] Toolchain building for older Versions broken
by coreboot＠fe80.eu 04 Aug '21

04 Aug '21

Issue #316 has been reported by Wladislav Artsimovich. ---------------------------------------- Bug #316: [crossgcc] Toolchain building for older Versions broken https://ticket.coreboot.org/issues/316 * Author: Wladislav Artsimovich * Status: New * Priority: Normal * Assignee: * Category: build system * Target version: ---------------------------------------- Building older versions of Coreboot (Tested was 4.10, 4.11, 4.12) errors out at different stages, on Manjaro Linux, with the latest updates. Building from git master works though. `make crossgcc-i386 CPUS=$(nproc)` fails with: **4.10:** ~~~ Building BINUTILS v2.32 for target ... failed. Check 'build-i386-elf-BINUTILS/build.log'. make[2]: *** [Makefile:26: build_gcc] Error 1 make[1]: *** [Makefile:48: build-i386] Error 2 make *** [util/crossgcc/Makefile.inc:47: crossgcc-i386] Error 2 ~~~ **4.11:** ~~~ Building BINUTILS v2.32 for target ... failed. Check 'build-i386-elf-BINUTILS/build.log'. make[2]: *** [Makefile:26: build_gcc] Error 1 make[1]: *** [Makefile:51: build-i386] Error 2 make *** [util/crossgcc/Makefile.inc:48: crossgcc-i386] Error 2 ~~~ **4.12:** ~~~ Building GCC v8.3.0 for target ... failed. Check 'build-i386-elf-GCC/build.log'. make[2]: *** [Makefile:26: build_gcc] Error 1 make[1]: *** [Makefile:51: build-i386] Error 2 make *** [util/crossgcc/Makefile.inc:35: crossgcc-i386] Error 2 ~~~ The logs are attached mentioned in these errors are attached. ~~~ System: Host: gigi-pc Kernel: 5.10.53-1-MANJARO x86_64 bits: 64 compiler: gcc v: 11.1.0 Desktop: Budgie 10.5.3 wm: budgie-wm dm: LightDM Distro: Manjaro Linux base: Arch Linux CPU: Info: Quad Core model: Intel Core2 Extreme Q9300 bits: 64 type: MCP arch: Penryn rev: A cache: L2: 6 MiB flags: lm nx pae sse sse2 sse3 sse4_1 ssse3 bogomips: 20277 Speed: 2533 MHz min/max: 1600/2534 MHz boost: enabled Core speeds (MHz): 1: 2533 2: 2534 3: 2534 4: 2534 Graphics: Device-1: Intel Mobile 4 Series Integrated Graphics vendor: Lenovo driver: i915 v: kernel bus-ID: 00:02.0 chip-ID: 8086:2a42 Display: x11 server: X.Org 1.20.11 compositor: budgie-wm driver: loaded: intel resolution: 1920x1200 s-dpi: 96 OpenGL: renderer: Mesa DRI Mobile Intel GM45 Express (CTG) v: 2.1 Mesa 21.1.5 direct render: Yes ~~~ I need to build those older versions to properly build up and test an issue about Coreboot + Grub being broken on the Thinkpad x200 since 4.12. ---Files-------------------------------- 4.12-build-i386-elf-GCC-build.log (6.59 KB) 4.11-build-i386-elf-BINUTILS-build.log (133 KB) 4.10-build-i386-elf-BINUTILS-build.log (187 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

1 0

Does coreboot support ASRock H110M-DVS R3.0?
by Alexander Zhang 02 Aug '21

02 Aug '21

Hello, Does anyone know if coreboot supports the ASRock H110M-DVS R3.0 mainboard? The documentation doesn't mention the revision number but the links are all for the R2.0 board and I can only find R3.0 boards for sale. Thanks, Alex

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