coreboot

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39687 discussions

Help debugging qemu + coreboot using GDB
by Ni, Ray 23 Sep '21

23 Sep '21

Hi experts, I built a coreboot image with following steps for tracing coreboot ramstage flow: 1. make menuconfig --- CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y CONFIG_GDB_STUB=y CONFIG_GDB_WAIT=y --- 1. make crossgcc-i386 2. make Then I start gdb: 1. gdb 2. (gdb) file /mnt/e/work/coreboot/build/cbfs/fallback/ramstage.debug Reading symbols from /mnt/e/work/coreboot/build/cbfs/fallback/ramstage.debug... 1. (gdb) target remote:1234 Then I start QEMU: 1. qemu-system-i386 --bios build/coreboot.rom -nographic -M q35 -s --- tty out put as below --- ... Timestamp - finished loading ramstage: 627985288 BS: postcar times (exec / console): total (unknown) / 80 ms $S02#b5$S02#b5$S02#b5$S02#b5$S02#b5$S02#b5$S02#b5$S02#b5$S02#b5$S02# ------------ (The "$S02#B5" repeats infinitely. I guess it's to report a stop event to GDB.) The GDB successfully connects to coreboot. "disassemble $eip, +20" works fine. "n" command doesn't work. (gdb) n Cannot find bounds of current function What mistake I might make? Thanks, Ray

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Mailing list archive not updating
by Branden Waldner 23 Sep '21

23 Sep '21

I was just checking the mailing list archive and noticed that it isn't showing any new messages since September 9. I wasn't able to determine if there was a mailing list admin address to send this to, so I hope just sending it to the list is okay. (I did see this "mailman(a)coreboot.org alias for mailman admins" while searching, but wasn't sure about it, since it doesn't actually show up on the available lists page.)

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How to enable SMMStore on MinowboardMax
by zahra rahimkhani 22 Sep '21

22 Sep '21

Hello I am trying to enable NVRAM for MainnoMax for the 4.11 branch. I am trying to save persistence config in SOC E3825. (It has a MC146818B-compatible 242 bytes of battery-backed RAM). I enabled the following options in coreboot 4.11 branch: - Use CMOS for configuration values - Load default config values on each boot And tested whether the configuration made by nvramcui (as my second mayload) is persistent across power-offs with no luck. I have the following questions and I would appreciate it if anyone can answer any of these questions: 1.How to enable coreboot to save configuration on MinnowMAX? 2.With the battery connected to the board, is it correct to use nvramcui to check persistent configuration? 3. I read about SMMSTORE as a way to store configuration changes in BIOS without having an actual EEPROM storage but I don't know if I have to enable it explicitly if my board doesn't support it. 4. How one can add SMMSTORE support for SoCs like Intel E3800 families. Also I would be grateful if anyone can send me links to investigate any further.

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T430: Flashing using plug contacts instead of fully disassembling the laptop
by Daniel Kulesz 21 Sep '21

21 Sep '21

Hi, I plan to flash a Thinkpad T430. According to an article in the german "golem.de" magazine [1] accessing the flash via SPI is possible by connecting the wires from the SPI flasher to plug contacts on the upper side of the board - without disassembling the whole device. Unfortunately, I was unable to find the details regarding these contacts neither in the coreboot docs nor anywhere else. Did I look in the wrong places or is this simply not publically documented? Cheers, Daniel [1] https://www.golem.de/news/coreboot-und-nitrokey-mein-acht-jahre-alter-lapto…

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custom board profile
by Brian Milliron 21 Sep '21

21 Sep '21

So now that I have the GPIO for my board, what else is needed? How do I setup a custom board profile in coreboot? How much debug/testing would be needed? How would that be done?

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Fwd: Denverton: NVMe not detected when serial console logs are disabled
by Sumo 21 Sep '21

21 Sep '21

Hi Paul, When logs are (almost) disabled the error isn't shown, so if I add the delay with logs disabled the log output will have almost no difference at all. Following are the logs, including a log with Coreboot debug enabled + no delay. For all logs FSP loglevel is set to NoDebug: - nvme-err.log : no delay; coreboot debug_level=Error; NVMe error: at the end of the log is shown the error in the UEFI FW: ERROR: C40000002:V02010007 I0 93B80004-9FB3-11D4-9A3A-0090273FC14D 7E90A998; - nvme-ok-delay.log : 20ms delay; coreboot debug_level=Error; NVMe ok; - nvme-ok.log : no delay; coreboot debug_level=Spew; NVMe ok: the coreboot log output is enough to make NVMe work properly; The NVMe is in the root port 00:0b.0, it is shown as 04:00.0 Thanks, Sumo On Mon, Aug 16, 2021 at 2:57 PM Paul Menzel <pmenzel(a)molgen.mpg.de> wrote: > Dear Sumo, > > > Am 16.08.21 um 18:38 schrieb Sumo: > > > The NVMe is not detected when serial console logs are disabled, I mean by > > setting both Coreboot log_level=Error (or less) and FSP > > PcdFspDebugPrintErrorLevel=NoDebug. Looks like the enumeration fails then > > further on the device is not listed in the UEFI FW (same issue shown in > > either CorebootPayloadPkg or UefiPayloadPkg). When Linux boots the device > > appears normally. > > > > The problem is fixed by adding a small delay inside dev_enumerate() - a > > 20ms delay at the very beginning of the function is enough. I'm wondering > > if there is a better solution for this, the device is already defined in > > the devicetree.cb (set as on). Maybe coreboot is too fast and the NVMe is > > still booting up - or the PCIe link is still training, not sure. Coreboot > > doesn't retry if the device is not detected right away? > > Please share the logs without and with the delay. > > > Kind regards, > > Paul >

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Coreboot on newer laptops
by Brian Milliron 18 Sep '21

18 Sep '21

I've run into 2 problems with trying to set up coreboot for an HP Probook 440 G7. The first is that I don't see this model listed as an option in the menuconfig. It is a newer Intel Cometlake CPU/chipset and most of what I see listed as options are much older machines. Is there a "generic cometlake" config I can try or am I just out of luck on this? The 2nd problem is that cbfstool doesn't recognize the bios dump I did from the mainboard. I get the error "Selected image region is not a valid CBFS." I'm pretty sure the the dump is valid because I can read it using the Intel FIT tool or ME_Analyzer. I'm going to need to pull the various binary blobs out of the current firmware and this is the only way I know how. Is there another option here?

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 14 Sep '21

14 Sep '21

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1462119: Resource leaks (RESOURCE_LEAK) /src/soc/intel/common/block/acpi/pep.c: 68 in read_pmc_lpm_requirements() ________________________________________________________________________________________________________ *** CID 1462119: Resource leaks (RESOURCE_LEAK) /src/soc/intel/common/block/acpi/pep.c: 68 in read_pmc_lpm_requirements() 62 } 63 64 if (info) { 65 info->addr = (uint8_t *)reg; 66 info->buffer_size = register_count * sizeof(uint32_t); 67 } >>> CID 1462119: Resource leaks (RESOURCE_LEAK) >>> Variable "reg" going out of scope leaks the storage it points to. 68 } 69 70 /* 71 * For now there is only one disabled non-existent device, because Windows 72 * expects at least one device and crashes without it with a bluescreen 73 * (`INTERNAL_POWER_ERROR`). Returning an empty package does not work. ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Using cmos.default / nvramtool?
by Rafael Send 14 Sep '21

14 Sep '21

Hi all- I'm trying to set gfx_uma_size on my X210. From what I can tell, I need to either use nvramcui / nvramtool to set this, or add a cmos.default file. However, I'm not clear on how to do this correctly. If I just invoke nvramtool, I'm told that this coreboot was built without selecting "CONFIG_USE_OPTION_TABLE, which is not found in menuconfig. How do I go about creating &using a proper cmos.layout file for my machine? Thanks, R

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Re: New Kabylake-U Laptop (Acer Aspire F5-573)
by Benjamin Doron 12 Sep '21

12 Sep '21

Hi, The return value 0x80000007 is EFI_DEVICE_ERROR, which is unfortunately for us, not very specific. The schematics will be a big help to you, if you can get them. However, you can probably manage without them. There are 3 BIOS images in the update binary from Acer. I took the liberty of assuming the relevant one was the 8 MiB file, as your SPI flash is 64 Mb. I've checked this image, and while its silicon configuration modules now more closely align with Intel's code (*OpenBoardPkg and *BoardPkg, MinPlatformPkg and reference code), so the work I've done for an Acer Skylake laptop doesn't help you, the theory is the same. The relevant modules for setting FSP-M configuration are BoardConfigInitPreMem and possibly PlatformInitPreMem. Since the RCOMP resistors and targets have a known structure (3 and 5 UINT16s, also with a somewhat predictable pattern), a good way to skip a lot of reverse engineering is to search a hexdump for known/common values, or eyeball the .data section. You may want to do this in IDA (costly, proprietary) or Ghidra (free, open-source), so that you can follow the references the code makes to the variables. I found some possible RCOMP resistors in BoardConfigInitPreMem, which brings us to 1, maybe 2, relevant functions. Depending on the board ID, the function loaded at 0xFFF15F48 will assign SpdAddressTable, DqByteMap, DqsMapCpu2Dram, RcompResistors, RcompTargets and others. coreboot boards generally ignore Dqs settings these days (except for LPDDR3/4, as I understand), so I'll just give you the possible RCOMP values, as I see them: - RCOMP targets: { 100, 40, 40, 23, 40 }, or { 100, 40, 20, 20, 26 }. Apparently, there is also { 60, 26, 20, 20, 26 }, but this looks different to what I've seen. - RCOMP resistors: { 200, 81, 162 }, or { 121, 75, 100 }, or { 121, 81, 100 } Board ID appears to be determined by PCD (essentially, UEFI global variables), so you should try dumping the PCD database with PcdGet from https://github.com/jyao1/EdkiiShellTool in a UEFI shell. By the way, according to the code you also may have an (unpopulated) SPD at 0x50 (0xA0 in the code, this is just because the SMBUS address was shifted 1 bit left into the 8-bit address form. They are equivalent). You also may need to set CaVrefConfig. "2" should be the correct value for DDR4. You should probably check that DqPinsInterleaved is correct, it's easiest if you can get this from the schematics. Best regards, Benjamin

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