April 2022 - coreboot - mail.coreboot.org

Intel Quark - a quick update
by Andy Pont July 20, 2022

July 20, 2022

Thanks to the generosity of members of the list there are two Intel Galileo boards, a Gen 1 and Gen 2, on their way to me which should arrive towards the end of the month. As soon as they get here I will start testing the various configs to see what works and what is broken. -Andy.

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[Proposal] Drop support for Ice lake [unmaintained]
by Tim Wawrzynczak May 30, 2022

May 30, 2022

Good day folks, In a recent change[0], it was proposed that we drop support for the Intel Ice Lake platform. The only mainboard supporting the platform was the Intel RVP, but as far as anyone knows, it appears the project never progressed past the initial silicon, and so the code is now unmaintained and also unused. Since Ice Lake is very similar to TGL & ADL, it poses a maintenance burden when dealing with Intel common code e.g., anything in src/soc/intel/common. According to [1], this should be announced in upcoming release notes first, and removal could happen in 6 months. Wondering if anyone has any thoughts on why we should keep it around, otherwise let's update the upcoming release notes to give the "official" notice that it will be dropped. Cheers, - Tim [0]https://review.coreboot.org/c/coreboot/+/60053 [1]https://doc.coreboot.org/releases/templates.html

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Another day, another SMM loader vulnerability
by Arthur Heymans May 23, 2022

May 23, 2022

Hi After last week's SMM loader problem on all but the BSP, I noticed another problem in the SMM setup. The permanent smihandler is currently built as a relocatable module such that coreboot can place it wherever it thinks it's a good idea. (TSEG is not known at buildtime). These relocatable modules have an alignment requirement. It looks however that the code to deal with the alignment requirement is also wrong and aligns the handler upwards instead of downwards which makes it encroach either an SSE2 FX_SAVE area or an SMM register save state. It's hard to know whether this is easily exploitable. I would think that a carefully crafted SMM save state on the right AP arbitrary code executing might be possible. On the other hand I noticed last week that launching SMM on APs is broken too so this is likely a lesser problem. Anyway the fix is in https://review.coreboot.org/c/coreboot/+/63475 (It has a comment indicating what code was causing this problem) Please review and update your coreboot code! Kind regards Arthur

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Open letter to Intel regarding the PSE on Elkhart Lake
by Zeh, Werner May 10, 2022

May 10, 2022

Dear coreboot community. I guess the most of you have seen the tension that was introduced to the community once Intel started to enable the Programmable Service Engine on the new IOTG SoC called Elkhart Lake (for reference, please see [1]). One of the outcome of this difficulties was to ask Intel for open sourcing the PSE code in order to avoid a new blob being introduced to coreboot. I took this action item and reached out to Intel in this regard. As a result I have had two meetings with the responsible people at Intel and they started to look into this request. So as of now Intel is analyzing the code to understand what needs to be done to open source it. What has been mentioned by Intel to me is that up to now nobody else have ever requested this for the PSE. Furthermore Intel let me know that it would be easier to convince the management layer to spend work on open sourcing the code if there would be more people from different companies requesting the same. My first guess was: we can do this! Therefore I have drafted up an open letter which I would like share with all of you: https://openletter.earth/request-for-opening-the-source-code-for-the-pse-on- elkhart-lake-26bad82a The wording have now been reviewed for two days between different parties and I would like to keep it as it is in order to get it done in time. This is now the moment where you can raise your voice! Please have a look at the open letter and sign it if you agree with the terms and if you support this approach. The more people we get the higher are our chances to be visible as an open source community. And it would be really helpful if we could get this letter signed by companies, this will for sure increase the traction of this request. I will keep this letter in "signing" state until 2021-12-09 07:00 am German time. Once we are there I will hand it over to Intel. Thank you for your support in advance Werner [1] <https://review.coreboot.org/c/coreboot/+/55367> https://review.coreboot.org/c/coreboot/+/55367

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Question about compressed FIT payloads
by Krystian Hebel May 2, 2022

May 2, 2022

Hello coreboot community, For our work on POWER9 coreboot port we were using Skiboot [1] packed into FIT payload. While it worked fine, we wanted to provide users with easier way of testing it on hardware. I believe it may be possible to modify only one of PNOR (fancy name for flash given by POWER people) partitions. In order to do this, we would have to fit whole CBFS into 512k (actually 1M including ECC, but that would require non-power-of-2 size), which should be doable with LTO and compressed payload. According to [2], whole file compression is not available for FIT payloads. I understand that this makes sense, thanks to this we can decompress/load individual parts of payload (e.g. kernel and initramfs) once, otherwise we would have to decompress it to read metadata first and then move code around in memory. However, FIT format doesn't hold information about uncompressed sizes of its components, required by decompressing functions in coreboot. Instead, their compressed sizes [3] are used to initialize output region sizes [4] and those are then passed to decompressors [5]. Only FDT has a workaround to this problem [6], and kernel's size is calculated in an arm64-specific way in [7]. On other architectures components (other than FDT) are partially decompressed until they run of of space, silently ignoring the rest. What should be "the proper way" of getting uncompressed size? I can think of the following options, listed in no particular order: 1. Extend hack used for FDT to other components, use it for all compressed parts. Arbitrary size multiplier may either waste some space potentially overlapping other component's memory range or not be enough in edge cases (e.g. mostly zeroed file). 2. For LZMA you may get decompressed size from the header, unfortunately this is not possible with LZ4. 3. Dry decompression just to check proper size - sounds too costly. 4. New properties for components' nodes in ITS file. May need changes in mkimage, haven't looked yet. Preferably shouldn't have to be manually written to ITS as that would be prone to error. While playing with mkimage, may add automatic compression, right now it expects already compressed files in ITS, although this can also be scripted. 5. Add more arch- and payload-specific parsing of images, as was done for arm64. This may require some kind of mark that a payload needs special handling (new CBFS attribute maybe?) 6. Enable whole file compression of FIT payloads, which results in juggling in RAM. 7. Mix of the above. For our current issue we can also load Skiboot from another PNOR partition (from where it is normally loaded by Hostboot [8] which we are basically substituting with coreboot) and manually create FDT for it. This would however break normal coreboot boot flow and we would like to avoid that. [1] https://github.com/open-power/skiboot [2] https://doc.coreboot.org/lib/payloads/fit.html#supported-compression [3] https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… [4] https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… [5] https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… [6] https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… [7] https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… [8] https://github.com/open-power/hostboot -- Krystian Hebel Firmware Engineer https://3mdeb.com | @3mdeb_com

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Security notice: SMM can be hijacked by the OS on APs
by Arthur Heymans April 28, 2022

April 28, 2022

Hi When refactoring the coreboot SMM setup I noticed that there is a security vulnerability in our SMM setup code. It boils down to this: except on the BSP the smihandler code will execute code at a random location, but most likely at offset 0. With some carefully crafted code a bootloader or the OS could place some code at that offset, generate an SMI on an AP and get control over SMM. More recent silicon has hardware mechanisms to avoid executing code outside the designated SMM area (TSEG) so those would not be affected. The commit introducing this problem is https://review.coreboot.org/c/coreboot/+/43684. Roughly it affects most x86 builds from end 2020/ beginning 2021 till now. https://review.coreboot.org/c/coreboot/+/63478 fixes the problem. (Feel free to review the rest of that series as it makes the smm setup much more readable ;-)) Kind regards Arthur

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2022-04-26 - coreboot UEFI working group meeting minutes
by coreboot org April 26, 2022

April 26, 2022

# 2022-04-26 - coreboot UEFI working group * Next meeting is 2022-05-24 * Meeting Minutes / Agenda Document: [1] ## Attendees * Martin, Jay, David, Nate ## Minutes Short meeting, few attendees and not much on the agenda. [Information] Here is an implementation of EFI support in rust, for cloud hypervisor. * [https://github.com/cloud-hypervisor/rust-hypervisor-firmware/tree/main/src/… * [https://github.com/cloud-hypervisor/rust-hypervisor-firmware/blob/main/src/… enumerates the services I guess they need. What’s the maintenance of the coreboot payload package? * They’re doing a lot of work, integrating the Universal Payload patches, but there may be a problem getting external patches reviewed. * They can reach out to martin at [gaumless@tutanota.com](mailto:gaumless@tutanota.com) What's the status of the patches being pushed to EDK2? * Unknown at this time. [1]:https://docs.google.com/document/d/13RjAddskjjCGhzIwxDTE1-w6HOIwhyoZsZUI…

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25 April 2022 Self Describing Blob Discussion
by coreboot org April 26, 2022

April 26, 2022

# 25 April 2022 Self Describing Blob Discussion * Next meeting: 2022-05-09 * Meeting minutes Doc [1] ## Attendees: Sheng, Jay Talbott, Martin Roth, Werner, Ron, Zhiguang, Dun.tan ## Minutes: Continue discussion over New UPL (Universal Payload) document. These are a list of proposed fields and not so much a discussion about the encoding right now. Currently, the only thing being discussed is the format for passing data from init firmware (coreboot/UEFI/U-Boot/ X) to a payload. Not all payloads will need all fields, and all fields are optional. If a field that a payload needs is not given, the expectation is that the receiver will do its best to continue. If a field is passed, it should be treated as the As mentioned in the last meeting, there are 2 levels in the definition: * Key * Subkey General Format for data structure - Maximum of two levels. Example: ``` | Key | Subkey | CBOR type | Native type | |---------|--------|-----------|--------------| | Example | | Integer | Unsigned int | ``` CBOR requires a different field type for positive and negative values, so all ints are explicitly signed. The oreboot mailing list is suggesting something more coreboot-tables like. * The tables can have issues if not using the same compiler version. CBOR is just a definition for serialized data - it should be read in by the recipient once and copied to memory to put into a native structure. With either CBOR or CBTables, the structure needs to be known by both the sender and the receiver. An open source library will be provided that may be used to encode/decode the data into structures. We need to try to get representatives from ARM, AMD, RISC-V present for future discussions. We need different viewpoints in this discussion so that it isn't Intel & x86-centric. Graphics has a number of fields to pass to the payload. If these are not present, the payload should assume that graphics has not been initialized. The Universal Payload spec will be released as a Google Doc shortly and will be open for comments. * The Spec needs definitions of all fields. Pointers to other documents where they are defined are fine. [1]: https://docs.google.com/document/d/1IDQqr4cv8dQHa9faSxBc29xHSeKuXNTiMP3a3bL…

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Request help and Support
by rainhenry＠savelife-tech.com April 26, 2022

April 26, 2022

Hello: I'm Rainhenry Wang from SAVELIFE Technology of Yunnan Co., LTD Company. We are currently developing a computer motherboard. Also want to use Coreboot to develop its BIOS firmware. It is based on Intel's Rocket Lake platform. The PCH model is FH82H510, and the spec code is SRKM2. However, I did not find Rocket Lake platform support code in all versions of Coreboot. So we want to understand and learn in detail how to add the code of another platform into Coreboot. I am not sure whether you have relevant learning resources or documents to share with us? Looking forward to your reply. Thank you very much. SAVELIFE® Technology of Yunnan Co., LTD 云南赛莱福科技有限公司王祥福 (Rainhenry Wang) Tel: +86-13104051251 (Voice calls only support Chinese) E-mail: rainhenry(a)savelife-tech.com

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[coreboot - Bug #351] test issue for mailing list
by Felix Singer April 25, 2022

April 25, 2022

Issue #351 has been updated by Felix Singer. test 2 ---------------------------------------- Bug #351: test issue for mailing list https://ticket.coreboot.org/issues/351#change-900 * Author: Felix Singer * Status: New * Priority: Normal * Target version: none * Start date: 2022-04-25 ---------------------------------------- Testing the mailing list bot for coreboot. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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No instructions for the Biostar AM1ML?
by Nicholas C. L. Ipsen April 25, 2022

April 25, 2022

Hi everyone, I recently managed to find a Biostar AM1ML, primarily purchasing it because I thought it would be a good board for a router with coreboot to make it 100% open source. However, even though the board is listed as supported, I can find no flashing instructions anywhere. Does anyone on this mailing list have experience flashing this board? I don't need anyone to hold my hand, but I would appreciate knowing what flashing method works, at least. Would hate to fry the chip. -- Nicholas C. L. Ipsen

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[RFC] i945 problematic code for IGD device enable, BUG?
by Petr Cvek April 25, 2022

April 25, 2022

Hello again :-D, I'm working on a code for a simultaneous use of IGD (GMA950) and x16 PCIe slot GPU. I've made some success, but the code which handles the IGD initialization is really weird. The IGD is initialized by DEVEN register (DEVEN_D2F0 and DEVEN_D2F1 bits), which is first written in i945_setup_pci_express_x16(). Few times before that the DEVEN_D2F0 and DEVEN_D2F1 bits are already tested during sdram_initialize() code. Also after the reset these bits are initialized to 1. This will cause the test from: https://elixir.bootlin.com/coreboot/4.16/source/src/northbridge/intel/i945/… if (!(pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))) integrated_graphics = false; to be effectively always -> if (0) also even when DEVEN_D2F0 is zeroed after chipset reset, the code located after a few lines: https://elixir.bootlin.com/coreboot/4.16/source/src/northbridge/intel/i945/… pci_or_config8(IGD_DEV, 0xc1, 1 << 2); will have a problem to work correctly. IGD_DEV is PCIe device enabled by DEVEN_D2F0 (setting DEVEN_D2F0 to 0 will remove IGD_DEV from the PCIe bus). It seems to not cause problems, but I didn't test it extensively. Also the test in northbridge_get_tseg_base() (used everytime top of the memory is needed): https://elixir.bootlin.com/coreboot/4.16/source/src/northbridge/intel/i945/… if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) /* IGD enabled, get top of Memory from BSM register */ tom = pci_read_config32(IGD_DEV, BSM); If only DEVEN_D2F1 is enabled, the test will succeed, but as the IGD_DEV is now disabled by DEVEN_D2F0 it will read garbage data for the global "top of the memory" value. I've sort of solved the missing initialization problem with CMOS config entry in mainboard_romstage_entry(): switch (get_uint_option("igd_en", 1)) { case 0: //disable pci_and_config32(HOST_BRIDGE, DEVEN, ~(DEVEN_D2F0 | DEVEN_D2F1)); break; case 2: //enable func0 only ??? TEST pci_update_config16(HOST_BRIDGE, DEVEN, ~(DEVEN_D2F1), DEVEN_D2F0); break; case 1: default: //enabled both pci_or_config32(HOST_BRIDGE, DEVEN, DEVEN_D2F0 | DEVEN_D2F1); break; } sdram_initialize( ... RFC: Is this approach OK? Of course the patch will need to cover the if (0) tests and skip access to missing PCI devices. Does anybody know if GCFC (Graphics Clock Frequency Control) register (i945 datasheet, section 8.1.35, page 296) needs to be explicitly disabled when IGD PCIe access is disabled by DEVEN bits or do I need to enable IGD PCIe access with DEVEN, disable clocks in GCFC and then disable IGD PCIe access again with DEVEN bits? Similar to GCFC settings without enabled IGD PCIe access. There are many registers in affected code, which doesn't have a name/description in the i945 datasheet. Does anybody know their function? It could help to determine if they needs to be set even when IGD will be disabled. Best regards, Petr

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Can coreboot run on a Dell Wyse 3290 or 3030?
by Martin Butt April 25, 2022

April 25, 2022

Hi, Thank you for your time helping me look into this. I have some Dell Wyse 3290 and 3030 thin clients. The firmware prevents booting into anything other than Windows Embedded Standard 7 from the internal SSD, so I'm investigating flashing the firmware with Coreboot to allow linux to be installed. Many of these were manufactured, and I'm hoping opening up the firmware can allow these to be upcycled into projects that SBCs are typically used for. Do you know if Coreboot would work on either of these systems? I've looked at the board and can't see a typical northbridge or southbridge. Here are some photos of the board to give you an idea: https://i.ebayimg.com/images/g/yxsAAOSwmTddSR2Y/s-l1600.jpg https://i.ebayimg.com/images/g/xIgAAOSw7ApdSR2Y/s-l1600.jpg Both the 3290 and the 3030 CPUs are a Intel Celeron N2807 1.58GHz From a visual inspection, the only difference between the boards of the two models is that the BIOS chip is different. The 3029 is a Winbond 25Q64FVSIG (or a 25Q64FWSIG, the chip is hard to read). The 3030 is a Macronix MX25U6435F. In case it is useful this page has some info on the hardware: https://www.parkytowers.me.uk/thin/wyse/3030/n03d.shtml *Output of "lspci -tvnn" (same on both boards)* -[0000:00]-+-00.0 Intel Corporation Atom Processor Z36xxx/Z37xxx Series SoC Transaction Register [8086:0f00] +-02.0 Intel Corporation Atom Processor Z36xxx/Z37xxx Series Graphics & Display [8086:0f31] +-13.0 Intel Corporation Atom Processor E3800 Series SATA AHCI Controller [8086:0f23] +-14.0 Intel Corporation Atom Processor Z36xxx/Z37xxx, Celeron N2000 Series USB xHCI [8086:0f35] +-1a.0 Intel Corporation Atom Processor Z36xxx/Z37xxx Series Trusted Execution Engine [8086:0f18] +-1b.0 Intel Corporation Atom Processor Z36xxx/Z37xxx Series High Definition Audio Controller [8086:0f04] +-1c.0-[01]----00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] +-1c.2-[02]-- +-1c.3-[03]-- +-1f.0 Intel Corporation Atom Processor Z36xxx/Z37xxx Series Power Control Unit [8086:0f1c] \-1f.3 Intel Corporation Atom Processor E3800 Series SMBus Controller [8086:0f12] *Output of "superiotool -dV" (same on both boards)* superiotool r4.16-623-g598ff42f12 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Aspeed Super I/O at 0x2e... Failed. Returned data: scratch registers all read as 0xff Probing for Aspeed Super I/O at 0x4e... Failed. Returned data: scratch registers all read as 0xff Probing for Exar Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Exar Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for VIA Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for VIA Super I/O (init=vt82c686) at 0x3f0... PCI device 1106:0686 not found. Probing for AMD EC Super I/O at 0xaa... Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff Probing for Infineon Super I/O at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for Infineon Super I/O at 0x4e... Failed. Returned data: id=0xff, rev=0xff No Super I/O found *Output of "flashrom -p internal -V" on 3290* flashrom v1.2 on Linux 5.13.0-30-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.6.4, GCC 9.2.1 20200304, little endian Command line (3 args): flashrom -p internal -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. DMI chassis-type is not specific enough. DMI string system-manufacturer: "WYSE" DMI string system-product-name: "Dell Wyse Thin Client Desktop 3290" DMI string system-version: "Rev 1" DMI string baseboard-manufacturer: "Inventec" DMI string baseboard-product-name: "Dell Wyse Thin Client Desktop 3290" DMI string baseboard-version: "A01" Found chipset "Intel Bay Trail" with PCI ID 8086:0f1c. Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc01: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap: not enabled 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI_BASE_ADDRESS = 0xfed01000 SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled 0x04: 0x6009 (HSFS) HSFS: FDONE=1, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... done 0x06: 0x0004 (HSFC) HSFC: FGO=0, FCYCLE=2, FDBC=0, SME=0 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0400 FREG1: BIOS region (0x00400000-0x007fffff) is read-write. 0x5C: 0x03ff0001 FREG2: Management Engine region (0x00001000-0x003fffff) is read-write. 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf94010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=1 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9c: 0xc79f0190 (OPMENU+4) 0xc4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xd0: 0x00000000 (FPB) OK. The following protocols are supported: SPI. Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25LQ032/A25LQ32A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for AMIC A25LQ64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DF021A, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DL081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DL161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25F1024(A), 128 kB: probe_spi_at25f: id1 0x60, id2 0x60 Probing for Atmel AT25F2048, 256 kB: probe_spi_at25f: id1 0x60, id2 0x60 Probing for Atmel AT25F4096, 512 kB: probe_spi_at25f: id1 0x60, id2 0x60 Probing for Atmel AT25F512, 64 kB: probe_spi_at25f: id1 0x60, id2 0x60 Probing for Atmel AT25F512A, 64 kB: probe_spi_at25f: id1 0x60, id2 0x60 Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25SF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25SF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25SF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25SF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT25SL128A, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT45DB321E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ESI ES25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ESI ES25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ESI ES25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ESMT F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ESMT F25L32PA, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25P05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25P10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25QH128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25QH64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25S32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25S64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon EN25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25B128B/GD25Q128B, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25LQ128C/GD25LQ128D, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25LQ40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25LQ64(B), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25LQ80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25Q10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25Q127C/GD25Q128C, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25Q16(B), 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25Q20(B), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25Q256D, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25Q32(B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25Q512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25Q64(B), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25Q80(B), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25T80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25VQ16C, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25VQ21B, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25VQ40C, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25VQ41B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for GigaDevice GD25VQ80C, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ISSI IS25LP064, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ISSI IS25LP128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ISSI IS25LP256, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ISSI IS25WP032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ISSI IS25WP064, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ISSI IS25WP128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ISSI IS25WP256, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX23L12854, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX23L1654, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX23L3254, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX23L6454, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L1005(C)/MX25L1006E, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L12805D, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L12835F/MX25L12845E/MX25L12865E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L1605A/MX25L1606E/MX25L1608E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L1605D/MX25L1608D/MX25L1673E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L2005(C)/MX25L2006E, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L25635F/MX25L25645G, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L3206E/MX25L3208E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L3273E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L4005(A/C)/MX25L4006E, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L512(E)/MX25V512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L6405D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L6406E/MX25L6408E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L6495F, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25L8005/MX25L8006E/MX25L8008E/MX25V8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25R6435F, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25U12835F, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25U1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25U25635F, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25U3235E/F, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25U51245G, 65536 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25U6435E/F, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX25U8032E, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix MX66L51235F/MX25L51245G, 65536 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25P20-old, 256 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M25PX80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M45PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M45PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M45PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M45PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST M45PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q00A..1G, 131072 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q00A..3G, 131072 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q128..1E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q128..3E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q256..1E, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q256..3E, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q512..1G, 65536 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron/Numonyx/ST N25Q512..3G, 65536 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron MT25QL01G, 131072 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron MT25QU01G, 131072 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron MT25QL02G, 262144 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron MT25QU02G, 262144 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron MT25QU128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron MT25QL128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron MT25QL256, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron MT25QU256, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron MT25QL512, 65536 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Micron MT25QU512, 65536 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Nantronics N25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Nantronics N25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Nantronics N25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Nantronics N25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Nantronics N25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LD010(C), 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LD020(C), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LD040(C), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LD256C, 32 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LD512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LQ016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LQ020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LQ032C, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LQ040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LQ080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LV010, 128 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for PMC Pm25LV010A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC Pm25LV512(A), 64 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for SST SST25LF020A, 256 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for SST SST25LF080(A), 1024 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for SST SST25VF010(A), 128 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25VF020, 256 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF020B, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25VF512(A), 64 kB: probe_spi_rems: id1 0xef, id2 0x16 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25WF020A, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25WF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25WF080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25WF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST26VF016B(A), 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST26VF032B(A), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST SST26VF064B(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ST M95M02, 256 kB: probe_spi_st95: id1 0xff, id2 0xffff Probing for Sanyo LE25FU106B, 128 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FU206, 256 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FU206A, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Sanyo LE25FU406B, 512 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FU406C/LE25U40CMC, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Sanyo LE25FW106, 128 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FW203A, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Sanyo LE25FW403A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Sanyo LE25FW406A, 512 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FW418A, 512 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FW806, 1024 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Sanyo LE25FW808, 1024 kB: probe_spi_res2: id1 0x16, id2 0x16 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL116K/S25FL216K, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL127S-256kB, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL127S-64kB, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL128P......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL128P......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL128S......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL128S......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL129P......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL129P......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL132K, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL164K, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL204K, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL208K, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL256S......0, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Spansion S25FL512S, 65536 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q128.V, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q128.V..M, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q128.W, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q128.JW.DTR, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q16.V, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q16.W, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q20.W, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q256.V, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q256JV_M, 32768 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q32.V, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q32.W, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q40.V, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q40BW, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q40EW, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q64.V, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q64.W, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Found Winbond flash chip "W25Q64.W" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Chip status register is 0x00. Probing for Winbond W25Q80.V, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q80BW, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25Q80EW, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Zetta Device ZD25D20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Zetta Device ZD25D40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Unknown SFDP-capable chip, 0 kB: No SFDP signature found. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x6017 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xef, id2 0x16 Found Winbond flash chip "W25Q64.W" (8192 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). No operations were specified. Restoring MMIO space at 0x7f3f199cd09c Restoring MMIO space at 0x7f3f199cd098 Restoring MMIO space at 0x7f3f199cd096 Restoring MMIO space at 0x7f3f199cd094 *Output of "flashrom -p internal -V" on the 3030* flashrom v1.2 on Linux 5.13.0-30-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.6.4, GCC 9.2.1 20200304, little endian Command line (3 args): flashrom -p internal -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. No DMI table found. Found chipset "Intel Bay Trail" with PCI ID 8086:0f1c. Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc01: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap: not enabled 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI_BASE_ADDRESS = 0xfed01000 SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled 0x04: 0x6009 (HSFS) HSFS: FDONE=1, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=0 Programming OPCODES... done 0x06: 0x0004 (HSFC) HSFC: FGO=0, FCYCLE=2, FDBC=0, SME=0 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0400 FREG1: BIOS region (0x00400000-0x007fffff) is read-write. 0x5C: 0x03ff0001 FREG2: Management Engine region (0x00001000-0x003fffff) is read-write. 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf94010 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=1 0x94: 0x5006 (PREOP) 0x96: 0x463b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9c: 0xc79f0190 (OPMENU+4) 0xc4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xd0: 0x00000000 (FPB) OK. The following protocols are supported: SPI. Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25LQ032/A25LQ32A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for AMIC A25LQ64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DF021A, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DL081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DL161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25F1024(A), 128 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F2048, 256 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F4096, 512 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512A, 64 kB: probe_spi_at25f: id1 0xff, id2 0xff Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25SF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25SF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25SF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25SF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT25SL128A, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT45DB321E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ESI ES25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ESI ES25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ESI ES25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ESMT F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ESMT F25L32PA, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25P05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25P10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25QH128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25QH64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25S10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25S16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25S20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25S32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25S40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25S64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon EN25S80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25B128B/GD25Q128B, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25LQ128C/GD25LQ128D, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25LQ40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25LQ64(B), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25LQ80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25Q10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25Q127C/GD25Q128C, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25Q16(B), 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25Q20(B), 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25Q256D, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25Q32(B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25Q512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25Q64(B), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25Q80(B), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25T80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25VQ16C, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25VQ21B, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25VQ40C, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25VQ41B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for GigaDevice GD25VQ80C, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ISSI IS25LP064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ISSI IS25LP128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ISSI IS25LP256, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ISSI IS25WP032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ISSI IS25WP064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ISSI IS25WP128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ISSI IS25WP256, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX23L12854, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX23L1654, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX23L3254, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX23L6454, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L1005(C)/MX25L1006E, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L12805D, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L12835F/MX25L12845E/MX25L12865E, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L1605A/MX25L1606E/MX25L1608E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L1605D/MX25L1608D/MX25L1673E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L2005(C)/MX25L2006E, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L25635F/MX25L25645G, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L3206E/MX25L3208E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L3273E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L4005(A/C)/MX25L4006E, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L512(E)/MX25V512(C), 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L6405D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L6406E/MX25L6408E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L6495F, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25L8005/MX25L8006E/MX25L8008E/MX25V8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25R6435F, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25U12835F, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25U1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25U25635F, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25U3235E/F, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25U51245G, 65536 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX25U6435E/F, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Found Macronix flash chip "MX25U6435E/F" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Probing for Macronix MX25U8032E, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix MX66L51235F/MX25L51245G, 65536 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25P20-old, 256 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M25PX80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M45PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M45PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M45PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M45PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST M45PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q00A..1G, 131072 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q00A..3G, 131072 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q128..1E, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q128..3E, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q256..1E, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q256..3E, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q512..1G, 65536 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron/Numonyx/ST N25Q512..3G, 65536 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron MT25QL01G, 131072 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron MT25QU01G, 131072 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron MT25QL02G, 262144 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron MT25QU02G, 262144 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron MT25QU128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron MT25QL128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron MT25QL256, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron MT25QU256, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron MT25QL512, 65536 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Micron MT25QU512, 65536 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Nantronics N25S10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Nantronics N25S16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Nantronics N25S20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Nantronics N25S40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Nantronics N25S80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LD010(C), 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LD020(C), 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LD040(C), 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LD256C, 32 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LD512(C), 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LQ016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LQ020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LQ032C, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LQ040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LQ080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LV010, 128 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for PMC Pm25LV010A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC Pm25LV512(A), 64 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for SST SST25LF020A, 256 kB: probe_spi_rems: id1 0xc2, id2 0x37 Probing for SST SST25LF040A, 512 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for SST SST25LF080(A), 1024 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for SST SST25VF010(A), 128 kB: probe_spi_rems: id1 0xc2, id2 0x37 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25VF020, 256 kB: probe_spi_rems: id1 0xc2, id2 0x37 Probing for SST SST25VF020B, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25VF040, 512 kB: probe_spi_rems: id1 0xc2, id2 0x37 Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25VF040B.REMS, 512 kB: probe_spi_rems: id1 0xc2, id2 0x37 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25VF512(A), 64 kB: probe_spi_rems: id1 0xc2, id2 0x37 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25WF020A, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25WF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25WF080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25WF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST26VF016B(A), 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST26VF032B(A), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST SST26VF064B(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ST M95M02, 256 kB: probe_spi_st95: id1 0xff, id2 0xffff Probing for Sanyo LE25FU106B, 128 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for Sanyo LE25FU206, 256 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for Sanyo LE25FU206A, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Sanyo LE25FU406B, 512 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for Sanyo LE25FU406C/LE25U40CMC, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Sanyo LE25FW106, 128 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for Sanyo LE25FW203A, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Sanyo LE25FW403A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Sanyo LE25FW406A, 512 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for Sanyo LE25FW418A, 512 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for Sanyo LE25FW806, 1024 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for Sanyo LE25FW808, 1024 kB: probe_spi_res2: id1 0x37, id2 0x37 Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL116K/S25FL216K, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL127S-256kB, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL127S-64kB, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL128P......0, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL128P......1, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL128S......0, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL128S......1, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL129P......0, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL129P......1, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL132K, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL164K, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL204K, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL208K, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL256S......0, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Spansion S25FL512S, 65536 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q128.V, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q128.V..M, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q128.W, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q128.JW.DTR, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q16.V, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q16.W, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q20.W, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q256.V, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q256JV_M, 32768 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q32.V, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q32.W, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q40.V, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q40BW, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q40EW, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q64.V, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q64.W, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q80.V, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q80BW, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25Q80EW, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Zetta Device ZD25D20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Zetta Device ZD25D40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Unknown SFDP-capable chip, 0 kB: Parsing JEDEC flash parameter table... done. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2537 Probing for Generic unknown SPI chip (REMS), 0 kB: probe_spi_rems: id1 0xc2, id2 0x37 Found Macronix flash chip "MX25U6435E/F" (8192 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). No operations were specified. Restoring MMIO space at 0x7fae453a309c Restoring MMIO space at 0x7fae453a3098 Restoring MMIO space at 0x7fae453a3096 Restoring MMIO space at 0x7fae453a3094 *Output of "dmidecode" on 3290* # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 2.7 present. 34 structures occupying 1517 bytes. Table at 0x000E0840. Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: Phoenix Technologies Ltd. Version: 1.0R Release Date: 12/22/2017 Address: 0xE0000 Runtime Size: 128 kB ROM Size: 4096 kB Characteristics: PCI is supported BIOS is upgradeable BIOS shadowing is allowed Boot from CD is supported Selectable boot is supported EDD is supported Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) NEC PC-98 ACPI is supported USB legacy is supported BIOS boot specification is supported Function key-initiated network boot is supported Targeted content distribution is supported UEFI is supported BIOS Revision: 0.1 Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: WYSE Product Name: Dell Wyse Thin Client Desktop 3290 Version: Rev 1 Serial Number: 640A9CHRV72 UUID: 0b0623a2-0218-2016-ee9a-008064ecc5e7 Wake-up Type: Power Switch SKU Number: Null Family: Dell Wyse Thin Client Desktop 3000 series Handle 0x0002, DMI type 2, 15 bytes Base Board Information Manufacturer: Inventec Product Name: Dell Wyse Thin Client Desktop 3290 Version: A01 Serial Number: 1 Asset Tag: Base Board Asset Tag Unknown Features: Board is a hosting board Board is replaceable Location In Chassis: Chassis Location Unknown Chassis Handle: 0x0000 Type: Motherboard Contained Object Handles: 0 Handle 0x0003, DMI type 3, 22 bytes Chassis Information Manufacturer: Inventec Type: Space-saving Lock: Not Present Version: A Serial Number: None Asset Tag: None Boot-up State: Unknown Power Supply State: Unknown Thermal State: Unknown Security Status: Unknown OEM Information: 0x00000000 Height: Unspecified Number Of Power Cords: 1 Contained Elements: 0 SKU Number: Not Specified Handle 0x0004, DMI type 4, 42 bytes Processor Information Socket Designation: CPU 1 Type: Central Processor Family: Atom Manufacturer: Intel(R) Corporation ID: 78 06 03 00 FF FB EB BF Signature: Type 0, Family 6, Model 55, Stepping 8 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) APIC (On-chip APIC hardware supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) CLFSH (CLFLUSH instruction supported) DS (Debug store) ACPI (ACPI supported) MMX (MMX technology supported) FXSR (FXSAVE and FXSTOR instructions supported) SSE (Streaming SIMD extensions) SSE2 (Streaming SIMD extensions 2) SS (Self-snoop) HTT (Multi-threading) TM (Thermal monitor supported) PBE (Pending break enabled) Version: Intel(R) Celeron(R) CPU N2807 @ 1.58GHz Voltage: 0.7 V External Clock: 83 MHz Max Speed: 4000 MHz Current Speed: 1592 MHz Status: Populated, Enabled Upgrade: None L1 Cache Handle: 0x0006 L2 Cache Handle: 0x0007 L3 Cache Handle: Not Provided Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified Core Count: 2 Core Enabled: 2 Thread Count: 1 Characteristics: 64-bit capable Multi-Core Execute Protection Enhanced Virtualization Power/Performance Control Handle 0x0005, DMI type 7, 19 bytes Cache Information Socket Designation: L1 Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 24 kB Maximum Size: 24 kB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Single-bit ECC System Type: Data Associativity: Fully Associative Handle 0x0006, DMI type 7, 19 bytes Cache Information Socket Designation: L1 Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 32 kB Maximum Size: 32 kB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Single-bit ECC System Type: Instruction Associativity: 8-way Set-associative Handle 0x0007, DMI type 7, 19 bytes Cache Information Socket Designation: L2 Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: Internal Installed Size: 1024 kB Maximum Size: 1024 kB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: 16-way Set-associative Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1500 Internal Connector Type: None External Reference Designator: USB 3.0 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1501 Internal Connector Type: None External Reference Designator: USB 3.0 From Panel HDR External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1502 Internal Connector Type: None External Reference Designator: USB 1/2 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x0010, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1504 Internal Connector Type: None External Reference Designator: USB 3/4 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x0011, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: SATA Port 1 J8J1 Internal Connector Type: SAS/SATA Plug Receptacle External Reference Designator: None External Connector Type: None Port Type: SATA Handle 0x0012, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: SATA Port 2 J7G1 Internal Connector Type: SAS/SATA Plug Receptacle External Reference Designator: None External Connector Type: None Port Type: SATA Handle 0x0013, DMI type 9, 17 bytes System Slot Information Designation: MINI PCIE 1 Type: x1 PCI Express Current Usage: Available Length: Short ID: 2 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Bus Address: 0000:00:00.0 Handle 0x0014, DMI type 10, 6 bytes On Board Device Information Type: Video Status: Enabled Description: Intel(R) Extreme Graphics 3 Controller Handle 0x0015, DMI type 10, 6 bytes On Board Device Information Type: Sound Status: Enabled Description: AZALIA HD Audio Handle 0x0016, DMI type 10, 6 bytes On Board Device Information Type: Ethernet Status: Enabled Description: Realtek RTL8111E-VL Handle 0x0017, DMI type 10, 6 bytes On Board Device Information Type: <OUT OF SPEC> Status: Disabled Description: Infineon TPM SLB9635 Handle 0x0018, DMI type 11, 5 bytes OEM Strings String 1: Dell Wyse Thin Client Desktop 3000 series String 2: www.dell.com String 3: DMI-R1 String 4: 008064ECC5E7 String 5: 01010B2E String 6: 0021 String 7: 640A9CHRV72 String 8: 0011 String 9: 14[4] Handle 0x0019, DMI type 12, 5 bytes System Configuration Options Handle 0x001A, DMI type 13, 22 bytes BIOS Language Information Language Description Format: Abbreviated Installable Languages: 6 en-US fr-FR ja-JP ko-KR zh-CHT zh-CHS Currently Installed Language: en-US Handle 0x0021, DMI type 15, 31 bytes System Event Log Area Length: 3970 bytes Header Start Offset: 0x0000 Header Length: 16 bytes Data Start Offset: 0x0010 Access Method: General-purpose non-volatile data functions Access Address: 0x00F0 Status: Valid, Full Change Token: 0x000000F7 Header Format: Type 1 Supported Log Type Descriptors: 4 Descriptor 1: POST error Data Format 1: POST results bitmap Descriptor 2: PCI system error Data Format 2: None Descriptor 3: System reconfigured Data Format 3: None Descriptor 4: Log area reset/cleared Data Format 4: None Handle 0x0008, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 4 GB Error Information Handle: Not Provided Number Of Devices: 2 Handle 0x0009, DMI type 17, 34 bytes Memory Device Array Handle: 0x0008 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: DIMM0 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1333 MT/s Manufacturer: 17 Serial Number: 02112387 Asset Tag: Unknown Part Number: HMT451S6BFR8A-PB Rank: Unknown Configured Memory Speed: 1333 MT/s Handle 0x000B, DMI type 17, 34 bytes Memory Device Array Handle: 0x0008 Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: SODIMM Set: None Locator: DIMM1 Bank Locator: BANK 1 Type: Unknown Type Detail: None Speed: Unknown Manufacturer: Not Specified Serial Number: Not Specified Asset Tag: Unknown Part Number: Not Specified Rank: Unknown Configured Memory Speed: Unknown Handle 0x000C, DMI type 19, 31 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Array Handle: 0x0008 Partition Width: 2 Handle 0x000A, DMI type 20, 35 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x0009 Memory Array Mapped Address Handle: 0x000C Partition Row Position: Unknown Handle 0x001B, DMI type 22, 26 bytes Portable Battery Location: Rear Manufacturer: Intel Corp. Manufacture Date: 2010 Serial Number: 1.0 Name: Smart Battery Design Capacity: Unknown Design Voltage: Unknown SBDS Version: V1.0 Maximum Error: Unknown SBDS Chemistry: Lithium-Ion OEM-specific Information: 0x00000000 Handle 0x0020, DMI type 24, 5 bytes Hardware Security Power-On Password Status: Disabled Keyboard Password Status: Not Implemented Administrator Password Status: Disabled Front Panel Reset Status: Not Implemented Handle 0x001D, DMI type 27, 23 bytes Cooling Device Temperature Probe Handle: 0x6800 Type: <OUT OF SPEC> Status: <OUT OF SPEC> OEM-specific Information: 0x80000000 Nominal Speed: 0 rpm Description: Not Specified Handle 0x001E, DMI type 28, 22 bytes Temperature Probe Description: Rear Location: Processor Status: OK Maximum Value: Unknown Minimum Value: Unknown Resolution: Unknown Tolerance: Unknown Accuracy: Unknown OEM-specific Information: 0x00000000 Nominal Value: Unknown Handle 0x001F, DMI type 32, 11 bytes System Boot Information Status: No errors detected Handle 0xFEFF, DMI type 127, 4 bytes End Of Table *Output of "dmidecode" in 3030 (yes, it still reports itself as a 3029)* # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 2.7 present. 34 structures occupying 1517 bytes. Table at 0xB94AE000. Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: Phoenix Technologies Ltd. Version: 1.0R Release Date: 12/22/2017 Address: 0xE0000 Runtime Size: 128 kB ROM Size: 4096 kB Characteristics: PCI is supported BIOS is upgradeable BIOS shadowing is allowed Boot from CD is supported Selectable boot is supported NEC PC-98 ACPI is supported USB legacy is supported BIOS boot specification is supported Function key-initiated network boot is supported Targeted content distribution is supported UEFI is supported BIOS Revision: 0.1 Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: WYSE Product Name: Dell Wyse Thin Client Desktop 3290 Version: Rev 1 Serial Number: 5PDDO900701 UUID: 000033a2-011f-2014-ee9a-008064f829e7 Wake-up Type: Power Switch SKU Number: Null Family: Dell Wyse Thin Client Desktop 3000 series Handle 0x0002, DMI type 2, 15 bytes Base Board Information Manufacturer: Inventec Product Name: Dell Wyse Thin Client Desktop 3290 Version: A01 Serial Number: 1 Asset Tag: Base Board Asset Tag Unknown Features: Board is a hosting board Board is replaceable Location In Chassis: Chassis Location Unknown Chassis Handle: 0x0000 Type: Motherboard Contained Object Handles: 0 Handle 0x0003, DMI type 3, 22 bytes Chassis Information Manufacturer: Inventec Type: Space-saving Lock: Not Present Version: A Serial Number: None Asset Tag: None Boot-up State: Unknown Power Supply State: Unknown Thermal State: Unknown Security Status: Unknown OEM Information: 0x00000000 Height: Unspecified Number Of Power Cords: 1 Contained Elements: 0 SKU Number: Not Specified Handle 0x0004, DMI type 4, 42 bytes Processor Information Socket Designation: CPU 1 Type: Central Processor Family: Atom Manufacturer: Intel(R) Corporation ID: 78 06 03 00 FF FB EB BF Signature: Type 0, Family 6, Model 55, Stepping 8 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) APIC (On-chip APIC hardware supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) CLFSH (CLFLUSH instruction supported) DS (Debug store) ACPI (ACPI supported) MMX (MMX technology supported) FXSR (FXSAVE and FXSTOR instructions supported) SSE (Streaming SIMD extensions) SSE2 (Streaming SIMD extensions 2) SS (Self-snoop) HTT (Multi-threading) TM (Thermal monitor supported) PBE (Pending break enabled) Version: Intel(R) Celeron(R) CPU N2807 @ 1.58GHz Voltage: 0.7 V External Clock: 83 MHz Max Speed: 4000 MHz Current Speed: 1589 MHz Status: Populated, Enabled Upgrade: None L1 Cache Handle: 0x0006 L2 Cache Handle: 0x0007 L3 Cache Handle: Not Provided Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified Core Count: 2 Core Enabled: 2 Thread Count: 1 Characteristics: 64-bit capable Multi-Core Execute Protection Enhanced Virtualization Power/Performance Control Handle 0x0005, DMI type 7, 19 bytes Cache Information Socket Designation: L1 Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 24 kB Maximum Size: 24 kB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Single-bit ECC System Type: Data Associativity: Fully Associative Handle 0x0006, DMI type 7, 19 bytes Cache Information Socket Designation: L1 Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 32 kB Maximum Size: 32 kB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Single-bit ECC System Type: Instruction Associativity: 8-way Set-associative Handle 0x0007, DMI type 7, 19 bytes Cache Information Socket Designation: L2 Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: Internal Installed Size: 1024 kB Maximum Size: 1024 kB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: 16-way Set-associative Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1500 Internal Connector Type: None External Reference Designator: USB 3.0 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000E, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1501 Internal Connector Type: None External Reference Designator: USB 3.0 From Panel HDR External Connector Type: Access Bus (USB) Port Type: USB Handle 0x000F, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1502 Internal Connector Type: None External Reference Designator: USB 1/2 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x0010, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: J1504 Internal Connector Type: None External Reference Designator: USB 3/4 External Connector Type: Access Bus (USB) Port Type: USB Handle 0x0011, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: SATA Port 1 J8J1 Internal Connector Type: SAS/SATA Plug Receptacle External Reference Designator: None External Connector Type: None Port Type: SATA Handle 0x0012, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: SATA Port 2 J7G1 Internal Connector Type: SAS/SATA Plug Receptacle External Reference Designator: None External Connector Type: None Port Type: SATA Handle 0x0013, DMI type 9, 17 bytes System Slot Information Designation: MINI PCIE 1 Type: x1 PCI Express Current Usage: Available Length: Short ID: 2 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Bus Address: 0000:00:00.0 Handle 0x0014, DMI type 10, 6 bytes On Board Device Information Type: Video Status: Enabled Description: Intel(R) Extreme Graphics 3 Controller Handle 0x0015, DMI type 10, 6 bytes On Board Device Information Type: Sound Status: Enabled Description: AZALIA HD Audio Handle 0x0016, DMI type 10, 6 bytes On Board Device Information Type: Ethernet Status: Enabled Description: Realtek RTL8111E-VL Handle 0x0017, DMI type 10, 6 bytes On Board Device Information Type: <OUT OF SPEC> Status: Disabled Description: Infineon TPM SLB9635 Handle 0x0018, DMI type 11, 5 bytes OEM Strings String 1: Dell Wyse Thin Client Desktop 3000 series String 2: www.dell.com String 3: DMI-R1 String 4: 008064F829E7 String 5: 01010B2E String 6: 0021 String 7: 5PDDO900701 String 8: 0011 String 9: 14[4] Handle 0x0019, DMI type 12, 5 bytes System Configuration Options Handle 0x001A, DMI type 13, 22 bytes BIOS Language Information Language Description Format: Abbreviated Installable Languages: 6 en-US fr-FR ja-JP ko-KR zh-CHT zh-CHS Currently Installed Language: en-US Handle 0x0021, DMI type 15, 31 bytes System Event Log Area Length: 3970 bytes Header Start Offset: 0x0000 Header Length: 16 bytes Data Start Offset: 0x0010 Access Method: General-purpose non-volatile data functions Access Address: 0x00F0 Status: Valid, Full Change Token: 0x000000F7 Header Format: Type 1 Supported Log Type Descriptors: 4 Descriptor 1: POST error Data Format 1: POST results bitmap Descriptor 2: PCI system error Data Format 2: None Descriptor 3: System reconfigured Data Format 3: None Descriptor 4: Log area reset/cleared Data Format 4: None Handle 0x0008, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 4 GB Error Information Handle: Not Provided Number Of Devices: 2 Handle 0x0009, DMI type 17, 34 bytes Memory Device Array Handle: 0x0008 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: DIMM0 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1333 MT/s Manufacturer: 17 Serial Number: 16115119 Asset Tag: Unknown Part Number: HMT451S6BFR8A-PB Rank: Unknown Configured Memory Speed: 1333 MT/s Handle 0x000B, DMI type 17, 34 bytes Memory Device Array Handle: 0x0008 Error Information Handle: Not Provided Total Width: Unknown Data Width: Unknown Size: No Module Installed Form Factor: SODIMM Set: None Locator: DIMM1 Bank Locator: BANK 1 Type: Unknown Type Detail: None Speed: Unknown Manufacturer: Not Specified Serial Number: Not Specified Asset Tag: Unknown Part Number: Not Specified Rank: Unknown Configured Memory Speed: Unknown Handle 0x000C, DMI type 19, 31 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Array Handle: 0x0008 Partition Width: 2 Handle 0x000A, DMI type 20, 35 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x000FFFFFFFF Range Size: 4 GB Physical Device Handle: 0x0009 Memory Array Mapped Address Handle: 0x000C Partition Row Position: Unknown Handle 0x001B, DMI type 22, 26 bytes Portable Battery Location: Rear Manufacturer: Intel Corp. Manufacture Date: 2010 Serial Number: 1.0 Name: Smart Battery Design Capacity: Unknown Design Voltage: Unknown SBDS Version: V1.0 Maximum Error: Unknown SBDS Chemistry: Lithium-Ion OEM-specific Information: 0x00000000 Handle 0x0020, DMI type 24, 5 bytes Hardware Security Power-On Password Status: Disabled Keyboard Password Status: Not Implemented Administrator Password Status: Disabled Front Panel Reset Status: Not Implemented Handle 0x001D, DMI type 27, 23 bytes Cooling Device Temperature Probe Handle: 0x6800 Type: <OUT OF SPEC> Status: <OUT OF SPEC> OEM-specific Information: 0x80000000 Nominal Speed: 0 rpm Description: Not Specified Handle 0x001E, DMI type 28, 22 bytes Temperature Probe Description: Rear Location: Processor Status: OK Maximum Value: Unknown Minimum Value: Unknown Resolution: Unknown Tolerance: Unknown Accuracy: Unknown OEM-specific Information: 0x00000000 Nominal Value: Unknown Handle 0x001F, DMI type 32, 11 bytes System Boot Information Status: No errors detected Handle 0xFEFF, DMI type 127, 4 bytes End Of Table Again, many thanks for your time, Martin

3 2

[BUG] nb/intel/i945: smm_subregion() prints assert when it should not
by Petr Cvek April 25, 2022

April 25, 2022

Hello, On i945 northbridge: ASSERTION ERROR: file 'src/cpu/x86/smm/tseg_region.c', line 31 can be triggered by some configurations. The assert ASSERT(IS_ALIGNED(sub_base, sub_size)); tests alignment of SMM base with SMM size. The problem is that IGD stolen memory can offset the SMM base by a smaller size than the SMM size. This causes SMM base to be unaligned. For example: 80000000: 2 GiB Top of RAM, stored in TOLUD 7ff00000: 1 MiB Stolen IGD RAM base, address in BSM 7fd00000: 2 MiB SMM base, defined as SMM size in ESMRAMC -> 0x7fd00000 is not aligned to SMM size. Probably works for different settings too. RFC: should the assert from https://elixir.bootlin.com/coreboot/4.16/source/src/cpu/x86/smm/tseg_region… be removed, changed or ignored on i945? The correct test should be probably for 1 MiB alignement as the base of stolen IGD memory have [31:20] bits. But I understand the smm_subregion() test is a generic one. regards, Petr

2 6

Deprecation of the Intel Quark SoC
by Felix Singer April 24, 2022

April 24, 2022

Hi all, to me it seems like the Intel Quark SoC has been unmaintained and unused for a long time now. So I'm proposing to deprecate the support for it with coreboot release 4.17 [1], in order to drop the support with release 4.19 so that the community has less maintenance overhead. Does anyone use this platform? Any opinions against this? // Felix [1] https://review.coreboot.org/c/coreboot/+/63283

15 55

PS/2 connected state and ACPI + BUG(s)
by Petr Cvek April 24, 2022

April 24, 2022

Hi, Observing ACPI on my new ryzen machine it seems its UEFI can generate the state of PS/2 mouse and keyboard accordingly to which one of them is connected or disconnected. I was trying to add something like that to my Core 2 Duo testing setup, but it seems there is no easy way how to export information of used PS/2 port. It seems the status (_STA) is defined at the compilation time. This means the linux autodetection can have a problem if one PS/2 device is not plugged when defined. If the export is possible it should be probably done inside src/drivers/pc80/pc/keyboard.c am I correct? Also slightly related bugs: Having CONFIG_DRIVERS_PS2_KEYBOARD enabled and while holding a key (for example escape) during a reset. The keyboard gets stuck in seabios, payloads (nvramcui) and bootloader until linux kernel resets it. Disabling CONFIG_DRIVERS_PS2_KEYBOARD fixes it. I can add the warning in the kconfig help description if this is just limited to a specific board configuration and it is not bug. Having CONFIG_DRIVERS_PS2_KEYBOARD disabled, but having PS/2 keyboard and generic USB mouse connected will cause nvramcui to not respond until the USB mouse is disconnected. This is probably problem with SeaBIOS, but it would be useful to have some confirmation. P.S. I'm not an expert in ACPI, I learned most of it just from .asl source files from coreboot. regards, Petr

1 0

[RFC] i945 RAM init failure
by Petr Cvek April 24, 2022

April 24, 2022

Hi, My board Kontron 986lcd-m (i945) sometimes fails in quick_ram_check_or_die() with RAM INIT FAILURE! The failure occurs in about 33% of reboots. RAM modules are fine (multiple memtest checks over the years), used RAM modules are rated with a reserve (DDR2-800 compatible modules and i945 supports up to DDR2-667). If the check will not fail the system will be long term stable. The checked memory is in the valid RAM (below top of the ram, below stolen IGD memory, below SMM region). If I force the checked word to not be the last 32b word (ex. 0x7fbffffc) but to be aligned to 256 bytes (ex. 0x7fbfff00) the test didn't fail even during multiple reset spamming. During the failed test the tested word looks like this (modification for printing the tested 32bit word): [DEBUG] ===FAIL1 5555b2ef //test for 0x5555555 [DEBUG] ===FAIL2 aaaab2aa //test for 0xaaaaaaa [DEBUG] ===FAIL3 0000b2ef //test for 0x0000000 [DEBUG] ===FAIL4 ffffb2ef //test for 0xfffffff At least the top half of the read_phys() value seems to be valid over subsequent reads (for loop). RFC: Could this be some problem with cache initialization, DDR2 controller impedance settings, or something else? Does anybody with i945 board or directly with 986lcd-m have the same problem? Regards, Petr

1 0

Re: Deprecation of the Intel Quark SoC
by Martin Roth April 23, 2022

April 23, 2022

Here's a list for coreboot. https://review.coreboot.org/c/coreboot/+/63797 Martin Apr 22, 2022, 18:46 by rminnich(a)gmail.com: > oh oops the person doing that misunderstood me, we'll have to fix it > > On Fri, Apr 22, 2022 at 5:41 PM Martin Roth <gaumless(a)tutanota.com> wrote: > >> >> Hey Ron, >> I think this is a good plan. We can make a markdown file doing the same. I'm not sure that coreboot wants to record where it's deleted, but instead the branch where it would be maintained. >> This is the solution I was talking about in the coreboot leadership meeting: >> https://review.coreboot.org/c/coreboot/+/63754 >> >> Take care. >> Martin >> Apr 22, 2022, 17:24 by rminnich(a)gmail.com: >> >> > The discussion here has been pretty helpful to my thinking. I think >> > the concerns people are raising are important. >> > >> > We are deprecating ALL boards on oreboot that need FSP, as we took the >> > decision a few weeks ago to drop boards >> > that require blobs on the main CPU (we're accepting PSP blobs for now) >> > >> > This leaves two x86 boards behind, not counting qemu. >> > >> > But, based on what has come up here, we decided we did not want to >> > leave all memory of old efforts behind. >> > >> > This is the result: https://github.com/oreboot/oreboot/pull/570/files >> > >> > Not sure if this would be desired for coreboot, but I am mentioning it >> > here for reference. >> > >> > Thanks >> > >> > ron >> > >> > On Mon, Apr 18, 2022 at 11:05 AM Sam Kuper <sam.kuper(a)uclmail.net> wrote: >> > >> >> >> >> (I'm not a Coreboot dev/maintainer, so apologies for commenting from the >> >> peanut gallery...) >> >> >> >> >> >> On Mon, Apr 18, 2022 at 04:32:36AM +0200, Martin Roth wrote: >> >> > [...] >> >> > 2) Decide on a set of criteria that we can use to evaluate whether or >> >> > not things should be removed from the master branch and maintained on >> >> > a release branch. >> >> >> >> Makes sense. >> >> >> >> >> >> > Currently, the only reason we have specified that a platform will be >> >> > moved to a release branch is if it's hindering progress. Basically if >> >> > it's not using an API we want to mark a required, or using code that >> >> > is being deprecated. >> >> > >> >> > If hindering progress is the only reason that something should ever be >> >> > removed from the master branch, I'm fine with that. Let's decide that >> >> > and document it so we don't have to have this discussion in the >> >> > future. >> >> >> >> Surely there will sometimes be platforms/chips that, for good reason, >> >> the community wants to keep in master - even if this would mean rewrites >> >> for those platforms/chips re the two matters you mentioned above: >> >> >> >> a. not using APIs that future versions of coreboot will require; >> >> >> >> b. using code that is being deprecated? >> >> >> >> >> >> Such "good reasons" could include that the plaform/chip: >> >> >> >> 1. is in widespread use with coreboot, even if long out of production >> >> (e.g. certain server boards or Thinkpad models); or >> >> >> >> 2. is targeted by related projects (e.g. Heads) that coreboot >> >> developers would prefer to avoid unnecessarily inconveniencing; or >> >> >> >> 3. has active coreboot testers/maintainers able to integrate relevant >> >> updates, and is passing all significant CI tests. >> >> >> >> >> >> > Other options we could look at: >> >> > >> >> > - A platform has not been sold in X years. >> >> > >> >> > - A chip has not been produced for X years. >> >> >> >> I can see the appeal of these criteria: they are easy to define. >> >> However, they are probably not wise criteria, as they may conflict with >> >> one or more of the "good reasons" above, especially reason 1. >> >> >> >> >> >> > - A platform has not been tested in X years. >> >> > >> >> > - A platform hasn't had an active maintainer for X years. (Maybe the >> >> > maintainer should be asked to test a platform as well?) >> >> >> >> These seem much better criteria. >> >> >> >> To make them easier to apply, should coreboot comprehensively track, for >> >> platforms/chips (roughly as Debian does for packages): >> >> >> >> - the current maintainer(s) for that platform/chip, >> >> >> >> - the current tester(s) for that platform/chip, >> >> >> >> - when that platform/chip was last tested, and >> >> >> >> - what the test results were? >> >> >> >> I think coreboot already tracks some of this data via >> >> https://lava.9esec.io or https://qa.coreboot.org/ - I'm not certain. >> >> >> >> That being so, I propose some draft policy wording (please >> >> change/improve...): >> >> >> >> "For any given platform or chip that has ever been targeted by the >> >> coreboot project: >> >> >> >> - For each coreboot "version" (point release, master, or >> >> hardware-specific branch): >> >> >> >> - if the platform/chip has been tested on that version, but >> >> the test was unsuccessful, the platform/chip shall be >> >> labelled *broken* re that version; else >> >> >> >> - if the test was successful, the platform/chip shall be >> >> labelled *working* re that version; else >> >> >> >> - the platform/chip shall be labelled *untested* re that >> >> version. >> >> >> >> - If the platform/chip has known security vulnerabilities on that >> >> version, the shall be labelled *vulnerable* re that version. >> >> >> >> - If the platform/chip has a person/team assigned to test/maintain >> >> it re master, it shall be labelled *maintained*, unless it has >> >> been *vulnerable*, *broken*, or *untested* re master for at >> >> least 6 months in which case it shall be labelled >> >> *unmaintained*, >> >> >> >> - If a platform/chip has been labelled *unmaintained* for at least >> >> 6 months, a branch shall be created for it, from the last >> >> coreboot point-release for which it was tested and found to be >> >> working. Such a platform/chip shall be labelled *relegated*. >> >> >> >> - A person/team who merges subsequent updates from master into >> >> such a branch, such that the branch becomes acceptable to the >> >> gatekeepers of master for merging back into master, and who also >> >> successfully tests the relegated platform/chip on the resulting >> >> codebase, and who volunteers to maintain that platform/chip for >> >> the foreseeable future, may become that platform/chip's >> >> maintainer, and upon the relevant changes being merged into >> >> master, the platform/chip shall no longer be labelled >> >> *relegated* but instead shall be labelled *tested* and >> >> *maintained*." >> >> >> >> >> >> > Thanks everyone [...] I'm not trying to argue with anyone, just >> >> > looking to get an actual decision of some sort out of this thread. >> >> >> >> Ditto! >> >> >> >> Sam >> >> _______________________________________________ >> >> coreboot mailing list -- coreboot(a)coreboot.org >> >> To unsubscribe send an email to coreboot-leave(a)coreboot.org >> >> >> > _______________________________________________ >> > coreboot mailing list -- coreboot(a)coreboot.org >> > To unsubscribe send an email to coreboot-leave(a)coreboot.org >> > >> > _______________________________________________ > coreboot mailing list -- coreboot(a)coreboot.org > To unsubscribe send an email to coreboot-leave(a)coreboot.org >

2 1

2022-04-20 - coreboot Leadership meeting minutes
by coreboot org April 23, 2022

April 23, 2022

# 2022-04-20 - coreboot Leadership Next meeting: 2022-05-04 ## Attendees: Jay, Martin, Felix, Christian, Piotr, Tim, Ron, Arthur, Julius, Felix Held, David, Stefan, Paul, Patrick ## Decisions * Martin will write up a document about when platforms would be moved to a branch: Basically only when it hinders progress, not because it's untested. * Martin will do an example of Kconfig where the platforms have been removed keep the mainboard names in the tree. When selected, it will show the branch where the platform is maintained. We can also include the last known good commit for current mainboards. * Patrick will look at adding the security mailing list to the page at [http://mail.coreboot.org](http://mail.coreboot.org) * Felix Singer will investigate adding better user authentication to our redmine server. ## Minutes ### [Felix S] The German government wants to fund open source projects. More information will follow next year 2022. [1] * I did some research and asked around, since I didn’t hear anything. The German government agreed on this funding last year, but their presented household finance plan (~22th March) doesn’t contain anything for open source. The final finance plan will likely be decided this summer. Until then it’s possible to change that. * Official statement from OKFN (only german) [2] * Alternative funding projects are the [Prototype Fund](https://prototypefund.de/en/) and the [Hardware Prototype Fund](https://hardware.prototypefund.de/en/), but they are expecting you to invent something new and all participants of a group should have their residents in Germany. Prototype fund is going until 2024. 5 or 6 projects are accepted every 6 months, and a project can get up to 50,000 euros. * Something “new” would have to be added to coreboot. * Hardware prototype fund is similar, but more specific to hardware. * [Piotr] [Technology Common Trust Open Firmware Fund](https://technologycommons.org/OFF/) in cryptocurrency. 50k Euros. Mostly for EU citizens, but have funded north american projects in the past as well. * What do we want to do with these funds? * Do the people working on the project get the funds? * Do we just put these up on the website as a way to help get coreboot projects funded if someone wants to do something? ### [Martin] Moving platforms to a stable branch. * What are the requirements? * I think (roughly) everyone agrees that platforms can be moved to a release branch if they’re blocking forward progress. * Is this the ONLY reason things should be removed? * Felix H, Paul: yes * Martin will write up something about this and push it to documentation to review. * David: We discussed before that platforms would be removed if it hasn’t been tested. * Give a release cycle or two to have it tested and remove it if it doesn’t get tested in that 6 months. * Boards that are moving to a stable/release branch are announced in the release notes prior to being moved, so there is time to update/test a target if a developer wishes to keep it in main. * Put the last known working version in the Kconfig. * Paul: Need to avoid having too many branches. ChromeOS, for example, has hundreds of branches that are difficult to understand. Security patches would need to be ported to many branches. * Ron: Everyone acts like leaving an unused target in the tree has no cost, and that’s not true. * There are other costs than just the jenkins builds. * FelixS many of us use freetime to do the maintenance, and this could be better used. * Can we make a requirement going forward that all mainboards must have maintainers and can we require that the mainboards be tested by the maintainer? Does this place too much of a burden on people contributing mainboards? * Julius: This may be a bit extreme. If we remove things that haven’t been tested in the last 6 monts this will remove most of the tree. * Martin: Can chromeos test all of their boards. * Answer: Not really. * Julius, David: There is an advantage to maintaining old mainboards that keep us away from focusing on specific architectures. * Also, people interested in porting coreboot to a board will look for examples. This could be some random embedded single board computer, or an experimental work done for a new architecture (POWER9 work based on POWER8 work?). * Ron: Keep old code in the tree, but stop building it. Then it can be used as a reference. ### [dhendrix] Make GCC the official compiler of coreboot? [3] * This is basically simply continuing what we're doing now, but making it formal instead of an unwritten rule. * Julius: Just because some extensions are allowed (like dollar signs in names), we don’t need to allow them. * [Martin]Should coreboot follow the linux kernel’s lead and look to switch to -std=gcc11 [4]? * The makefile is already specifying gcc11, so no change is needed here. We should document it somewhere though. ### [Martin] Proposal for handling platforms moved to a stable branch to make them easier to use: * Add all those mainboards back into the Kconfig in ToT, just with the branch name that they’re being maintained in and which host compiler is needed. * Offer to check out that branch if desired. * Branches are already being built by jenkins, so patches can be pushed directly to the 4.11, 12, 14, 15, and 4.16 branches. * Update buildgcc on those branches to pull the tools from the coreboot download site instead of the original sites. * Martin will implement and post for review. ### [Martin (Arthur)] SMM security fixes [5] * Backport to 4.14, 15, & 4.16 branches. * Martin will do releases of the branches after the fixes are in. * Should this have gone to the security mailing list instead of the general mailing list? * Probably. Arthur looked for the security mailing list, but didn't find it. * Add to the mailman interface page? Is this possible? * Patrick will look at this. ### [Martin(Arthur)] Deprecate lb_serial uart_pci_addr field [6] * How does this help us? * It removes ugly code. * We’d still want to keep the field in the structure so that a payload that uses it doesn’t misinterpret the field. * Make this field reserved. ### [Jay]: Martin, any sign of the ITRenew server? * No, still no signs of it. :-( ### [Martin] New page at coreboot website: Help the coreboot project. * Add small projects * Add requests for testing. * Make it easier to test things. * FelixH: Build an image, post coreboot output & dmesg output and have this parsed and added to the test list. * Replacement for board status. * Don’t need to check out the 2GB git repo. * Paul will take a look at how to download less. * Script doesn’t always work. * Felix s: Add a control server that allows distributed testing of mainboards for people. * Need to be some sort of authentication mechanism for pushing - git serves this purpose. * David: Make a branch that can be checked out. * Martin has a script that will remove old versions. ### [FelixH] Can we add oauth authorization to redmine? * FelixS: There’s a plugin, but it’s not officially supported. * FelixH: is there a bugtracker that better integrates with gerrit? * FelixS: we can look, but redmine has the best interface in my opinion, and it is very customizable. * FelixH: Not suggesting switching, but it's a hassle to use separate credentials. [1]: https://sovereigntechfund.de/en [2]: https://okfn.de/blog/2022/03/stf-offener-brief/ [3]: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/3C2… [4]: https://www.phoronix.com/scan.php?page=news_item&px=Linux-5.18-C11-Plan [5]: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/PAT6… [6]: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/RYKU… # Notice Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting.

4 3

Get Coreboot version and build details in linux.
by Putsala Amar April 23, 2022

April 23, 2022

Hi, We are working on intel c508 intel denverton board. We have programmed coreboot image in 16MB NOR flash. How can i get the coreboot version and build time stamp details in linux user mode? Does it creates any sys/proc entry? Thanks in advance.., Thanks & Regards, Amar Putsala ( ID : 2353 ) 4th Floor , Cubical : 4058 J.P. Software Park, Electronic City Phase-1, Hosur Road, 560100 Ext. No: 8110

2 1

2022-03-29 - coreboot UEFI working group meeting minutes
by coreboot org April 23, 2022

April 23, 2022

# 2022-03-29 - coreboot UEFI working group Next meeting: 2022-04-26 ## Attendees: Jay, Werner, Martin, Sheng, Ron, David ## Minutes: * In the coreboot meeting last week, we discussed a proposal from Intel to change the handoff mechanism to payloads [1]. After that discussion, the decision was made to move further discussion of that topic over to the UEFI working group meeting. There was another meeting on Monday, March 28th where we got a much better understanding of what’s going on and the reasons behind the proposal. * Intel wants to look at modifying the payload handoff as a part of their universal-scalable-firmware [2] initiative. * The current payload handoff method has a number of flaws that they’d like to fix, such as the address for stack being hardcoded. * This likely also gives coreboot an opportunity to address other parts of the USF spec that cause issues or incompatibilities for us. * The coreboot project got involved when Sheng suggested to Intel that it would be good to align the payload-handoff format with other projects such as coreboot. * Thanks Sheng! * Using CBOR is the current proposal, but Intel was open to discussing different formats than CBOR if anyone has a better suggestion. * If anyone is not familiar with CBOR, you can get more information at cbor.io [3]. * In the coreboot meeting, it was suggested that we push to just use coreboot tables as they’re already supported in a number of payloads. This really isn’t practical however. Intel would need to be able to modify the list of known cbmem IDs and they would need to be able to change the description format to something that’s more self-describing. * The coreboot project can, however, encapsulate a CBOR-based handoff-structure into cbmem, similar to what we currently do with ACPI tables. * Additionally Intel was willing to look at using CBOR structures as input and output to the FSP, so we could get rid of both the UPDs & HOBs. * The coreboot community can help to drive this, and Intel has said that they will send an email to the coreboot mailing list. * Since this is a part of the Universal-Scalable-Firmware initiative, it would be good to look that over for issues as well. Currently, it’s very Intel oriented, and specifies that the FSP will be used as the silicon initialization layer, which obviously doesn’t work for non-x86 platforms. * The details for the weekly meeting are below. * Self Describing Blob discussion. A copy of this meeting has been added to the coreboot calendar [4]. Biweekly on Monday, 4:00 – 5:00pm CET/CEST Berlin (Currently UTC+2) Video call link: https://meet.google.com/gha-shza-wnw Or dial: ‪(DE) +49 30 300195187‬ PIN: ‪848 847 031‬# More phone numbers: https://tel.meet/gha-shza-wnw?pin=2380921555764 Self Describing Blob discussion Meeting minutes [5]. * Sean Rhodes from StarLabs has worked to get all of the coreboot related EDK2 patches submitted to their repo. These are still currently in review. [1]: https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK… [2]: https://universalscalablefirmware.github.io/documentation/ [3]: https://cbor.io/ [4]: https://calendar.google.com/event?action=TEMPLATE&tmeid=NHVvZDRuYXZ2bjdtZTJ… [5]: https://docs.google.com/document/d/1IDQqr4cv8dQHa9faSxBc29xHSeKuXNTiMP3a3bL…

6 13

Flashing EC is getting failed
by Sameeruddin Shaik April 23, 2022

April 23, 2022

hi, I am getting the below error while flashing the EC image with the micro servo, Did anyone know about this?. sudo ./util/flash_ec --board=adlrvpp_ite --image build/adlrvpp_ite/ec.bin INFO: Using servo_micro. INFO: Using ec image : build/adlrvpp_ite/ec.bin INFO: Flashing chip it83xx. INFO: Asking servo to send the dbgr special waveform to it83xx 2022-04-02 11:38:29,203 - Controls - ERROR - (ptyError) Failed getting enable_ite_dfu: servo_micro: Timeout waiting for response. There was output: enable_ite_dfu, Command 'enable_ite_dfu' not found or ambiguous., > Problem with ['enable_ite_dfu'] :: servo_micro: Timeout waiting for response. There was output: enable_ite_dfu, Command 'enable_ite_dfu' not found or ambiguous., > ERROR: command exited 1 (non-zero): dut-control enable_ite_dfu INFO: Restoring servo settings... Please help!!!, thanks in advance --sameer

1 1

Two Payloads
by Lukas Jungbauer April 21, 2022

April 21, 2022

Hi, is it possible to run two Payloads on Coreboot at the same Time, like Heads and TianoCore? Payloads can only be installed by building a new Image and Software-Flashing it, correct? Best Regards, Lukas

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Coreboot : Change/modify Boot maintenance manager for auto boot support.
by Putsala Amar April 21, 2022

April 21, 2022

Hi, We are working on intel c508 intel denverton board. We have programmed coreboot image in 16MB NOR flash. After the coreboot hw initialization , it moves to payload stage by default it is entering to "boot maintenance manager" . We expect the node to boot without getting into boot manager(without waiting for any key) . Made below experiment which i found in BIOS : Change/Modify Auto Boot Time-out option as "0" in "Boot Maintenance manager". but this timeout parameter is not allow to commit/save the new changes. As per the Auto Boot Time-out description : Range: 0 means no wait , 65535 means waiting for Key. By default timeout hold 65535. Thanks in advance.., Thanks & Regards, Amar Putsala ( ID : 2353 ) 4th Floor , Cubical : 4058 J.P. Software Park, Electronic City Phase-1, Hosur Road, 560100 Ext. No: 8110

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RFC: Clarifying use of GCC extensions in the coding style
by Julius Werner April 18, 2022

April 18, 2022

Hi, We occasionally get into discussions in code reviews when code uses a GCC extension, and a reviewer asks that it be rewritten to be C standard compliant instead. A recent example was on the use of `void *` arithmetic in this patch https://review.coreboot.org/c/coreboot/+/56791/9/src/soc/mediatek/common/pc… , and there have been others in the past. I would like to come to a consensus on this topic here and add some blurb to the coding style document so we don't have to rehash the same discussion over and over again. In my opinion, GCC extensions are absolutely necessary for coreboot development and there should be no reason to reject them. Inline assembly is the most obvious example -- without it we would have to convert a ton of static inline functions that wrap special instructions into full linker-level functions in a separate assembly file instead, and eat all the unnecessary function call overhead that comes with that. Others enable such important features that it would become much more dangerous and cumbersome to develop without them -- most importantly statement expressions (https://gcc.gnu.org/onlinedocs/gcc-11.2.0/gcc/Statement-Exprs.html) which are necessary to write things like double-evaluation safe macros, expression-assertions like dead_code_t() and simple convenience shortcuts like wait_us(). And some extensions just offer a small bit of convenience to reduce boilerplate -- for example, `void *` arithmetic just tends to be useful to prevent cluttering the code with a bunch of unnecessary casts to other types that don't add any additional meaning to the data (e.g. for an unspecified buffer of opaque data I think `void *` is a much more appropriate type than `uint8_t *`, even if I want to add a byte offset to it), and I've never seen a case where I think it would have actually been unclear to anyone what step width the pointer arithmetic was done at (there's no reason to assume anything other than bytewise for a `void *`). If we need some extensions anyway, and coreboot will never be "fully C standards compliant" (not that that would actually be very useful for anything in practice), I don't see a reason why we should still avoid some extensions when we're using others. I think if an (official, long-term supported) extension exists and it allows us to write better code than standard C, there should be no reason not to use it. (Note that for those people who are trying to get coreboot working with clang, it generally supports all the same extensions as GCC.) I've written a draft CL to add a section for this to the coding style, please let me know what you think: https://review.coreboot.org/c/coreboot/+/63660

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lb_serial: drop 'uart_pci_addr' entry
by Arthur Heymans April 17, 2022

April 17, 2022

Hi In 2016 'uart_pci_addr' was added to the coreboot table entry for serial devices. (https://review.coreboot.org/c/coreboot/+/14609) It was done for the Intel Quark platform which has its uart on a PCI device like other Intel hardware. Right now only Quark sets this to a non zero value using an awkwardly defined Kconfig parameter: CONFIG_UART_PCI_ADDR. It looks like only tianocore uses this and it's pretty much a NOOP used only to get the VID/DID of the PCI device. Should we update tianocore and just drop this for the lb_table? Most other payloads don't even have this struct entry updated to contain this entry... Now our codebase has awkward code with "serial.uart_pci_addr = CONFIG_UART_PCI_ADDR;" on a lot of platforms that don't even feature PCI and there is no real use case as far as I can tell. Do any of your payloads use this in a meaningful way? If not, can we just drop it? Kind regards Arthur

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review.coreboot.org 's wget is working unreliable today
by Mike Banon April 17, 2022

April 17, 2022

Downloading the patches by wget from review.coreboot.org - really often results in these errors today. my Internet connection is OK and I'm able to load review.coreboot.org at the same time with a browser. --2022-04-17 **:**:**-- https://review.coreboot.org/changes/58748/revisions/1/patch?zip Loaded CA certificate '/etc/ssl/certs/ca-certificates.crt' Resolving review.coreboot.org (review.coreboot.org) 78.46.105.101, 2a01:4f8:121:1254::2 Connecting to review.coreboot.org (review.coreboot.org)|78.46.105.101|:443... failed: Connection timed out. Connecting to review.coreboot.org (review.coreboot.org)|2a01:4f8:121:1254::2|:443... failed: Network is unreachable. WARNING: can't download a ./patch?zip file ! Please check your Internet connection and try again. press [ENTER] to continue... -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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Re: Deprecation of the Intel Quark SoC
by Martin Roth April 14, 2022

April 14, 2022

Apr 14, 2022, 14:06 by 0xloem(a)gmail.com: > Hi Martin, > >> I think we all agree that it'd be good to have test racks that have all of the boards in the coreboot repository for verification, however that's currently not practical with the resources we have. The whole thing just isn't a simple problem to solve. >> > > Often the biggest impediment to something like this is simply holding it as a shared goal, and continuing to do so when issues arise. > > If public test labs were desired, a callout for donations of space and hardware could be placed on the main page. If somebody had the capacity to do more than that, then local makerspaces and hackerspaces could be reached out to. > It's a good point. Maybe we can put up a webpage with how an individual can help the coreboot project. Put up a list of boards to be adopted for testing and how to find which commit broke them if they're broken. >> I'm actually also not completely convinced that just testing the boards is the solution to whether or not we keep a board/chip on the mastre branch. If there really aren't any people using coreboot on their quark boards, then personally, I don't see any need to keep it in the master branch. I know others feel differently, but as I said earlier in this thread, I don't think there's actually any harm in moving an aging or little-used platform to be maintained on a branch. >> > > Sounds like there is a difference of opinion in the community. > Always. ;-) > It seems obvious to me that there would be people using coreboot on their quark boards. The world is gigantic. > > But you have a different opinion, which is fine. > > It seems to me the reason to include a board is because people care about doing so. > Agreed. Currently we have no way of knowing whether or not anyone cares about a board. There are two ways people typically make it known - by working on a board or by testing a board. > I care enough about including boards that I'd test this one if it was needed to do so to retain it. But I'm just a visitor. And it seems more productive to discuss public test labs that could grow to support more boards. > Sure, and I'm not trying to advocate that we remove anything. Mostly right now I'm trying to figure out how we should decide when things should or should not be moved to a branch to make it easier going forward. Take care Martin

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libpayload CBFS API deprecation; please port payloads to new API
by Julius Werner April 14, 2022

April 14, 2022

The libpayload CBFS stack ("libcbfs") has recently been rewritten from scratch in order to eliminate a bunch of very old warts and better match the new CBFS API in coreboot (https://review.coreboot.org/59497) For the time being, the old libcbfs code remains side-by-side to the new one so that the old API functions still work for existing payloads. However, we would like to remove this code eventually as it still presents a maintenance burden. All payloads that use the CBFS API in libpayload should please upgrade to the new API. Among the payloads hooked up to the coreboot build system, I think this only affects depthcharge (we already ported that one), BOOTBOOT and FILO. See https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/pa… for available interfaces (they match the coreboot API which is documented in more detail in https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr…) If you have a use case that cannot be implemented with this interface please let me know. If there are no objections I'd suggest that we target the official deprecation and removal of the old API for the release after next, i.e. 4.18 around the end of this year.

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Fwd: Refactoring duplicate Embedded Controller code
by Ivan Ivanov April 13, 2022

April 13, 2022

G505S has KB9012 chip on board, I can guarantee this. However, maybe KB9012 is a bit similar to the older chips, and just the internal 128KB memory and some features got added. If you'd look at KB9012 dataset available online, I think it had a comparison table of KB9012 vs some older chip. Hope this helps! пт, 8 апр. 2022 г., 16:46 Abel Briggs <abelbriggs1(a)hotmail.com>: > Yes, I was looking at the G505S and its EC when considering these patches. > > The situation with the EC in the G505S seems a bit odd. The EC is named > `ene932`, but there are several commits in the codebase which reference the > chip as a KB9012. The KB9012 datasheet, however, reference the ENE930 > series chips as the predecessor chip to the KB9010 series. > > The S230U has a KB9012 and the Compal firmware seems to have a similar > `OperationRegion` layout to the firmware in the `ene932`, but the EC query > values are completely different. The S230U basically defines its own EC in > its mainboard tree and only uses the `ene932` code for its helper I/O space > functions. > > If anyone has a G505S or its vendor documentation to check that the chip > on the board is really an ENE930 series, I think that would help clear this > up. > > This is something I was considering trying to refactor as well, by giving > the S230U its own `ec/` common code. However, I would probably throw that > patch in with my mainboard's patchset (Lenovo Edge E530), since otherwise > the S230U would be the only user of that code. > > ------------------------------ > *From:* Ivan Ivanov <qmastery16(a)gmail.com> > *Sent:* Friday, April 8, 2022, 4:38 AM > *To:* Abel Briggs <abelbriggs1(a)hotmail.com> > *Cc:* coreboot(a)coreboot.org <coreboot(a)coreboot.org> > *Subject:* Re: [coreboot] Refactoring duplicate Embedded Controller code > > If this could help you, coreboot-supported Lenovo G505S also has EC KB9012 > > чт, 7 апр. 2022 г. в 06:44, Abel Briggs <abelbriggs1(a)hotmail.com>: > > > > Hello, > > > > I was looking at the code and ACPI for a number of different embedded > > controllers while adding support for a Lenovo mainboard. > > The mainboard in question has an EC nearly identical to the Twist S230U > > (Compal KB9012), so I planned to factor out the S230U's EC code/ACPI > > into its own chip. > > > > While doing this, I noticed there were several duplicate functions > > across the `ec/` directory, so I'd like to potentially submit some > > patches to clean them up. However, I'm not sure of the best way to > > go about this. > > > > The following is what I currently have in mind: > > > > - Removing most individual `ec_write_cmd()` > > and similar functions andreplacing calls with their respective > `ec/acpi/ec.c` library functions > > - Removing individual `kbc_` polling functions and sharing the ones > defined > > in `drivers/pc80/keyboard.c` > > - Should public library functions for sending and receiving data from > > a PC80 keyboard controller be defined in the PC80 driver and exported > > in `include/pc80/keyboard.h`? > > - We already have `send_keyboard()` there, > > which sends a command and receives data - would it be good to add > > individual functions for those operations as well? > > > > Any suggestions or recommendations would be appreciated. I looked for > > guidelines on suggested code organization in the docs/commit history/ > > mailing list, but came up mostly empty-handed. > > > > Thanks! > > > > _______________________________________________ > > coreboot mailing list -- coreboot(a)coreboot.org > > To unsubscribe send an email to coreboot-leave(a)coreboot.org > >

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regarding support for W25Q256JW (0x6019)
by ritul guru April 12, 2022

April 12, 2022

Hi, I am looking for info to add WINBOND SPI FLASH part W25Q256JW (0x6019). tried adding below entry in winbond.c, is there any other changes required to enable this part to boot from? { /* W25Q256JW */ .id[0] = 0x6019, .nr_sectors_shift = 13, .fast_read_dual_output_support = 1, .fast_read_dual_io_support = 1, .protection_granularity_shift = 16, .bp_bits = 4, }, *Thanks & RegardsRitul Guru+91-9916513186*

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[Issue Tracker] Security notification
by Issue Tracker April 12, 2022

April 12, 2022

Email coreboot(a)coreboot.org was removed. https://ticket.coreboot.org/my/account User: flx IP address: 185.104.142.213 Date: 04/12/2022 12:55 AM -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot][GSoC] idea for a proposal project porting to a Thinkpad AMD Ryzen 3rd gen machine
by Lahfa Samy April 10, 2022

April 10, 2022

Hi all Coreboot folks, I'm a first year graduate student in CS, been hanging around on #coreboot IRC (Libera.Chat server) and was thinking if it was possible or not to port Coreboot to a Thinkpad T495 (AMD Ryzen 7 3700U PRO) [1] manufactured in May 2019, I successfully dumped the BIOS using flashrom internally, see `flashrom_info.log` and 'flashrom_info.err.log`. It is unclear if there is any AMD protection that does the same as Intel BootGuard on Ryzen 3rd gen (there is for sure this [2] since the 1st gen of Ryzen which is the equivalent to Intel Management Engine). AMD has a whitepaper stating that from Ryzen 5000s mobile generation [3], AMD PSB (Platform Secure Boot) is activated, and it looks like kind of the same as Intel BootGuard if I'm not mistaken here. I know so far that the BIOS SPI chip is operating at 1.8v, and is a Winbond flash chip "W25Q128.W" (16384 kB, SPI), will be useful in case I need to externally flash the SPI ROM to unbrick the laptop. I still have to : - Test whether there is a protection that checks if the firmware was changed or not by patching the original bios ROM, I was told for this to change a copyright string or changing the logo : - it is a gif file and has a sha2-256 signature in its properties, which isn't the sha256sum of the file. - I've attached the `identify -verbose logo.gif` output) and trying to boot could allow checking for any tamper protection on the ROM flash (bricking intentionally the device if there is). - Understand if the EC RAM is something I can make out of or not (so far there is a lot of FF and 00 in it, the last line shows the version of the embedded firmware), so far I'm not too sure I can make sense of it right now. - Get the model of the EC and try to find datasheets online. I have at my disposal: - A kind of cheap 16 channel logic analyzer [4] with a software available on Linux/Windows with a few decoders for most known serial protocols such as SMBUS, I2C, SPI and more. - Raspberry Pi 3 model B+ (will be used as an external programmer, but I still need to find out how I could pull down the power to 1.8v since the VCC is 3.3v). - SOIC clip 8 pins (will be delivered to me in 2 weeks), I took the best one from this guide [5]. - A cheap multimeter with basic probes, capable of continuity test. And possibly more such as FPGAs by going to hackerspaces in my vicinity. I have built Coreboot for qemu with the Seabios payload as the documentation for GSoC recommended, see coreboot-serial.log output attached as a text file. In the case where there is indeed a protection, maybe a solution could be found by using a flash emulator (spispy ?) [6] but I need more details on this. I am also aware that a complete port will not be feasible under the time period of GSoC hence I need to know what should be the basics that needs to be covered for a Coreboot port to be considered minimally working first ? USB should work ? Charging is made using a USB-C port, this might be partly handled by the EC Embedded Controller. Finally, if nothing could be done on this Thinkpad because it is too recent, I also have an older Intel Thinkpad a T450, that has Intel BootGuard but that I'm looking try to port Coreboot to it too, using a flash emulator and possibly this attack [7]. Thanks for the time taken to read this lengthy mail, I hope the goal of this mail is clear. Kind regards, Lahfa Samy Links: ------ [1] https://psref.lenovo.com/syspool/Sys/PDF/ThinkPad/ThinkPad_T495/ThinkPad_T4… [2] https://en.wikipedia.org/wiki/AMD_Platform_Security_Processor [3] https://www.amd.com/system/files/documents/amd-security-white-paper.pdf [4] https://sigrok.org/wiki/Kingst_LA2016 [5] http://dangerousprototypes.com/docs/Flashing_a_BIOS_chip_with_Bus_Pirate [6] https://github.com/osresearch/spispy [7] https://trmm.net/Sleep_attack/

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ThinkPad T420 and FireWire chip on Linux
by Alesandar Metodiev April 9, 2022

April 9, 2022

Hello, Recently I have decided to give a try to coreboot for first time and flashed my ThinkPad T420, but a few weeks ago I have swapped the USB controller on the back, next to the battery, with a FireWire/USB controller (40GAB5809-G200) from another T420. Nothing special, since some models have been shipped like this. The controller is no longer accessible on my laptop. It seems like it may have been detected as an "SD Host Controller" or not detected at all. I will probably have to remove the chip and compare the output of lspci and lshw. If nothing has changed, I will probably have to return the stock BIOS and compare the results again. I have also tried to load some of the firewire kernel modules manually with modprobe. The operating systems I have tested so far are Arch Linux and Xubuntu. I am willing to provide more useful information, boot into a fresh Windows install, flash the chip again or whatever else. Correct me if I am wrong, but if I go back to the stock BIOS, the next time I flash, I will have to disassemble the laptop again and otherwise I must be fine with flashing internally, right? Thanks

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Refactoring duplicate Embedded Controller code
by Abel Briggs April 8, 2022

April 8, 2022

Hello, I was looking at the code and ACPI for a number of different embedded controllers while adding support for a Lenovo mainboard. The mainboard in question has an EC nearly identical to the Twist S230U (Compal KB9012), so I planned to factor out the S230U's EC code/ACPI into its own chip. While doing this, I noticed there were several duplicate functions across the `ec/` directory, so I'd like to potentially submit some patches to clean them up. However, I'm not sure of the best way to go about this. The following is what I currently have in mind: - Removing most individual `ec_write_cmd()` and similar functions andreplacing calls with their respective `ec/acpi/ec.c` library functions - Removing individual `kbc_` polling functions and sharing the ones defined in `drivers/pc80/keyboard.c` - Should public library functions for sending and receiving data from a PC80 keyboard controller be defined in the PC80 driver and exported in `include/pc80/keyboard.h`? - We already have `send_keyboard()` there, which sends a command and receives data - would it be good to add individual functions for those operations as well? Any suggestions or recommendations would be appreciated. I looked for guidelines on suggested code organization in the docs/commit history/ mailing list, but came up mostly empty-handed. Thanks!

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com April 8, 2022

April 8, 2022

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1487871: Control flow issues (DEADCODE) /src/vendorcode/google/chromeos/watchdog.c: 35 in reset_watchdog_tombstone() ________________________________________________________________________________________________________ *** CID 1487871: Control flow issues (DEADCODE) /src/vendorcode/google/chromeos/watchdog.c: 35 in reset_watchdog_tombstone() 29 BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, 30 elog_handle_watchdog_tombstone, NULL); 31 32 bool reset_watchdog_tombstone(void) 33 { 34 if (!REGION_SIZE(watchdog_tombstone)) >>> CID 1487871: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "return false;". 35 return false; 36 37 bool flag = (read32(_watchdog_tombstone) == WATCHDOG_TOMBSTONE_MAGIC); 38 write32(_watchdog_tombstone, 0); 39 return flag; 40 } ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Elkhart Lake board bring up questions
by Dubravko Moravski | Exor Embedded S.r.l. April 8, 2022

April 8, 2022

Hello Coreboot, I work for a company that makes a board containing an Elkhart Lake CPU and we use Coreboot to boot it. We have started from Intel's document #626123 source files and document #641906 for instructions. Release notes say "This is the main release of the coreboot Boot Loader Proof of Concept for the Elkhart Lake (EHL) series. Date: May 2021; revision: PR 1; description: PR 1 release" We have already asked Intel for assistance, but they redirected us here. The final Coreboot binary works, but we are having some issues that so far we were unable to solve on our own. We are using latest Linux Mint x64 for most of our tests and soon we'll switch to Yocto. 1. There are roughly about 200 configurable pins on the CPU. We would like to use some as GPIOs. We can configure pin functionalities according to our needs in Coreboot source code (gpio.c, gpio_table[] definition), but Linux doesn't seem to know what to do with GPIO pins: in /sys/class/gpio we only see gpiochip445. To which of the EHL pins does 445 correspond? What should we do to see the rest of the pins? Some comments in the code suggest there can't be more than 32 pins per 'gpiochip'. 2. We have enabled CAN controllers in devicetree.cb: device pci 18.1 on end # Intel Programmable Services Engine CAN0 device pci 18.2 on end # Intel Programmable Services Engine CAN1 ... but in Linux we don't see devices 0:18.1 and 0:18.2. What else should we do to enable CAN controllers? 3. How do we enable eSPI in Coreboot and how it should be accessible afterwards in Linux? We did: device pci 1f.0 on end # eSPI Interface Device 0:1f.0 is visible. How should we access this bus in Linux or declare a device in SSDT table on this bus? 4. We have a TPM chip SLB9670 connected to FSPI, CS2. device pci 1f.5 on end # PCH SPI (flash & TPM) ... and device 0:1f.5 is visible, but Linux kernel reports it couldn't find any TPM chip. What do we need to do to get it working? $ dmesg | grep -i tpm [ 0.006614] ACPI: TPM2 0x0000000075AEF4B0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200717) [ 0.006640] ACPI: Reserving TPM2 table memory at [mem 0x75aef4b0-0x75aef4fb] [ 0.771703] ima: No TPM chip found, activating TPM-bypass! 5. We can't get audio to work. device pci 1f.3 on end # cAVS/HDA ... and device 0:1f.3 is visible. This is output from kernel: $ dmesg | grep -i hda [ 5.559993] snd_hda_intel 0000:00:1f.3: DSP detected with PCI class/subclass/prog-if info 0x040100 [ 5.560003] snd_hda_intel 0000:00:1f.3: NHLT table not found [ 66.698806] snd_hda_intel 0000:00:1f.3: couldn't bind with audio component [ 66.731030] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec [ 66.731465] snd_hda_intel 0000:00:1f.3: Cannot probe codecs, giving up We think Linux should see (up to) 3 audio devices: HDMI, DisplayPort and analog codec CS4207. Thank you in advance for any advice. Dubravko Moravski SW engineering Exor Embedded S.r.l. p: +38 512455659<tel:+38%20512455659> m: +38 5915402413<tel:+38%205915402413> a: Slavonska avenija, 50, Zagreb, Croatia, 10000 w: exorint.com<https://exorint.com/> [cid:x-sign_alone_89a12ff2-fa07-4acd-b9a0-8e9a8c2b3e4c.jpg] [cid:environment-verde_4010c4a3-6fcf-4e6d-8a58-167a2248b283.jpg] Prima di stampare pensa ai costi ambientali. Please consider the environment before printing this email. Privacy<https://www.exorint.com/it/privacy>

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[GSoC] Introduction & project ideas
by Théo Jehl April 6, 2022

April 6, 2022

Hello! I'm Théo, a 1st-year master's student, specializing in embedded system engineering from France. I'm interested in joining Coreboot with the Google Summer of Code program. Currently, I have little to no experience in the firmware/boot world as I'm only starting in this field. At university I've learned operating systems architecture, I know how to write C/C++ and I started doing some X86 ASM. I also developed a disk driver, a file system and virtual memory mapping using an emulated MMU as part of a university project. I'm interested in porting a payload to ARM or AARCH64 [1] but I'm open to other project ideas if you have any. Thanks in advance Théo [1] https://doc.coreboot.org/contributing/project_ideas.html#port-payloads-to-a…

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2022-04-06 - coreboot Leadership Meeting Minutes
by coreboot org April 6, 2022

April 6, 2022

# 2022-04-06 - coreboot Leadership Meeting Minutes Next meeting - 2022-04-20 - See the calendar on the coreboot website for more information. ## Attendees Felix Held, Jay Talbott, Arthur Heymans, David Hendricks, Christian Walter, Stefan Reinauer, Lean Sheng Tan, Martin Roth, Matt Papageorge, Piotr Krol, Tim Crawford, Julius Werner, Felix Singer, Patrick Georgi ## Decisions * Let’s look at adding code to be able to combine romstage and ramstage. This is similar to what is currently done with combining verstage with either romstage or bootblock. * Send out surveys to coreboot consultants. * No reason to move Quark to a branch unless there's actually an issue. Felix S will link to the problematic code. ## Minutes * [Arthur] Let's look at a single stage (ramstage) on AMD platforms * We discussed a hybrid romstage before, but we really only need a ramstage at this point. None of the currently required code really needs to be in romstage however. We can move all of the required code into ramstage, which would dramatically simplify the code by removing everything passing between stages. * One stage means we can reference symbols directly without requiring linker scripts, cbmem additions, etc. * How would this work with Ron’s idea of getting rid of ramstage? * It would generally be a different configuration. * How much re-architecture would this require? * The idea wasn’t to rearchitect coreboot, just to add the calls that would normally happen in romstage to the beginning of ramstage. * Make ramstage callable as a function rather than treating it as a separate blob to jump to. * Let’s not make this a requirement or try to move all platforms to this flow. * [Martinr] Coreboot approved vendors - update website. * Send out a survey to all coreboot consultants. * [Julius]: libpayload CBFS API deprecation; please port payloads to new API. See the notice on the mailing list for more information. [1] * [Martin]: Moving Quark to a branch. [2] * We’re not “Deprecating platforms”, we’re moving their support to a branch. * [Jay]: Syspro has pushed a number of platform changes to the 4.11 branch. Supporting platforms there is not a problem. * Why would we move this out of the main branch? It uses FSP 2.0, and it’s the only open source fsp. * [Felix S] There’s some quark-only code that should probably be improved if quark is not getting removed. * [Martin] See if we can gather some information about what’s getting built to help decide what’s not actually being used anymore. * Would need to consult lawyers * This might cause more confusion than we even have * [Arthur] Update sdk docker for latest clang * This will be updated this week. * [FelixS] Thinking about doing a firmware hackathon in Darmstadt, Germany. Poll and some more details at the link. [3] * [Chris] 9elements / Foundation can sponsor food/place/whatever * @Felix - Get in contact with Sheng or Chris on that * This would happen June 10 - 12 June * [Jay]: Martin, any sign of the ITRenew server? * Not yet. :( * [David]: Porting Up Extreme to coreboot - whiskey lake platform * Having issues flashing with a dediprog * The UP Extreme boards have a unique port for flashing that needs an adapter. * 9elements has adapters that will make this work. * Can we figure out a way that people can get these created easily? * qspimux: https://github.com/felixheld/qspimux * David had issues getting the qspiMux boards manufactured at oshpark. Outlines too close to board edge - small violations of design rules, probably due to the castellated holes on the board adapters; that usually costs extra and not all manufacturers can do that. # Next meeting * The coreboot leadership meeting minutes are available here: [4] * The next coreboot leadership meeting will be 2022-04-20: [5] # Notice Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. [1]: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/VLMK… [2]: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YRJQ… [3]: https://terminplaner4.dfn.de/pBooK8FBDlM2zDwa [4]: https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK… [5]: https://calendar.google.com/event?action=TEMPLATE&tmeid=MzNhYm9rMmtxMnU1aWV…

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[GSoC] Console via SMBus
by Ahamed Husni April 5, 2022

April 5, 2022

Hi everyone, I would like to work with bringing up the Console via SMBus project [1]. This project requires a mainboard with pluggable RAM for the development so that we can use a RAM breakout board [2] to access the SMBus interface. Preferably the mainboard should already support coreboot. Please add your thoughts and concerns about the project and suggest a mainboard for the project :) [1] https://www.coreboot.org/Project_Ideas#console_via_SMBus [2] https://www.joom.com/en/products/5fa9df2ea1684001068ec310 Thank you, Husni.

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Memtest 86+ fork
by Sameeruddin Shaik April 3, 2022

April 3, 2022

Hi all, I wanted to work on below ticket https://ticket.coreboot.org/issues/184 Is there anyone working on it. Any inputs/hints would be appreciated. --sameer.

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com April 1, 2022

April 1, 2022

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 6 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 6 of 6 defect(s) ** CID 1487636: Resource leaks (RESOURCE_LEAK) /util/cbfstool/fmd_parser.y: 173 in parse_descriptor() ________________________________________________________________________________________________________ *** CID 1487636: Resource leaks (RESOURCE_LEAK) /util/cbfstool/fmd_parser.y: 173 in parse_descriptor() 167 struct descriptor_node *next_node = cur_node->next; 168 free(cur_node); 169 cur_node = next_node; 170 } 171 } else { 172 region->list = NULL; >>> CID 1487636: Resource leaks (RESOURCE_LEAK) >>> Variable "region" going out of scope leaks the storage it points to. 173 } 174 return region; 175 } 176 177 void yyerror(const char *s) 178 { 179 fprintf(stderr, "%s\n", s); ** CID 1487635: Incorrect expression (SIZEOF_MISMATCH) /src/soc/qualcomm/common/qclib.c: 172 in qclib_load_and_run() ________________________________________________________________________________________________________ *** CID 1487635: Incorrect expression (SIZEOF_MISMATCH) /src/soc/qualcomm/common/qclib.c: 172 in qclib_load_and_run() 166 memset(_ddr_training, 0, REGION_SIZE(ddr_training)); 167 } 168 qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, 169 _ddr_training, REGION_SIZE(ddr_training), 0); 170 171 /* Attempt to read MEM CHIP information */ >>> CID 1487635: Incorrect expression (SIZEOF_MISMATCH) >>> Passing argument "mem_chip_addr" of type "void *" and argument "8U /* sizeof (mem_chip_addr) */" to function "qclib_add_if_table_entry" is suspicious. 172 qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, 173 mem_chip_addr, sizeof(mem_chip_addr), 0); 174 175 /* Attempt to load PMICCFG Blob */ 176 data_size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", 177 _pmic, REGION_SIZE(pmic)); ** CID 1487634: Integer handling issues (SIGN_EXTENSION) /src/cpu/intel/common/common_init.c: 226 in set_energy_perf_pref() ________________________________________________________________________________________________________ *** CID 1487634: Integer handling issues (SIGN_EXTENSION) /src/cpu/intel/common/common_init.c: 226 in set_energy_perf_pref() 220 * prefer energy efficiency. 221 * This function needs to be called when HWP_ENABLE is set. 222 */ 223 void set_energy_perf_pref(u8 pref) 224 { 225 msr_unset_and_set(IA32_HWP_REQUEST, IA32_HWP_REQUEST_EPP_MASK, >>> CID 1487634: Integer handling issues (SIGN_EXTENSION) >>> Suspicious implicit sign extension: "pref" with type "u8" (8 bits, unsigned) is promoted in "pref << 24" to type "int" (32 bits, signed), then sign-extended to type "unsigned long long" (64 bits, unsigned). If "pref << 24" is greater than 0x7FFFFFFF, the upper bits of the result will all be 1. 226 pref << IA32_HWP_REQUEST_EPP_SHIFT); ** CID 1487633: Error handling issues (CHECKED_RETURN) /src/drivers/i2c/tpm/cr50.c: 257 in cr50_i2c_tis_ready() ________________________________________________________________________________________________________ *** CID 1487633: Error handling issues (CHECKED_RETURN) /src/drivers/i2c/tpm/cr50.c: 257 in cr50_i2c_tis_ready() 251 } 252 253 /* cr50 requires all 4 bytes of status register to be written */ 254 static void cr50_i2c_tis_ready(struct tpm_chip *chip) 255 { 256 uint8_t buf[4] = { TPM_STS_COMMAND_READY }; >>> CID 1487633: Error handling issues (CHECKED_RETURN) >>> Calling "cr50_i2c_write" without checking return value (as is done elsewhere 4 out of 5 times). 257 cr50_i2c_write(TPM_STS(chip->vendor.locality), buf, sizeof(buf)); 258 mdelay(CR50_TIMEOUT_SHORT_MS); 259 } 260 261 /* cr50 uses bytes 3:2 of status register for burst count and 262 * all 4 bytes must be read */ ** CID 1487632: Null pointer dereferences (REVERSE_INULL) /src/drivers/wifi/generic/acpi.c: 539 in wifi_ssdt_write_properties() ________________________________________________________________________________________________________ *** CID 1487632: Null pointer dereferences (REVERSE_INULL) /src/drivers/wifi/generic/acpi.c: 539 in wifi_ssdt_write_properties() 533 534 static void wifi_ssdt_write_properties(const struct device *dev, const char *scope) 535 { 536 bool is_cnvi_ddr_rfim_enabled = false; 537 538 const struct drivers_wifi_generic_config *config = dev->chip_info; >>> CID 1487632: Null pointer dereferences (REVERSE_INULL) >>> Null-checking "dev" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 539 if (dev && config) 540 is_cnvi_ddr_rfim_enabled = config->enable_cnvi_ddr_rfim; 541 542 /* Scope */ 543 acpigen_write_scope(scope); 544 ** CID 1487631: Memory - corruptions (OVERRUN) ________________________________________________________________________________________________________ *** CID 1487631: Memory - corruptions (OVERRUN) /src/mainboard/google/herobrine/bootblock.c: 14 in bootblock_mainboard_init() 8 9 void bootblock_mainboard_init(void) 10 { 11 setup_chromeos_gpios(); 12 13 if (CONFIG(MAINBOARD_HAS_I2C_TPM_CR50)) >>> CID 1487631: Memory - corruptions (OVERRUN) >>> Overrunning callee's array of size 12 by passing argument "14U" in call to "i2c_init". 14 i2c_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); /* H1/TPM I2C */ 15 16 if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) 17 qup_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1010 * KHz); /* H1/TPM SPI */ 18 19 if (CONFIG(EC_GOOGLE_CHROMEEC)) 20 qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); /* EC SPI */ ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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Support to Openpower platforms
by ratatouille gamer April 1, 2022

April 1, 2022

the openpower have created this new firmware for boot openpower platforms is possible to coreboot use this base to write a new code for best support in openpower socs? https://github.com/open-power/hostboot

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Re: PSE devices enumeration in corevoot
by Rao G April 1, 2022

April 1, 2022

Hi Sheng, In the coreboot log I see PCI: 00:1d.0 [8086/4bb3] disabled PCI: Static device PCI: 00:1d.1 not found, disabling it. PCI: Static device PCI: 00:1d.2 not found, disabling it. In the FSP debug log I see PSE TSN Device: Device Id: 0xFFFF, Vendor Id: 0xFFFF PSE TSN Device: Device Id: 0xFFFF, Vendor Id: 0xFFFF Thanks Ranga Thanks Ranga On Thu, Mar 31, 2022 at 3:04 PM Rao G <grao.v80(a)gmail.com> wrote: > Hi Sheng, > > Thanks for your email and response. > > 1. Yes I used unsigned binary - PSE_FW that came along with 638228_PSE > > 2. In Device Tree > device pci 1d.0 off end # Intel Programmable Services Engine IPC > (local host to PSE) > device pci 1d.1 on end # Intel Programmable Services Engine > Time-Sensitive Networking GbE 0 > device pci 1d.2 on end # Intel Programmable Services Engine > Time-Sensitive Networking GbE 1 > > 3. This is not an RVP but a platform with EHL SoC and I could boot to > OS/Ubuntu with coreboot BIOS > > Do these TSN GbE devices need MAC programming? I don't see them enumerated > from EFI Shell or in OS/spci > > Thanks > Ranga > > > On Thu, Mar 31, 2022 at 2:34 PM Lean Sheng Tan <sheng.tan(a)9elements.com> > wrote: > >> Hi Ranga, >> Are you using Intel RVP? Yes you should at least be able to see the PSE >> TSN working if the PSE binary is included correctly (remember to include >> the 'unsigned' PSE binary from Intel), by turning on PSE TSN devices in >> devicetree.cb: >> device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 >> device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 >> >> Thanks, >> Sheng >> >> On Tue, 29 Mar 2022 at 18:32, Rao G <grao.v80(a)gmail.com> wrote: >> >>> Hi All, >>> >>> Did anybody work on Elkhart Lake that comes with PSE Firmware? >>> I don't see any devices getting enumerated which are under PSE I2C,UART, >>> Gbe,TSN >>> >>> The logs shows >>> >>> PSE Firmware Status is A138 read from address FE400034 >>> BIOS: PSE FW is loaded and running >>> >>> Looks like FSP is disabling PSE devices to enumerate >>> >>> Is this binary enough for coreboot? PSE_FW.bin >>> [image: image.png] >>> >>> Appreciate any pointers that would help to enumerate PSE devices in EFI >>> Shell >>> >>> Thanks >>> Ranga >>> _______________________________________________ >>> coreboot mailing list -- coreboot(a)coreboot.org >>> To unsubscribe send an email to coreboot-leave(a)coreboot.org >>> >>

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