January 2019 - coreboot - mail.coreboot.org

Depreciating FSP1.1 on soc/intel/quark along with util/checklist
by Arthur Heymans Jan. 9, 2019

Jan. 9, 2019

Dear community soc/intel/quark Has 2 FSP versions hooked up, both FSP1.1 and FSP2.0. Maintaining the code for both versions does increase the developers load. So my question is can we remove the older FSP1.1 implementation? Is someone using this board in a setup that cannot be obtained with FSP2.0? There is only one board that has both FSP versions hooked up which can be selected in menuconfig, so we wouldn't be dropping a board. FSP1.1 on the Intel Galileo (only board using soc/intel/quark) is also the only board that uses util/checklist. This utility allows to check if certain linker symbols are found. Supposedly it allows board porters to gradually work towards with a checklist of things to do while in reality its just an extra burden to maintain a list of symbols. So can we remove util/checklist? [1] does that. Kind regards Arthur Heymans [1] https://review.coreboot.org/c/coreboot/+/30691

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Re: [coreboot] AMD IMC open source firmware replacement
by Rudolf Marek Jan. 7, 2019

Jan. 7, 2019

Dne 30.5.2018 v 16:06 Mike Banon napsal(a): > Hi Rudolf, > > Regarding this part: > " To check if IMC is active check if PCI 0:14.3 0x40 bit7 set. " > what command do I need to use to check this? Try: sudo setpci -s 14.3 40.b Despite command name, it will print the value. Thanks Rudolf

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Please help me adapt coreboot to HiFive-Unleashed
by 王翔 Jan. 7, 2019

Jan. 7, 2019

I tried to adapt coreboot to HiFive-Unleashed and boot bbl with coreboot and run linux. My changes are as follows: https://github.com/hardenedlinux/coreboot-HiFiveUnleashed/tree/HiFive-Unlea… My code can run bbl, but it doesn't respond when bbl exits m-mode and enters linux. I use freedom-u-sdk to compile bbl. In order not to conflict with the coreboot memory address, execute the following command. riscv64-elf-objcopy --change-addresses 0x200000 work/riscv-pk/bbl ../coreboot/payload.elf I don't know what I missed, what should I do, I hope to get your help. ------------------ 王翔安全研究员广州市腾御安信息科技有限公司广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com Jan. 4, 2019

Jan. 4, 2019

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1398603: (CONSTANT_EXPRESSION_RESULT) /src/soc/mediatek/mt8183/dramc_pi_basic_api.c: 124 in transfer_pll_to_spm_control() /src/soc/mediatek/mt8183/dramc_pi_basic_api.c: 125 in transfer_pll_to_spm_control() ________________________________________________________________________________________________________ *** CID 1398603: (CONSTANT_EXPRESSION_RESULT) /src/soc/mediatek/mt8183/dramc_pi_basic_api.c: 124 in transfer_pll_to_spm_control() 118 clrsetbits_le32(&mtk_spm->poweron_config_set, 119 (0xffff << 16) | (0x1 << 0), 120 (0xb16 << 16) | (0x1 << 0)); 121 122 /* Set SPM pinmux */ 123 clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); >>> CID 1398603: (CONSTANT_EXPRESSION_RESULT) >>> "((uint32_t)read32(&mtk_spm->dramc_dpy_clk_sw_con_sel) & 4294967295U /* ~((uint32_t)0) */) | 0xffffffffU" is always 0xffffffff regardless of the values of its operands. This occurs as an argument to a function call. 124 setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); 125 setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); 126 127 setbits_le32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12)); 128 setbits_le32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0); 129 /src/soc/mediatek/mt8183/dramc_pi_basic_api.c: 125 in transfer_pll_to_spm_control() 119 (0xffff << 16) | (0x1 << 0), 120 (0xb16 << 16) | (0x1 << 0)); 121 122 /* Set SPM pinmux */ 123 clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); 124 setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff); >>> CID 1398603: (CONSTANT_EXPRESSION_RESULT) >>> "((uint32_t)read32(&mtk_spm->dramc_dpy_clk_sw_con_sel2) & 4294967295U /* ~((uint32_t)0) */) | 0xffffffffU" is always 0xffffffff regardless of the values of its operands. This occurs as an argument to a function call. 125 setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff); 126 127 setbits_le32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12)); 128 setbits_le32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0); 129 130 shu_lev = (shu_lev == 1) ? 2 : 1; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Please suggest a AM3/AM3+ motherboard which is supported by Coreboot when32GB of RAM installed
by info＠aulix.com Jan. 3, 2019

Jan. 3, 2019

Hello, I have found that following boards are indicated as supported: Version:1.0 StartHTML:0000000105 EndHTML:0000025498 StartFragment:0000020391 EndFragment:0000025458 ASUS M4A785-M WIP... AMD Fam10h AMD RS780/SB700 ITE™ IT8712F AMD Athlon™ 64 / FX / X2 Socket AM3/AM2(+) DIP8 SPI Y Y — ASUS M4A785T-M OK... AMD Fam10h AMD RS780/SB700 ITE™ IT8712F AMD Athlon™ 64 / FX / X2 Socket AM3 DIP8 SPI Y Y — ASUS M4A78-EM OK... AMD Fam10h AMD RS780/SB700 ITE™ IT8712F AMD Athlon™ 64 / FX / X2 Socket AM3/AM2(+) DIP8 SPI Y Y — ASUS M5A88-V OK... AMD Fam10h AMD 880G/850 ITE™ IT8721F AMD Athlon™Phenom™Sempron™ 64 / FX / X2 Socket AM3/AM3+ DIP8 SPI Y Y — GIGABYTE GA-MA785GMT-UD2H OK... AMD Fam10h AMD 785G / SB710 ITE IT8718F AMD Phenom™ II / Athlon™ II Socket AM3 ? ? ? ? — GIGABYTE GA-MA78GM-US2H OK AMD Fam10h AMD 780G / SB700 ITE IT8718F AMD Phenom™ / Athlon™ / Sempron™ Socket AM2+ ? ? ? ? — And actually most of them missing any info on the status page and somewhere is info like: The boards works only with less than 4GB of RAM, if installed more then it does not boot Linux. You can see that some AMD 16GB boards support 32GB two with 4x8GB modules: https://www.overclockers.com/forums/showthread.php/698565-Can-i-use-8GB-DDR… http://www.tomshardware.com/answers/id-1714859/asus-m5a88-evo-ram.html But these are 32GBs with their original BIOSes. What about 16GB or 32GB with a Coreboot flashed on these boards? Did anyone tested and used such config with 16GB or 32GB DDR3 RAM? Kind Regards, Alex

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Graphics Mode
by galla rao Jan. 3, 2019

Jan. 3, 2019

Video Mode in Coreboot *CorebootLog* coreboot video frame buffer information physical_address: 0xC0000000 *x_resolution: 0x400* *y_resolution: 0x300* bits_per_pixel: 0x20 bytes_per_line: 0x1000 red_mask_size: 0x8 red_mask_pos: 0x10 GOP UEFI driver (Tiano payload) is expected to report 4 modes GOP should report MaxMode 4 *0: 1600x900 BGRReserved Pixels 1600 1: 640x480 BGRReserved Pixels 640 2: 800x600 BGRReserved Pixels 800 3: 1024x768 BGRReserved Pixels 1024 In BayTrail Platform i only see 1 single mode which is 400 * 300 what changes are expected from GOP/VBIOS to set one of the 4 graphics mode Please advise! Best Regards Ranga

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