January 2019 - coreboot - mail.coreboot.org

OpenBSD won't install on an x220 Thinkpad with Coreboot
by Robert Milton April 12, 2020

April 12, 2020

I'm trying to get OpenBSD to install on an x220 Thinkpad with Coreboot/SeaBIOS but I'm running into two problems: the ethernet device doesn't work and OpenBSD doesn't detect my HDD. dmesg said em0 wouldn't load because the EEPROM had an invalid signature. I have no idea why OpenBSD doesn't see my HDD though. It's strange because everything works fine under Linux. And I cannot seem to mount a usb drive under the OpenBSD installer to attach dmesg errors. I originally posted this as a bug report to bug report mailing list but Theo said it would be better suited for Coreboot's and wasn't a bug in OpenBSD.

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Optiplex 790 now has preliminary support by coreboot
by Taiidan＠gmx.com Jan. 15, 2020

Jan. 15, 2020

https://review.coreboot.org/21774 In case anyone else didn't notice - It is a sandy/ivy system with IOMMU. This is great and should help get coreboot in to the corporate user world.

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Coreboot doesn't POST on ASUS KCMA-D8
by espionage724＠posteo.net March 28, 2019

March 28, 2019

I have a KCMA-D8 motherboard with two Opteron 4226s, and 6x4GB (24GB) Hynix HMT151R7BFR4C-H9 RAM sticks. All my attempts of getting Coreboot to POST with this board so far haven't worked. I'm compiling Coreboot from Git (master branch), and can build it without issue. A pre-built Libreboot ROM (20160907) POSTs and boots fine. For Coreboot's config, I've tried including/excluding CPU microcode updates, along with some less important-sounding options. For hardware, I've tried unplugging everything external (KB/mouse), my GPU (RX 580), and only had a single RAM stick in (slot A1). I've also tried a single CPU being powered (kept the 2nd CPU in but only had a single 4-pin CPU going to the 1st CPU). Can anyone else confirm Git builds of Coreboot booting on this board, or provide any tips as to anything I could be missing? I see this issue https://ticket.coreboot.org/issues/151 but there's a board status months after that that looks like it boots: https://review.coreboot.org/cgit/board-status.git/tree/asus/kcma-d8/4.7-789…

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Menu time-out missing when GRUB is loaded quickly and `at_keyboard`
by Paul Menzel Feb. 6, 2019

Feb. 6, 2019

Dear GRUB folks, When the module `at_keyboard` is directly into the GRUB image (`--modules`), and GRUB is loaded really quickly, then the timer, which, after counting down to 0 (`GRUB_TIMEOUT`), starts the selected entry, is not shown. I noticed this issue on the ASRock E350M1 with coreboot and a small GRUB payload, and a PS/2 keyboard connected. Due to the missing time-out, I manually have to confirm the selected entry. By chance, the keyboard wasn’t connected setting up the system somewhere else, and that made it work as expected. So, it looks like, it’s related to `at_keyboard`, and some race, because the bigger default GRUB payload also does not show the problem. Luckily, it’s easily reproducible with GRUB’s standard `default_payload.elf` and QEMU. Please find the instructions below to reproduce the issue. $ git clone https://review.coreboot.org/coreboot $ cd coreboot $ # save attached grub.cfg in the directory $ util/scripts/config -e PAYLOAD_GRUB2 grep: .config: Datei oder Verzeichnis nicht gefunden $ util/scripts/config -e GRUB2_INCLUDE_RUNTIME_CONFIG_FILE $ util/scripts/config -e GRUB2_MASTER $ util/scripts/config -e CONFIG_COREBOOT_ROMSIZE_KB_2048 # default of 512 KB too small for GRUB payload $ util/scripts/config -e ANY_TOOLCHAIN $ # or: make crossgcc-i386 CPUS=`nproc` $ make olddefconfig $ make -j`nproc` $ qemu-system-x86_64 --version QEMU emulator version 3.1.0 (Debian 1:3.1+dfsg-2+b1) Copyright (c) 2003-2018 Fabrice Bellard and the QEMU Project developers $ qemu-system-x86_64 -M pc -bios build/coreboot.rom -serial stdio *No* time-out is shown. Telling QEMU to emulate a USB keyboard, indirectly disabling the PS/2 keyboard, the time-out *is* shown. $ qemu-system-x86_64 -M pc -bios build/coreboot.rom -serial stdio \ -usb -device usb-kbd Not including `at_keyboard` directly in GRUB’s “core image”, modules loaded automatically, the time-out is also shown. `set debug=at_keyb` did not show anything interesting. Can you reproduce that, and see what the problem is? Kind regards, Paul PS: Please find the instructions to build GRUB as a coreboot payload done by coreboot’s Kconfig system automatically, and how put it into the coreboot filesystem CBFS. ``` $ git clone https://git.savannah.gnu.org/git/grub.git/ $ cd grub $ git describe --tags --dirty grub-2.02-238-ga791dc0e3 $ ./autogen.sh $ ./configure --with-platform=coreboot $ make default_payload.elf # this includes `at_keyboard` $ cp default_payload.elf my/coreboot/folder/ $ cd my/coreboot/folder/ $ build/cbfstool build/coreboot.rom print $ build/cbfstool build/coreboot.rom remove -n fallback/payload $ build/cbfstool build/coreboot.rom add-payload -f payload.elf -n fallback/payload -c lzma ``` Kind regards, Paul

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Braswell FPS memory init problems
by Michal Zygowski Feb. 1, 2019

Feb. 1, 2019

Dear coreboot community, I am experiencing problems with FSP Memory Init on Braswell SoCs. FSP Memory Init is not returning. I have following processors that fail: Celeron J3060 and Celeron J3160; both have the same issue. The platform has 1 SODIMM module on channel 0. I am feeding the UPD header with correct SPD, but still no luck. I have also tried FSP MR1 and MR2, but nothing works. Is anyone here more experienced with Braswell platforms? Could You give me some advices? Best regards, -- Michał Żygowski Embedded Systems Engineer http://3mdeb.com | @3mdeb_com

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Re: [coreboot] [LinuxBoot] FOSDEM 2019 deadline today
by Carl-Daniel Hailfinger Feb. 1, 2019

Feb. 1, 2019

In that case, I'd also like to point you to the deadline for submitting main track talks which is tomorrow(!). https://fosdem.org/2019/news/2018-08-10-call-for-participation/ Having a coreboot/LinuxBoot talk there would be awesome. Ron/David, could you submit something or do you have someone in mind who can do that? There's also lightning talks, deadline is a bit later. OK, I'm submitting a request for a stand. I need a backup contact for the stand. Who is willing to do that? AFAICS we can still change the backup contact later if life happens. Regards, Carl-Daniel On 02.11.2018 20:48, David Hendricks wrote: > > > On Fri, Nov 2, 2018 at 9:15 AM 'Ron Minnich' via linuxboot > <linuxboot(a)googlegroups.com <mailto:linuxboot@googlegroups.com>> wrote: > > I"m leaning to yes, by which I mean if you do it, I'll show up. > > I can't believe I said that. > On Fri, Nov 2, 2018 at 7:20 AM Carl-Daniel Hailfinger > <c-d.hailfinger.devel.2006(a)gmx.net > <mailto:c-d.hailfinger.devel.2006@gmx.net>> wrote: > > > > Hi! > > > > FOSDEM next year will be on 2 & 3 February 2019. > > The deadline for applying for a stand is today. > > Do we want a coreboot/flashrom/LinuxBoot stand/booth? > > > Same as what Ron said. I think someone from FB can be there to talk > about coreboot/LinuxBoot stuff and perhaps bring some hardware to demo. > >

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Re: [coreboot-gerrit] Change in ...coreboot[master]: usbdebug: Fix reserve in CAR
by Aaron Durbin Jan. 31, 2019

Jan. 31, 2019

On Thu, Jan 31, 2019 at 11:13 AM Kyösti Mälkki (Code Review) < gerrit(a)coreboot.org> wrote: > Aaron, Julius; there is a bit of dilemma with car.ld. > > 1) We need consistent layout across PRE_RAM stages > 2) We want RO bootblock, unaware of (future) RW romstage requirements > 3) I don't like the semi-random size reserve, like done here for usbdebug > > Any ideas how to from improve this? Looking at CONFIG_COMMONLIB_STORAGE > and CONFIG_PAGING_IN_CACHE_AS_RAM, I am not sure if the fixed locations are > always maintained properly. There is some strong assumption at least, that > bootblock and romstage are built with same set of Kconfig options set. > That definitely is the assumption. Kconfigs are global and there shouldn't be guarding of entries in the car.ld linker script based on stage w.r.t. to order and size of the allocated space. > View Change <https://review.coreboot.org/c/coreboot/+/31174> > > 1 comment: > > - > > File src/arch/x86/car.ld: > <https://review.coreboot.org/#/c/31174/1/src/arch/x86/car.ld> > - > > Patch Set #1, Line 70: > <https://review.coreboot.org/#/c/31174/1/src/arch/x86/car.ld@70> . > += 0x60; > > yes > > Done > > To view, visit change 31174 > <https://review.coreboot.org/c/coreboot/+/31174>. To unsubscribe, or for > help writing mail filters, visit settings > <https://review.coreboot.org/settings>. > Gerrit-Project: coreboot > Gerrit-Branch: master > Gerrit-Change-Id: Ib49fca781e55619179aa8888e2d859560e050876 > Gerrit-Change-Number: 31174 > Gerrit-PatchSet: 2 > Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> > Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> > Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> > Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> > Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> > Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> > Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> > Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> > Gerrit-Comment-Date: Thu, 31 Jan 2019 18:13:01 +0000 > Gerrit-HasComments: Yes > Gerrit-Has-Labels: No > Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> > Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> > Gerrit-MessageType: comment > _______________________________________________ > coreboot-gerrit mailing list -- coreboot-gerrit(a)coreboot.org > To unsubscribe send an email to coreboot-gerrit-leave(a)coreboot.org >

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RTC issue
by Hilbert Tu(杜睿哲_Pegatron) Jan. 30, 2019

Jan. 30, 2019

Hi, My platform is Intel Denverton with Coreboot 4.8.1 and it can boot up successfully except RTC. There is always an error like “unable to open rtc device (rtc0)” when I try to set clock. But if I use BIOS to boot up again, this error will be disappeared and later boot up with Coreboot and setup hwclock successfully. Does anyone have same experience and know how to fix it? Thanks. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

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Second call for mentor candidates and project ideas for Google Summer of Code 2019
by Patrick Georgi Jan. 29, 2019

Jan. 29, 2019

Hi everybody, I just want to remind you that we're applying for GSoC this year and for planning reasons they want us to state how many mentors we expect to have. So if you're interested to potentially help a student get up to speed on a firmware related topic (coreboot or nearby projects), please reach out to me until Sunday, so I can finalize the paper work (which is due next week). While students shall outline the project they want to work on in their application to GSoC, it's normal and expected to provide guidance in the form of project proposals. If you have ideas (and ideally are prepared to mentor students working on them) please reach out to me as well. I'll incorporate them in https://review.coreboot.org/c/coreboot/+/30972 so we'll have a maintained collection on our documentation site. That list is also suitable for other situations but whatever the occasion, it always help to have a point of contact listed with any idea so that somebody interested in working on them knows who to contact for details and help. Thanks, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

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Re: [coreboot] Upgrade the 12 years old LZMA libraries - should we do it?
by Carl-Daniel Hailfinger Jan. 29, 2019

Jan. 29, 2019

Hi Ivan, On 03.04.2018 20:03, Ivan Ivanov wrote: > I have noticed that both coreboot and seabios are using the very old > versions of LZMA SDK. True. I introduced the lzma code in coreboot (back when it was called LinuxBIOS) when we were working on OLPC XO-1 support. > If we will upgrade our LZMA libraries from the > outdated-by-12-years 4.42 to the current version 18.04 , speed and > compression ratio should improve and maybe a few bugs will be fixed. Do you have any numbers for this? An improved compression ratio and improved speed would be nice indeed, but how does the size of the decompression code change? If the decompression code grows more than the size reduction from better compression, it would be a net loss. A significantly reduced decompression speed would also be a problem. Decompression speed would have to be measured both for stream decompression (i.e. the decompressor gets the compressed data in single-byte or multibyte chunks) as well as full-size decompression (i.e. the decompressor can access all compressed data at once). We also have to make sure that stream decompression still works after the change. > Do you think it should be done, or you are OK with using such an > outdated version? A size benefit for the resulting image is a good reason to switch. Regards, Carl-Daniel

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Fallback mechanisms on x86 with C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans Jan. 25, 2019

Jan. 25, 2019

Hi As more and more x86 platforms are moving to C_ENVIRONMENT_BOOTBLOCK and therefore don't use a romcc compiled bootblock anymore a certain question arises. With the romcc bootblock there was a normal/fallback mechanism. It works the following way: It uses RTC cmos to select between the normal and the fallback bootpaths. So depending on that bit the bootblock selected either normal/romstage or fallback/romstage which also load postcar stage, ramstage and payloads with the same prefix from there. There is also a reboot counter which makes sure that it actually gets to the point it can load the payload and depending on CONFIG_SKIP_MAX_REBOOT_CNT_CLEAR it resets that the counter. This mechanism is not very robust and is more intended to be used to be able to test things without needing a hardware programmer to flash images in the case something goes wrong. I use it for instance to test changes on laptops which take a long time to disassemble. Currently C_ENVIRONMENT_BOOTBLOCK lacks such generic mechanism on x86 platforms. On the first sight it looks like VBOOT with verstage running after the bootblock, might be able to achieve a similar boot scheme. VBOOT seems to lack documentation and while not that hard to get working, it looks like it is not falling back when there is problem on a RW_A/B boot path (I called die die(); somewhere in the ramstage to test). Also the tools around vboot (crossystem) are quite chromeos specific, requiring Chromeos specific ACPI code exposing the VBNV variables and also a Linux kernel exposing those ACPI methods via sysfs. My understanding of VBOOT might be incorrect or incomplete, so it would be great if someone more knowledgeable could fill in here. So at the moment it looks like VBOOT does not fit the bill to be able to quickly test things while having a fallback mechanism. Now being able to run GCC compiled code in the bootblock does have the advantage of allowing much more flexibility over romcc compiled code. So it is possible to simply reimplement the same behavior with different prefixes for bootpaths but it would also be possible to do something similar to what vboot does, namely using separate FMAP regions for boot paths. This would require a simple cbfs_locator. Upstream flashrom master now supports using FMAP as a layout so it would be rather easy to use. Using FMAP requires a little bit more work (generating a proper default FMAP, populate the CBFS FMAP regions, implementing a cbfs_locator) but does allow for nice features like locking the fallback CBFS region to make sure the fallback can't be erased by accident. Any thought or suggestions? Kind regards Arthur Heymans

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Re: Configuration for Thinkpad T530
by Ivan Ivanov Jan. 23, 2019

Jan. 23, 2019

Please don't forget to CC the coreboot mailing list. You could determine the chip's layout by looking on it: it has a dot near CS pin. As for cable/clip and programmer, check "Flashing BIOS chip with Bus Pirate" article at dangerous prototypes forums: it has a good review of SOIC8 test clips and also compatible with CH341A programmer. I'm quoting your message below, hope someone would help you with Intel-related questions вт, 22 янв. 2019 г. в 00:53, Yannik Catalinac <yc-153434(a)hs-weingarten.de>: > > Hello guys, > > thanks for the answers! > > >although I've never flashed t530 to me it seems pretty obvious: > >usually you connect your 8 wires to SPI flash chip and doing the > >flashing, but this time you'll connect 7 wires like usual to your > >programmer, but 8th CS wire to programmers VCC instead of programmers > >CS, and that programmers CS will be connected to CS of another chip > > The first problem is I don't know the layout of the first chip and especially of the second chip. > I could assume it depending on other boards I found on the internet/coreboot wiki but I'm not 100% sure for the T530. Where do I find the layout of the two chips of the T530? > > Second problem is how do I connect the second chip with the SPI programmer? I know which pins to connect, but I mean what cable/clip etc. do I need? What hardware do I need to buy? > > Greetings > >

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intelmetool crashed mei_me driver
by Shawn Jan. 23, 2019

Jan. 23, 2019

Hi, intelmetool crashed mei_me driver and you can reproduce it via: -------------------------- #!/bin/bash counter=0 while [ $counter -le 1000 ] do ./intelmetool -m >> /tmp/me.log echo $counter sleep 5 counter=$(($counter + 1)) done -------------------------- The kernel crash log was attached! -- GNU powered it... GPL protect it... God blessing it... regards Shawn

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Testing modernizing patches on ASUS KGPE-D16. (was Re: Asus KGPE-D16 with latest coreboot errors with Unsupported Hardware on Qubes 4 install missing IOMMU?)
by Daniel Kulesz Jan. 22, 2019

Jan. 22, 2019

Hi folks, is there a branch that has all the outstanding KGPE-D16 changes merged? I will be happy to test, but I feat I won't find the time to test all those fixes each in a separate branch. Also some specification of what tests need to be conducted would help. The outstanding KGPE-D16 bugs on my personal list are boot failures that require to turn off/on AC and the power consumption issues in idle that forced me to pull out one of the CPU packages and its RAM. But as far as I understood these were not targeted in the recent changes but could be "accidentially" fixed (e.g. by removal of some old buggy code) - correct? Cheers, Daniel

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intelmetool doesn't work on SPS
by Shawn Jan. 22, 2019

Jan. 22, 2019

Hi guys, I've tested coreboot/util/intelmetool on dell r730( haswell) and asus p10s-m ws( skylake) but got the same results: ./intelmetool -m MEI found: [8086:8d3a] C610/X99 series chipset MEI Controller #1 ME Status : 0x700f0345 ME Status 2 : 0xb8006000 ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : YES ME: Manufacturing Mode : NO ME: Boot Options Present : NO ME: Update In Progress : NO ME: Current Working State : Normal ME: Current Operation State : M0 without UMA ME: Current Operation Mode : (null) ME: Error Code : No Error ME: Progress Phase : Global reset after an error ME: Power Management Event : Sx/M3->S0/M0 ME: Progress Phase State : Unknown 0x00 ME: Extend Register not valid ME: circular buffer full, resetting... ME: message (4) too large for buffer (255) ME: GET FW VERSION message failed host.buffer_depth and host.buffer_write_ptr having the same values( 0xff) caused it into dark. Seems SPS and ME has some differences here. Any idea how to fix it? -- GNU powered it... GPL protect it... God blessing it... regards Shawn

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Re: coreboot meets apollolake
by Christian Gmeiner Jan. 21, 2019

Jan. 21, 2019

Hi > Hi, > > I do not see anything obviously wrong with your configuration. > Does the flash you use is 16mb or 8mb? IFD defines its own regions and FMAP must match IFD. The flash is 8mb. If IFD gets dump with ifdtool then I have this: 00000000:00000fff fd 00001000:00100fff res1 00101000:0010ffff pd 00110000:007fffff bios > One common issue is that people have IFD that uses 16mb and use FMAP that uses 8mb. > you can find some sample ifds in mainboard/intel/leafhill > ifds == *.fmd file that gets processed? >> Afterwards we tried to open the aforementioned coreboot.rom in >> FIT.exe. This was not possible however as the tool gave the error > > > This sounds like image was not stitched correctly, which is probably the root cause of the problem. > If I fit.exe could be more verbose about the problem I would knew where to dig. > Unfortunately I do not have time to help you debug this issue. > > My only recommendation would be to post on coreboot mailing list https://www.coreboot.org/Mailinglist > Please post there, somebody will help you out. > Lets hope for the best. > Hope that helps. > Andrey > > On Tue, Jan 15, 2019 at 3:52 AM Christian Gmeiner <christian.gmeiner(a)gmail.com> wrote: >> >> Hi Andrey >> >> Me and a colleague of mine are busy replacing the stock vendor BIOS on >> a board our employer gave us with coreboot. The board is equipped with >> an Apollolake CPU. >> >> I have found your presentation regarding coreboot and Apollolake >> (hxxps://www.coreboot.org/images/2/23/Apollolake_SoC.pdf) and did run >> into some problems. >> >> Let me give you a quick outline of what we did: >> >> We took an image from the stock vendor BIOS, removed the OEM signing >> stuff. We then replaced this with a key pair we created and were able >> to boot it. >> >> Attached to this email you can find the settings XML file we created >> in the process. >> >> We then took the outimage.bin created by the FIT.exe tool and >> configured it as the IFWI in the coreboot build process, as can be >> seen below: >> >> CONFIG_IFD_BIN_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" >> CONFIG_NEED_IFWI=y >> CONFIG_IFWI_FMAP_NAME="IFWI_CORE" >> CONFIG_IFWI_FILE_NAME="3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" >> CONFIG_HAVE_IFD_BIN=y >> >> We also took the first 4k from the image as the "descriptor.bin". >> >> The fmd file we came up with is visible below. >> >> 00000000:00000fff fd >> 00001000:00100fff res1 >> 00101000:0010ffff pd >> 00110000:007fffff bios >> >> FLASH 8M { >> SI_DESC@0x0 0x1000 >> DEVICE_EXTENSION@0x1000 0x10EFFF >> IFWI@0x110000 0x6f0000 { >> IFWI_CORE@0x0 0x2ff000 >> FMAP@0x2FF000 0x1000 >> RW_MRC_CACHE@0x300000 0x10000 >> COREBOOT(CBFS)@0x310000 0x100000 >> UNUSED_HOLE >> NOT_MEMORY_MAPPED@0x6B0000 0x40000 >> } >> } >> >> When generating a coreboot.rom image and flashing it to our BIOS flash >> chip, it wouldn't boot though. We didn't see any post codes at all, so >> the image is likely not even executed. >> >> Afterwards we tried to open the aforementioned coreboot.rom in >> FIT.exe. This was not possible however as the tool gave the error >> >> Error 30: Failed to decompose Full Image. >> Error 10: Failed to open with processed commands. >> Unable to open file: U:\Apollo Lake Intel(R) TXE >> 3.1.60.2280\Tools\FIT\WINDOWS\coreboot.bin. Reverting to default >> configuration. >> >> It seems that we made an error in process. Would you be so kind to >> have a look at this and point us in the right direction? >> >> -- >> Thanks a lot! >> -- >> Christian Gmeiner, MSc >> >> https://christian-gmeiner.info > > > > -- > Best regards, > Andrey Petrov -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info

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PCI tree topology regression
by Michal Zygowski Jan. 21, 2019

Jan. 21, 2019

Hello coreboot community, It seems like recent changes to PCI introduced regression. Building coreboot for PC Engines apu2 results in unbootable image halting at: get_pbus: dev is NULL! occuring in dev_finalize_chips during boot state machine write_table entry. I suspect it may be related to devicetree structure which is slightly different than on mainboards with Intel processors. Latest known working commit for me was cd26f08. Bisecting mentioned commit against current master (afe15f0) led me towards: ``` 8712aa107f4a4a0f64684e00c03eb2ec0d8baf6b device/pci_device: Do not break tree topology Fix regression introduced with commit ad7674e device: Introduce pcidev_on_root() and friends ... ``` Any ideas what can I do to fix it, or what is the cause? I would appreciate Your help. Best regards, -- Michał Żygowski Embedded Systems Engineer http://3mdeb.com | @3mdeb_com

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Configuration for Thinkpad T530
by Yannik Catalinac Jan. 19, 2019

Jan. 19, 2019

Hello, I'm trying to configure coreboot for a Lenovo Thinkpad T530 and I need help because for some parts I didn't find any information on the internet. The T530 (Machine Type Model: 24297ZG) has the the following specifications: Intel Core i5-3230M with Intel HD Graphics 4000 NVIDIA NVS 5400M AUO B156HW01 V.4 FullHD Display Samsung SSD 840 Pro 16 GB RAM I want to use a Docking Station. In the future I want to upgrade the following: Intel Core i7-3940XM more and faster RAM eGPU I'm going to install only some Linux distributions (no Windows). I think I will install OpenSuse which has a modified GRUB2 bootloader, where you can choose from which kernel or snapshot you would like to boot (maybe this information is important for configuring coreboot). Inside the Linux distribution, with graphical environment KDE, I would like to install some virtual machines with QEMU/kvm and there could be also a Windows virtual machine. I configured everything until now with 'make menuconfig' as listed bellow. Could you please give me some advise which settings I should change and why I should change them. I also wrote some questions behind a few configuration settings (marked with '#####') which I don`t understand. I would really appreciate your help. 1 General setup 1.1 () Local version string 1.2 (fallback) CBFS prefix to use 1.3 Compiler to use (GCC) 1.4 [ ] Allow building with any toolchain 1.5 [ ] Use ccache to speed up (re)compilation 1.6 [ ] Generate flashmap descriptor parser using flex and bison 1.7 [ ] Generate SCONFIG & BINCFG parser using flex and bison 1.8 [*] Use CMOS for configuration values 1.9 [ ] Load default configuration values into CMOS on each boot 1.10 [*] Compress ramstage with LZMA 1.11 [*] Include the coreboot .config file into the ROM image 1.12 [*] Create a table of timestamps collected during boot 1.13 [ ] Print the timestamp values on the console 1.14 [*] Allow use of binary-only repository 1.15 [ ] Code coverage support 1.16 [ ] Undefined behavior sanitizer support 1.17 [ ] Update existing coreboot.rom image 1.18 [ ] Add a bootsplash image 2 Mainboard 2.1 Mainboard Vendor 2.1.1 Lenovo 2.2 Mainboard model 2.2.1 TinkPad T530 2.3 ROM chip size 2.3.1 12 MB 2.4 (0x100000) Size of CBFS filesystem in ROM 2.5 () fmap description file in fmd format 3 Chipset 3.1 -*- Enable VMX for virtualization 3.2 [*] Set lock bit after configuring VMX 3.3 Include CPU microcode in CBFS (Generate from tree) 3.4 () Microcode binary path and filename 3.5 [*] Ignore vendor programmed fuses that limit max. DRAM frequency 3.6 [*] Ignore XMP profile max DIMMs per channel 3.7 Flash locking during chipset lockdown (Don't lock flash sections) 3.8 [*] Lock down chipset in coreboot 3.9 [*] Beep on fatal error 3.10 [*] Flash LEDs on fatal error 3.11 [*] Support bluetooth on wifi cards 3.13 [*] Add Intel descriptor.bin file 3.14 (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin) Path and filename of the descriptor.bin file 3.15 [*] Add Intel ME/TXE firmware 3.16 (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin) Path to management engine firmware 3.17 [*] Verify the integrity of the supplied ME/TXE firmware 3.18 [*] Strip down the Intel ME/TXE firmware 3.19 [*] Add gigabit ethernet firmware ##### If I read correctly I need that for internet connection and this bianry has just some configuration in it and no excecutable? So this should be not a privacy concerning thing? 3.20 (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/gbe.bin) Path to gigabit ethernet firmware 3.21 [*] Add EC firmware 3.22 (3rdparty/blobs/mainboard/$(MAINBOARDDIR)/ec.bin) Path to EC firmware 3.23 [*] Lock ME/TXE section 3.24 Bootblock behaviour (Always load fallback) 4 Devices 4.1 Graphics initialization (Use native graphics init) ---> 4.2 Display ---> Framebuffer mode (Legacy VGA text mode) ##### I have no idea what to choose here 4.3 [*] Enable PCIe Clock Power Management ##### I read it should increase battery runtime 4.4 [*] Enable PCIe ASPM L1 SubState ##### I read it should increase battery runtime 4.5 [ ] Early PCI bridge 4.6 (0x0000) Override PCI Subsystem Vendor ID ##### What?! 4.7 (0x0000) Override PCI Subsystem Device ID ##### And again: What?! 4.8 [*] Add a VGA BIOS image ##### I'm not sure if I need a VGA Option ROM. In which cases I need it? What disadvantage do I have if I do not integrate a VGA Option ROM? Will I see GRUB when I boot Linux? How could you value that binary in case of privacy and security? 4.9 (pci8086,0106.rom) VGA BIOS path and filename 4.10 (8086,0106) VGA device PCI IDs 4.11 [*] Add a Video Bios Table (VBT) binary to CBFS ##### Same questions as for the VGA BIOS image 4.12 (src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt) VBT binary path and filename 4.13 [ ] Enable I2C controller emulation in software 5 Generic Drivers 5.1 [ ] AS3722 RTC support 5.2 [ ] Enable protection on MRC settings 5.3 [ ] Disable Fast Read command 5.4 [ ] Serial port on SuperIO 5.5 [ ] Oxford OXPCIe952 5.6 (0x0) UART's PCI bus, device, function address ##### What is that? What I have to insert? 5.7 [ ] USB 2.0 EHCI debug dongle support 5.8 [ ] Support for Vital Product Data tables 5.9 [*] Support Intel PCI-e WiFi adapters ##### If enabled, will this include a binary in the coreboot image? 5.10 [*] PS/2 keyboard init 5.11 [ ] Silicon Image SIL3114 5.12 [ ] TI TPS65913 support 5.13 [ ] TI TPS65913 RTC support 6 Security 6.1 Verified Boot (vboot) ---> 6.2 Trusted Platform Module ---> [*] Deactivate TPM ##### I disabled it because of security/privacy reasons. Any disadvantages when I disable it? 6.2.2 [ ] Output verbose TPM debug messages 6.2.3 [ ] Enable Delay Workaround for TPM 7 Console 7.1 [*] Squelch AP CPUs from early console. 7.2 [ ] spkmodem (console on speaker) console output 7.3 [*] Use onboard VGA as primary video device ##### On coreboot mailinglist I read: make sure you enable ONBOARD_VGA_IS_PRIMARY in your config, otherwise your integrated graphics will be disabled and you'll lose eGPU hotplug. 7.4 [ ] Network console over NE2000 compatible Ethernet adapter 7.5 [*] Send console output to a CBMEM buffer 7.6 (0x20000) Room allocated for console output in CBMEM 7.7 [ ] SPI Flash console output 7.8 Default console log level (0: EMERG) ---> ##### I read that this should decrease boot time. What disadvantages do I have with this setting? 7.9 [ ] Don't show any POST codes ##### What? 7.10 [ ] Store post codes in CMOS for debugging ##### What? 7.11 [ ] Show POST codes on the debug console ##### What? 7.12 [*] Send POST codes to an external device ##### What? 7.13 Device to send POST codes to (None) ##### What? 7.14 [*] Send POST codes to an IO port ##### What? 7.15 (0x80) IO port for POST codes ##### What? 8 System tables 8.1 [*] Generate SMBIOS tables 9 Payload 9.1 Add a payload (SeaBIOS) ---> 9.2 SeaBIOS version (1.11.2) ---> ##### Or should I choose master? 9.3 (10) PS/2 keyboard controller initialization timeout (milliseconds) 9.4 [ ] Hardware init during option ROM execution 9.5 () SeaBIOS config file 9.6 () SeaBIOS bootorder file 9.7 [ ] Add SeaBIOS sercon-port file to CBFS 9.8 (-1) SeaBIOS debug level (verbosity) 9.9 [ ] Add a PXE ROM 9.10 Payload compression algorithm (Use LZMA compression for payloads) ---> 9.11 [ ] FIT support 9.12 [*] Use LZMA compression for secondary payloads 9.13 Secondary Payloads ---> 9.13.1 [*] Load coreinfo as a secondary payload 9.13.2 [ ] Load Memtest86+ as a secondary payload 9.13.3 [*] Load nvramcui as a secondary payload 9.13.4 [ ] Load tint as a secondary payload 10 Debugging 10.1 [ ] Halt when hitting a BUG() or assertion error 10.2 [ ] Output verbose CBFS debug messages 10.3 [ ] Output verbose RAM init debug messages 10.4 [ ] Output verbose SMBus debug messages 10.5 [ ] Output verbose SMI debug messages 10.6 [ ] Debug SMM relocation code 10.7 [ ] Output verbose SPI flash debug messages 10.8 [ ] Trace function calls 10.9 [ ] Debug boot state machine 10.10 [ ] Compile debug code in Ada sources 10.11 [ ] Configure image for EM100 usage Is there anything else I should take care of with a T530? Thanks for reading until here ;) Greetings

4 8

No GRUB/Graphical boot-output on x4x chipset series with PCIe GPU
by akjuxr3＠dismail.de Jan. 19, 2019

Jan. 19, 2019

I have installed coreboot on 2 different x4x boards. Both with intel G41 chipset and attached GPU to the PCIe slot (so probably not an issue with missing gpu-bios file because the gpu-bios of the PCIe card is been used). Work-timeline: 1. I got a clean ssd and installed linux on it using the OEM bios. The typical graphical Grub output was visable and i was able to change configuration in it by pressing 'e' at boot. 2. I used this installed linux and git cloned coreboot (today), built everything and flashed with flashrom the coreboot image. 3. Turned the computer fully off. Turned it on and grub graphical output is gone. I have this issue since i can think of it. How i build coreboot: make menuconfig, choose mainboard-vendor, mainboard model, press esc and confirm saving. Then build.

3 6

Coreboot hangs with post code 0x26 - Infinit loop in cache_as_ram.S (Intel Atom denverton_ns)
by dponamorev＠gmail.com Jan. 18, 2019

Jan. 18, 2019

Motherboard with Intel Atom Denverton C3538 Stepping B1 processor. I configured Intel FSP (FSP_M and FSP_S, FSP_T did not use - is it needed at all?). Integrate FSP_M & FSP_S to coreboot 4.9 (intel/harcuvar or Scaleway/tagada same behavior). I copied the header files from the FSP package to the coreboot /home/dubel/Work/2019/coreboot-4.9/src/vendorcode/intel/fsp/fsp2_0/denverton_ns and I had to change the type name of FSP_M_СONFIG to FSPM_СONFIG (as in Intel FSP header files) in some coreboot files. Compiled coreboot, added descritor region + intel me region and flash it. Coreboot hangs with post code 0x26 Infinit loop in /home/dubel/Work/2019/coreboot-4.9/src/soc/intel/common/block/cpu/car/cache_as_ram.S (Create n-way set associativity of cache (find_llc_subleaf)). What coreboot settings (.config) can lead to such consequences? What can cause this behavior? #elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED) .global car_nem_enhanced car_nem_enhanced: /* Disable cache eviction (setup stage) */ mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr post_code(0x26) /* Create n-way set associativity of cache */ xorl %edi, %edi find_llc_subleaf: movl %edi, %ecx movl $0x04, %eax cpuid inc %edi and $0xe0, %al /* EAX[7:5] = Cache Level */ cmp $0x60, %al /* Check to see if it is LLC */ jnz find_llc_subleaf My .config file: # # Automatically generated file; DO NOT EDIT. # coreboot configuration # # # General setup # CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set # CONFIG_UTIL_GENPARSER is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_TIMESTAMPS_ON_CONSOLE is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set # CONFIG_UBSAN is not set # CONFIG_NO_RELOCATABLE_RAMSTAGE is not set CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # # # Important: Run 'make distclean' before switching boards # # CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set # CONFIG_VENDOR_AOPEN is not set # CONFIG_VENDOR_APPLE is not set # CONFIG_VENDOR_ASROCK is not set # CONFIG_VENDOR_ASUS is not set # CONFIG_VENDOR_AVALUE is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_CAVIUM is not set # CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set # CONFIG_VENDOR_FACEBOOK is not set # CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set # CONFIG_VENDOR_GOOGLE is not set # CONFIG_VENDOR_HP is not set # CONFIG_VENDOR_IBASE is not set # CONFIG_VENDOR_IEI is not set CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_JETWAY is not set # CONFIG_VENDOR_KONTRON is not set # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LIPPERT is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_OCP is not set # CONFIG_VENDOR_OPENCELLULAR is not set # CONFIG_VENDOR_PACKARDBELL is not set # CONFIG_VENDOR_PCENGINES is not set # CONFIG_VENDOR_PURISM is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set # CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SCALEWAY is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SIFIVE is not set # CONFIG_VENDOR_SUPERMICRO is not set # CONFIG_VENDOR_TI is not set # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="intel/harcuvar" CONFIG_MAINBOARD_PART_NUMBER="Harcuvar CRB" CONFIG_MAX_CPUS=16 CONFIG_CBFS_SIZE=0x200000 CONFIG_PAYLOAD_CONFIGFILE="" CONFIG_MAINBOARD_VENDOR="Intel" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" CONFIG_DEVICETREE="devicetree.cb" CONFIG_POST_IO=y CONFIG_DCACHE_RAM_BASE=0xfef00000 CONFIG_DCACHE_RAM_SIZE=0x100000 CONFIG_MAX_REBOOT_CNT=3 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 CONFIG_FMDFILE="" CONFIG_C_ENV_BOOTBLOCK_SIZE=0x8000 CONFIG_DCACHE_BSP_STACK_SIZE=0x10000 CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 CONFIG_HAVE_INTEL_FIRMWARE=y CONFIG_POST_DEVICE=y # CONFIG_DRIVERS_UART_8250IO is not set # CONFIG_VBOOT is not set CONFIG_OVERRIDE_DEVICETREE="" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set # CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set # CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set # CONFIG_BOARD_INTEL_CAMELBACKMOUNTAIN_FSP is not set # CONFIG_BOARD_INTEL_CANNONLAKE_RVPU is not set # CONFIG_BOARD_INTEL_CANNONLAKE_RVPY is not set # # Coffeelake RVP # # CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set # CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set # CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set # CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set # CONFIG_BOARD_INTEL_D510MO is not set # CONFIG_BOARD_INTEL_D945GCLF is not set # CONFIG_BOARD_INTEL_DCP847SKE is not set # CONFIG_BOARD_INTEL_DG41WV is not set # CONFIG_BOARD_INTEL_DG43GT is not set # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set # CONFIG_BOARD_INTEL_GALILEO is not set # CONFIG_BOARD_INTEL_GLKRVP is not set CONFIG_BOARD_INTEL_HARCUVAR=y # CONFIG_BOARD_INTEL_ICELAKE_RVPU is not set # CONFIG_BOARD_INTEL_ICELAKE_RVPY is not set # CONFIG_BOARD_INTEL_KBLRVP3 is not set # CONFIG_BOARD_INTEL_KBLRVP7 is not set # CONFIG_BOARD_INTEL_KBLRVP8 is not set # CONFIG_BOARD_INTEL_KUNIMITSU is not set # CONFIG_BOARD_INTEL_LEAFHILL is not set # CONFIG_BOARD_INTEL_LITTLEPLAINS is not set # CONFIG_BOARD_INTEL_MINNOW3 is not set # CONFIG_BOARD_INTEL_MINNOWMAX is not set # CONFIG_BOARD_INTEL_MOHONPEAK is not set # CONFIG_BOARD_INTEL_SKLSDLBRK is not set # CONFIG_BOARD_INTEL_STRAGO is not set # CONFIG_BOARD_INTEL_WTM2 is not set CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Harcuvar CRB" # CONFIG_BOARD_INTEL_BASEBOARD_GLKRVP is not set # CONFIG_ENABLE_FSP_MEMORY_DOWN is not set # CONFIG_HAVE_IFD_BIN is not set CONFIG_ADD_FSP_BINARIES=y CONFIG_FSP_M_FILE="./FSP/FSP_M.rom" CONFIG_FSP_S_FILE="./FSP/FSP_S.rom" CONFIG_FSP_S_CBFS="fsps.bin" CONFIG_FSP_M_CBFS="fspm.bin" CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7 CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set # CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_CPU_MICROCODE_CBFS_LEN=0x0ff80 CONFIG_CPU_MICROCODE_CBFS_LOC=0xfff20040 CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03 CONFIG_BOARD_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set # CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set # # Chipset # # # SoC # CONFIG_CPU_SPECIFIC_OPTIONS=y CONFIG_HEAP_SIZE=0x4000 CONFIG_SMM_TSEG_SIZE=0x200000 CONFIG_SMM_RESERVED_SIZE=0x000000 CONFIG_SMM_MODULE_STACK_SIZE=0x400 CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_CAVIUM_CN81XX is not set CONFIG_ARCH_ARMV8_EXTENSION=0 CONFIG_STACK_SIZE=0x1000 # CONFIG_SOC_CAVIUM_COMMON is not set # CONFIG_SOC_INTEL_GLK is not set CONFIG_PCR_BASE_ADDRESS=0xfd000000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 CONFIG_FSP_M_ADDR=0xfff32000 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y CONFIG_CPU_BCLK_MHZ=100 # CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set # CONFIG_PCIEXP_ASPM is not set # CONFIG_PCIEXP_COMMON_CLOCK is not set # CONFIG_PCIEXP_CLK_PM is not set # CONFIG_SOC_INTEL_COFFEELAKE is not set # CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set CONFIG_SOC_INTEL_DENVERTON_NS=y CONFIG_FSP_S_ADDR=0xfffc3000 CONFIG_IQAT_ENABLE=y CONFIG_IQAT_MEMORY_REGION_SIZE=0x100000 CONFIG_HSUART_DEV=0x1a # CONFIG_NON_LEGACY_UART_MODE is not set CONFIG_LEGACY_UART_MODE=y CONFIG_DENVERTON_NS_CAR_NEM_ENHANCED=y CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x8000d000 # CONFIG_SOC_INTEL_KABYLAKE is not set CONFIG_SOC_INTEL_COMMON=y # # Intel SoC Common Code # CONFIG_SOC_INTEL_COMMON_BLOCK=y CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y # CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT is not set CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y # CONFIG_INTEL_CAR_NEM is not set # CONFIG_INTEL_CAR_CQOS is not set CONFIG_INTEL_CAR_NEM_ENHANCED=y # CONFIG_SOC_INTEL_COMMON_BLOCK_CSE is not set CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 is not set CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y CONFIG_PCR_COMMON_IOSF_1_0=y CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y # CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set CONFIG_POWER_STATE_ON_AFTER_FAILURE=y # CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set # CONFIG_PMC_INVALID_READ_AFTER_WRITE is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_ESPI_ACPI_DIS is not set CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0 CONFIG_SA_PCIEX_LENGTH=0x10000000 # CONFIG_SA_ENABLE_IMR is not set # CONFIG_SA_ENABLE_DPR is not set # CONFIG_SOC_INTEL_COMMON_BLOCK_VMX is not set # # Intel SoC Common PCH Code # # # Intel SoC Common coreboot stages # # CONFIG_DISPLAY_SMM_MEMORY_MAP is not set CONFIG_SOC_INTEL_COMMON_RESET=y # CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE is not set # CONFIG_ACPI_CONSOLE is not set # CONFIG_SOC_INTEL_COMMON_ACPI is not set # CONFIG_SOC_INTEL_COMMON_ACPI_EC_PTS_WAK is not set # CONFIG_SOC_INTEL_COMMON_NHLT is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_MEDIATEK_MT8183 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_QUALCOMM_SDM845 is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set # CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set # # CPU # # CONFIG_CPU_ALLWINNER_A10 is not set CONFIG_XIP_ROM_SIZE=0x10000 CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set # CONFIG_SSE2 is not set # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set CONFIG_PARALLEL_MP=y # CONFIG_PARALLEL_MP_AP_WORK is not set # CONFIG_UDELAY_IO is not set # CONFIG_UDELAY_LAPIC is not set CONFIG_UDELAY_TSC=y CONFIG_TSC_CONSTANT_RATE=y CONFIG_TSC_MONOTONIC_TIMER=y # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y # CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y CONFIG_SMM_TSEG=y CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 CONFIG_SMM_STUB_STACK_SIZE=0x400 # CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set # CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y CONFIG_NO_CAR_GLOBAL_MIGRATION=y CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 # CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set # CONFIG_USES_MICROCODE_HEADER_FILES is not set # CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set CONFIG_CPU_MICROCODE_CBFS_NONE=y # # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set # CONFIG_NORTHBRIDGE_AMD_PI is not set CONFIG_MAX_PIRQ_LINKS=4 # # Southbridge # # CONFIG_AMD_SB_CIMX is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set # CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y # CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # # CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # # CONFIG_EC_GOOGLE_WILCO is not set CONFIG_EC_BASE_ACPI_DATA=0x930 CONFIG_EC_BASE_ACPI_COMMAND=0x934 CONFIG_EC_BASE_HOST_DATA=0x940 CONFIG_EC_BASE_HOST_COMMAND=0x944 CONFIG_EC_BASE_PACKET=0x950 CONFIG_SEABIOS_PS2_TIMEOUT=0 # # Intel Firmware # # CONFIG_CAVIUM_BDK is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set # CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set CONFIG_UDK_2015_BINDING=y # CONFIG_UDK_2017_BINDING is not set CONFIG_UDK_2013_VERSION=2013 CONFIG_UDK_2015_VERSION=2015 CONFIG_UDK_2017_VERSION=2017 CONFIG_UDK_VERSION=2015 # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set # CONFIG_ARCH_ROMSTAGE_ARM is not set # CONFIG_ARCH_RAMSTAGE_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set # CONFIG_ARCH_VERSTAGE_ARMV4 is not set # CONFIG_ARCH_ROMSTAGE_ARMV4 is not set # CONFIG_ARCH_RAMSTAGE_ARMV4 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set # CONFIG_ARCH_VERSTAGE_ARMV7 is not set # CONFIG_ARCH_ROMSTAGE_ARMV7 is not set # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set # CONFIG_ARCH_VERSTAGE_ARMV7_R is not set # CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set # CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set # CONFIG_ARCH_VERSTAGE_ARM64 is not set # CONFIG_ARCH_ROMSTAGE_ARM64 is not set # CONFIG_ARCH_RAMSTAGE_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set # CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set # CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set # CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set # CONFIG_ARM64_USE_ARCH_TIMER is not set # CONFIG_ARM64_A53_ERRATUM_843419 is not set # CONFIG_ARCH_MIPS is not set # CONFIG_ARCH_BOOTBLOCK_MIPS is not set # CONFIG_ARCH_VERSTAGE_MIPS is not set # CONFIG_ARCH_ROMSTAGE_MIPS is not set # CONFIG_ARCH_RAMSTAGE_MIPS is not set # CONFIG_ARCH_PPC64 is not set # CONFIG_ARCH_BOOTBLOCK_PPC64 is not set # CONFIG_ARCH_VERSTAGE_PPC64 is not set # CONFIG_ARCH_ROMSTAGE_PPC64 is not set # CONFIG_ARCH_RAMSTAGE_PPC64 is not set # CONFIG_ARCH_RISCV is not set # CONFIG_ARCH_BOOTBLOCK_RISCV is not set # CONFIG_ARCH_VERSTAGE_RISCV is not set # CONFIG_ARCH_ROMSTAGE_RISCV is not set # CONFIG_ARCH_RAMSTAGE_RISCV is not set # CONFIG_RISCV_USE_ARCH_TIMER is not set CONFIG_ARCH_X86=y CONFIG_ARCH_BOOTBLOCK_X86_32=y CONFIG_ARCH_VERSTAGE_X86_32=y CONFIG_ARCH_ROMSTAGE_X86_32=y CONFIG_ARCH_POSTCAR_X86_32=y CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_BOOTBLOCK_X86_64 is not set # CONFIG_ARCH_VERSTAGE_X86_64 is not set # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_POSTCAR_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set CONFIG_RAMBASE=0xe00000 CONFIG_RAMTOP=0x1000000 # CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set # CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set # CONFIG_HPET_ADDRESS_OVERRIDE is not set CONFIG_HPET_ADDRESS=0xfed00000 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POSTCAR_STAGE=y # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set CONFIG_BOOTBLOCK_SIMPLE=y # CONFIG_BOOTBLOCK_NORMAL is not set CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set CONFIG_COLLECT_TIMESTAMPS_TSC=y # CONFIG_PAGING_IN_CACHE_AS_RAM is not set # CONFIG_IDT_IN_EVERY_STAGE is not set CONFIG_HAVE_CF9_RESET=y # # Devices # CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y # CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set # CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set CONFIG_VGA_ROM_RUN=y # CONFIG_NO_GFX_INIT is not set # CONFIG_ALWAYS_LOAD_OPROM is not set # CONFIG_ON_DEVICE_ROM_LOAD is not set CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y # CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set # # Display # # CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set CONFIG_VGA_TEXT_FRAMEBUFFER=y # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set CONFIG_PCI=y # CONFIG_NO_MMCONF_SUPPORT is not set CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_INTEL_GMA_ADD_VBT is not set # CONFIG_SOFTWARE_I2C is not set # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set # CONFIG_ELOG is not set # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set CONFIG_CACHE_MRC_SETTINGS=y CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000 # CONFIG_MRC_SETTINGS_PROTECT is not set # CONFIG_HAS_RECOVERY_MRC_CACHE is not set # CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN is not set # CONFIG_MRC_SETTINGS_VARIABLE_DATA is not set # CONFIG_MRC_WRITE_NV_LATE is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SMMSTORE is not set # CONFIG_SMMSTORE_IN_CBFS is not set CONFIG_SPI_FLASH=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y # CONFIG_SPI_FLASH_NO_FAST_READ is not set CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set # CONFIG_DRIVERS_UART_8250MEM_32 is not set # CONFIG_HAVE_UART_SPECIAL is not set # CONFIG_DRIVERS_UART_OXPCIE is not set # CONFIG_DRIVERS_UART_PL011 is not set # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set # CONFIG_HAVE_USBDEBUG is not set # CONFIG_HAVE_USBDEBUG_OPTIONS is not set # CONFIG_VPD is not set # CONFIG_DRIVERS_AMD_PI is not set # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set # CONFIG_DRIVERS_I2C_MAX98373 is not set # CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCA9538 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set # CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set # CONFIG_DRIVERS_I2C_RX6110SA is not set # CONFIG_DRIVERS_I2C_SX9310 is not set # CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set # CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set # CONFIG_DISPLAY_HOBS is not set # CONFIG_DISPLAY_UPD_DATA is not set CONFIG_CHECKLIST_DATA_FILE_LOCATION="src/vendorcode/intel/fsp/fsp2_0/checklist" CONFIG_PLATFORM_USES_FSP2_0=y # CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set # CONFIG_DISPLAY_FSP_HEADER is not set # CONFIG_FSP_CAR is not set # CONFIG_FSP_M_XIP is not set # CONFIG_FSP_T_XIP is not set # CONFIG_FSP_USES_CB_STACK is not set # CONFIG_VERIFY_HOBS is not set # CONFIG_DISPLAY_FSP_VERSION_INFO is not set # CONFIG_INTEL_DDI is not set # CONFIG_INTEL_EDID is not set # CONFIG_INTEL_INT15 is not set # CONFIG_INTEL_GMA_ACPI is not set # CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set # CONFIG_INTEL_GMA_SWSMISCI is not set # CONFIG_DRIVER_INTEL_I210 is not set # CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set CONFIG_DRIVERS_INTEL_WIFI=y # CONFIG_USE_SAR is not set # CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_LPC_TPM is not set # CONFIG_MAINBOARD_HAS_LPC_TPM is not set # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set # CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set # CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVERS_USB_ACPI is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set # CONFIG_COMMONLIB_STORAGE is not set # # Security # # # Verified Boot (vboot) # # # Trusted Platform Module # CONFIG_USER_NO_TPM=y # CONFIG_ACPI_SATA_GENERATOR is not set CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y # CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set # CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y # CONFIG_RTC is not set # # Console # CONFIG_BOOTBLOCK_CONSOLE=y CONFIG_POSTCAR_CONSOLE=y CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set # CONFIG_CONSOLE_SPI_FLASH is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set # CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set CONFIG_HWBASE_DEBUG_CB=y # CONFIG_HAVE_ACPI_RESUME is not set # CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set CONFIG_HAVE_MONOTONIC_TIMER=y # CONFIG_GENERIC_UDELAY is not set # CONFIG_TIMER_QUEUE is not set # CONFIG_HAVE_OPTION_TABLE is not set # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y # CONFIG_USE_WATCHDOG_ON_BOOT is not set # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y # CONFIG_COMMON_FADT is not set # CONFIG_ACPI_NHLT is not set # # System tables # # CONFIG_GENERATE_MP_TABLE is not set # CONFIG_GENERATE_PIRQ_TABLE is not set CONFIG_GENERATE_SMBIOS_TABLES=y # # Payload # # CONFIG_PAYLOAD_NONE is not set # CONFIG_PAYLOAD_ELF is not set # CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_LINUXBOOT is not set CONFIG_PAYLOAD_SEABIOS=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_YABITS is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" CONFIG_SEABIOS_STABLE=y # CONFIG_SEABIOS_MASTER is not set # CONFIG_SEABIOS_REVISION is not set # CONFIG_SEABIOS_THREAD_OPTIONROMS is not set CONFIG_SEABIOS_BOOTORDER_FILE="" # CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set CONFIG_SEABIOS_DEBUG_LEVEL=-1 # # Using default SeaBIOS log level # CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set # CONFIG_PAYLOAD_FIT_SUPPORT is not set CONFIG_COMPRESS_SECONDARY_PAYLOAD=y # # Secondary Payloads # # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set # CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set # CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging # # # CPU Debug Settings # CONFIG_HAVE_DISPLAY_MTRRS=y # CONFIG_DISPLAY_MTRRS is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # # General Debug Settings # # CONFIG_FATAL_ASSERTS is not set CONFIG_HAVE_DEBUG_GPIO=y CONFIG_DEBUG_GPIO=y # CONFIG_DEBUG_CBFS is not set # CONFIG_HAVE_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_REALMODE_DEBUG is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set # CONFIG_DEBUG_ADA_CODE is not set # CONFIG_HAVE_EM100_SUPPORT is not set CONFIG_NO_EDID_FILL_FB=y # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set # CONFIG_NO_XIP_EARLY_STAGES is not set CONFIG_EARLY_CBMEM_INIT=y # CONFIG_EARLY_CBMEM_LIST is not set CONFIG_RELOCATABLE_MODULES=y CONFIG_NO_STAGE_CACHE=y CONFIG_C_ENVIRONMENT_BOOTBLOCK=y

1 0

How do I install a patch for the w520 to use Displayport/VGA output?
by surfbro＠tuta.io Jan. 17, 2019

Jan. 17, 2019

I've installed Coreboot to a number of my Thinkpad machines, but I have no experience installing patches post installation. I'm trying to get the Displayport/VGA output to function on my now corebooted w520. https://www.coreboot.org/Board:lenovo/w520#VGA_.2F_DisplayPort_output <https://www.coreboot.org/Board:lenovo/w520#VGA_.2F_DisplayPort_output> The official coreboot guide says there's a patch to install to get these to work. Is it possible to put it in layman's terms so that I can get these working, I really really want to use my projector, so this would be so much help! I installed coreboot on my w520 myself so if it's similar to that process I believe I can get it done. Thanks Coreboot team.

3 2

Google Summer of Code 2019
by Patrick Georgi Jan. 17, 2019

Jan. 17, 2019

Dear coreboot community, I'm preparing the application to have coreboot participate in this year's Google Summer of Code. There are two things we should think about until early February for this: 1. We'll need some project proposals, for which I started https://review.coreboot.org/c/coreboot/+/30972 2. I need to specify the number of mentors we expect to have at hands. This needn't be a guaranteed commitment, but a rough idea would be good. As a mentor-candidate, if we make it into GSoC, we'd try to match you to a student with a project matching your interest and knowledge. You'd discuss their plan, follow up at least weekly on their progress and support them in their process to join and grow in the community. The time frame would be early May to early September: https://developers.google.com/open-source/gsoc/timeline. So if you're interested in growing our community, please speak up :-) Thanks, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

2 2

Manual microcode update for G505s still needed? e.a.
by Anac Jan. 16, 2019

Jan. 16, 2019

Dear all, Now with Coreboot version 4.9, is it still recommended to manually update AMD microcodes for Lenovo G505s as described here? Or is Coreboot 4.9 up-to-date for using a G505s as a Qubes station? http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#AMD_microcode_upda… How do you handle the AMD GPU AtomBIOS blobs? https://github.com/g505s-opensource-researcher/g505s-atombios#corebootrom-o… may be very clear to experts, but I don't get it. It reads "use one of these commands:" 1) Adding VGABIOS to coreboot.rom 2) Removing VGABIOS from coreboot.rom 3) Printing coreboot.rom memory map Which one should I use? Probably No.1. But there are 2 files for my G505S with discrete HD-8570M (pci1002,990b.rom and pci1002,6663.rom). Which one should I add? Both, separated by space? Then the command would look like that? ./util/cbfstool/cbfstool ~/coreboot.rom add -f ~/pci1002,990b.rom pci1002,6663.rom -n pci****,****.rom -t optionrom That looks odd. Doesn't it? What about TPM? Qubes recommends TPM in their system requirements since it is required for 'Anti Evil Maid'. But Coreboot configuration (make nconfig) does not allow to activate TPM. Am I doing something wrong or is TPM just really not an option? Best regards and thank you! Anac

2 3

To modify MCTRL.SPDDIS of Intel Denvertion in coreboot
by Hilbert Tu(杜睿哲_Pegatron) Jan. 15, 2019

Jan. 15, 2019

Hi, Is there anyone can tell me how to change MCTRL.SPDDIS in Coreboot? The Intel Denverton blocks write permission to address A0~AE due to security concern of DIMM SPD, but this also restricts the write access to generic EEPROM access in our platform. So I need to modify the SPDDIS bit to bypass the protection. But I don’t know how to do that in Coreboot. Please help and thanks in advance. -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

2 1

Coreboot build process with gcc 8.1
by Salvatore Bellizzi Jan. 11, 2019

Jan. 11, 2019

Hi, I have a question reguarding the build process. Since crossgcc has been updated and gcc is now at version 8.1 I always encounter an error when building coreboot: coreboot/src/console/vtxprintf.c:102: undefined reference to '__udivmoddi4' Since coreboot uses crossgcc and its own libgcc libraries, I figured that the __udivmoddi4 function has not yet been implemented. Anyway I have incurred in this failure several times and even with the latest 4.9 release. Shouldn't I be able to build at least this latest release using unmodified crossgcc or am I missing something else? thanks, salvatore

2 2