coreboot June 2017

coreboot@coreboot.org

57 participants
159 discussions

Dell Precision M4600 support
by Valentine Levshuk 09 Jun '17

09 Jun '17

1. Dell Precision M4600 laptop: -- CPU: Intel Core i7-2860QM -- SouthBridge: Intel Cougar Point QM67 -- NorthBridge: Intel Sandy Bridge-MB IMC -- MXM 3.0a graphics slot, 2x Mini Pci-e, 1x Mini Pci-e combined with mSATA, 1x Expresscard slot. 1. “lspci -tvnn” output: -[0000:00]-+-00.0 Intel Corporation 2nd Generation Core Processor Family DRAM Controller [8086:0104] +-01.0-[01]--+-00.0 Advanced Micro Devices, Inc. [AMD/ATI] Venus XTX [Radeon HD 8890M / R9 M275X/M375X] [1002:6820] | \-00.1 Advanced Micro Devices, Inc. [AMD/ATI] Cape Verde/Pitcairn HDMI Audio [Radeon HD 7700/7800 Series] [1002:aab0] +-16.0 Intel Corporation 6 Series/C200 Series Chipset Family MEI Controller #1 [8086:1c3a] +-16.3 Intel Corporation 6 Series/C200 Series Chipset Family KT Controller [8086:1c3d] +-19.0 Intel Corporation 82579LM Gigabit Network Connection [8086:1502] +-1a.0 Intel Corporation 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #2 [8086:1c2d] +-1b.0 Intel Corporation 6 Series/C200 Series Chipset Family High Definition Audio Controller [8086:1c20] +-1c.0-[02]-- +-1c.2-[03-08]-- +-1c.3-[09]----00.0 NEC Corporation uPD720200 USB 3.0 Host Controller [1033:0194] +-1c.4-[0a]----00.0 Broadcom Limited BCM4360 802.11ac Wireless Network Adapter [14e4:43a0] +-1c.7-[0b-12]--+-00.0 O2 Micro, Inc. OZ600 1394a-2000 Controller [1217:11f7] | +-00.1 O2 Micro, Inc. OZ600RJ1/OZ900RJ1 SD/MMC Card Reader Controller [1217:8320] | \-00.2 O2 Micro, Inc. OZ600 MS/xD Controller [1217:8330] +-1d.0 Intel Corporation 6 Series/C200 Series Chipset Family USB Enhanced Host Controller #1 [8086:1c26] +-1f.0 Intel Corporation QM67 Express Chipset Family LPC Controller [8086:1c4f] +-1f.2 Intel Corporation 82801 Mobile SATA Controller [RAID mode] [8086:282a] \-1f.3 Intel Corporation 6 Series/C200 Series Chipset Family SMBus Controller [8086:1c22] 1. Superiotools found SMSC FDC37C93xFR 2. Winbond SOIC8 soldered two flash chips: 1x 8Mb and 1x2Mb – 10240 Kb in total 3. Motherboard schematics: https://1drv.ms/b/s!AooKL5SiajFyioJPEP1Jla85VqPy3w

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Re: [coreboot] Coreboot + Seabios Asus F2A85-M LE card
by Piotr Kubaj 09 Jun '17

09 Jun '17

https://www.coreboot.org/VGA_support On 17-06-08 11:01:55, Gabriel Bosque wrote: > Internal. Where do I find firmware for it? > > Tanks in advance > > 2017-06-08 10:45 GMT-03:00 Piotr Kubaj <pkubaj(a)anongoth.pl>: > > > Do you use the internal GPU or external? If you use internal, you probably > > need firmware from AMD (SeaVGABIOS won't work). If you have external GPU, > > you don't need VGA option ROM at all. > > > > Anyway, you don't need SeaVGABIOS. > > > > You also put CONFIG_QEMU_HARDWARE=y, which is unnecessary. > > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner, and is > believed to be clean. > -- ____________________________________ / No matter where I go, the place is \ \ always called "here". / ------------------------------------ \ ^__^ \ (oo)\_______ (__)\ )\/\ ||----w | || ||

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 09 Jun '17

09 Jun '17

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1375986: (NEGATIVE_RETURNS) /src/mainboard/google/link/i915.c: 281 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 287 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 291 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 297 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 304 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 310 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 315 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 318 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 324 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 329 in i915lightup_sandy() /src/mainboard/google/link/i915.c: 332 in i915lightup_sandy() ________________________________________________________________________________________________________ *** CID 1375986: (NEGATIVE_RETURNS) /src/mainboard/google/link/i915.c: 281 in i915lightup_sandy() 275 vsync = (mode->va + mode->vso - 1) | 276 ((mode->va + mode->vso + mode->vspw - 1) << 16); 277 printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync); 278 279 printk(BIOS_SPEW, "Table has %d elements\n", niodefs); 280 >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 281 index = run(0); 282 printk(BIOS_SPEW, "Run returns %d\n", index); 283 auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe; 284 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14); 285 auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; 286 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); /src/mainboard/google/link/i915.c: 287 in i915lightup_sandy() 281 index = run(0); 282 printk(BIOS_SPEW, "Run returns %d\n", index); 283 auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_DPCD_REV << 8|0xe; 284 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14); 285 auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; 286 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 287 index = run(index); 288 printk(BIOS_SPEW, "Run returns %d\n", index); 289 auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; 290 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); 291 index = run(index); 292 printk(BIOS_SPEW, "Run returns %d\n", index); /src/mainboard/google/link/i915.c: 291 in i915lightup_sandy() 285 auxout[0] = 0 << 31 /* i2c */|1 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; 286 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); 287 index = run(index); 288 printk(BIOS_SPEW, "Run returns %d\n", index); 289 auxout[0] = 0 << 31 /* i2c */|0 << 30|0x0 << 28/*W*/|0x0 << 8|0x0; 290 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 291 index = run(index); 292 printk(BIOS_SPEW, "Run returns %d\n", index); 293 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0; 294 auxout[1] = 0x01000000; 295 /* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */ 296 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); /src/mainboard/google/link/i915.c: 297 in i915lightup_sandy() 291 index = run(index); 292 printk(BIOS_SPEW, "Run returns %d\n", index); 293 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_SET_POWER << 8|0x0; 294 auxout[1] = 0x01000000; 295 /* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */ 296 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 297 index = run(index); 298 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8; 299 auxout[1] = 0x0a840000; 300 /*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/ 301 auxout[2] = 0x00000000; 302 auxout[3] = 0x01000000; /src/mainboard/google/link/i915.c: 304 in i915lightup_sandy() 298 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8; 299 auxout[1] = 0x0a840000; 300 /*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/ 301 auxout[2] = 0x00000000; 302 auxout[3] = 0x01000000; 303 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0); >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 304 index = run(index); 305 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; 306 auxout[1] = 0x21000000; 307 /* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE | 308 * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/ 309 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); /src/mainboard/google/link/i915.c: 310 in i915lightup_sandy() 304 index = run(index); 305 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; 306 auxout[1] = 0x21000000; 307 /* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE | 308 * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/ 309 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 310 index = run(index); 311 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; 312 auxout[1] = 0x00000000; 313 /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ 314 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); 315 index = run(index); /src/mainboard/google/link/i915.c: 315 in i915lightup_sandy() 309 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); 310 index = run(index); 311 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; 312 auxout[1] = 0x00000000; 313 /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ 314 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 315 index = run(index); 316 auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; 317 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); 318 index = run(index); 319 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; 320 auxout[1] = 0x22000000; /src/mainboard/google/link/i915.c: 318 in i915lightup_sandy() 312 auxout[1] = 0x00000000; 313 /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ 314 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); 315 index = run(index); 316 auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; 317 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 318 index = run(index); 319 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; 320 auxout[1] = 0x22000000; 321 /* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE | 322 * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/ 323 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); /src/mainboard/google/link/i915.c: 324 in i915lightup_sandy() 318 index = run(index); 319 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; 320 auxout[1] = 0x22000000; 321 /* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE | 322 * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/ 323 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 324 index = run(index); 325 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; 326 auxout[1] = 0x00000000; 327 /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ 328 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); 329 index = run(index); /src/mainboard/google/link/i915.c: 329 in i915lightup_sandy() 323 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); 324 index = run(index); 325 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3; 326 auxout[1] = 0x00000000; 327 /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ 328 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 329 index = run(index); 330 auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; 331 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); 332 index = run(index); 333 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; 334 auxout[1] = 0x00000000; /src/mainboard/google/link/i915.c: 332 in i915lightup_sandy() 326 auxout[1] = 0x00000000; 327 /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ 328 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); 329 index = run(index); 330 auxout[0] = 1 << 31 /* dp */|0x1 << 28/*R*/|DP_LANE0_1_STATUS << 8|0x5; 331 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); >>> CID 1375986: (NEGATIVE_RETURNS) >>> Assigning: signed variable "index" = "run". 332 index = run(index); 333 auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0; 334 auxout[1] = 0x00000000; 335 /* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | 336 * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/ 337 intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); ** CID 1375985: Null pointer dereferences (FORWARD_NULL) /src/mainboard/google/link/i915.c: 179 in run() ________________________________________________________________________________________________________ *** CID 1375985: Null pointer dereferences (FORWARD_NULL) /src/mainboard/google/link/i915.c: 179 in run() 173 break; 174 case R: 175 u = READ32(id->addr); 176 if (verbose & vio) 177 printk(BIOS_SPEW, "\texpect %08lx\n", id->data); 178 /* we're looking for something. */ >>> CID 1375985: Null pointer dereferences (FORWARD_NULL) >>> Dereferencing null pointer "lastidread". 179 if (lastidread->addr == id->addr){ 180 /* they're going to be polling. 181 * just do it 1000 times 182 */ 183 for (t = 0; t < 1000 && id->data != u; t++){ 184 u = READ32(id->addr); ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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Yet another gerrit update (2.14.1)
by Patrick Georgi 09 Jun '17

09 Jun '17

Hi everybody, I just updated our gerrit instance, which should fix a number of performance related regressions. Since there were requests for supporting ecdsa and ed25519 keys in gerrit's ssh interface, I also want to point out that 2.14 brought support for them. I didn't mention it because it was known to be broken, but 2.14.1 is supposed to fix it, so feel free to use it now. Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle

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Re: [coreboot] riscv: How to debug (王翔)
by 王翔 09 Jun '17

09 Jun '17

On Friday,June 9, 2017 9:17 AM, Jonathan Neuschäfer wrote: >On Thu, Jun 08, 2017 at 05:32:31PM +0800, 王翔 wrote: >> I try to debug coreboot with **spike**. >> I has apply the **8250 usart patch** to **spike**. >I haven't updated the patches at [1] in a while. Please check if the two >patches in [2] work for you if you also apply the following patch to >coreboot: >------------------------------------------------------------------------ >diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c >index 57647fee1d..26ab630091 100644 >--- a/src/mainboard/emulation/spike-riscv/uart.c >+++ b/src/mainboard/emulation/spike-riscv/uart.c >@@ -20,5 +20,5 @@ >uintptr_t uart_platform_base(int idx) >{ >- return (uintptr_t) 0x40001000; >+ return (uintptr_t) 0x02100000; >} >------------------------------------------------------------------------ >[1]: https://github.com/riscv/riscv-isa-sim/pull/53 >[2]: https://github.com/neuschaefer/riscv-isa-sim/commits/uart-update I get source frome https://github.com/riscv/riscv-tools.git. Compare the difference with https://github.com/riscv/riscv-isa-sim/pull/53 and fix the code. The difference of Our patch is **UART_BASE**. You use 0x02100000, me use 0x40001000. In my test 0x40001000 can be work with **coreboot**, but 0x02100000 can not. My patch is in the attachment of the message. >> But I get from the official website of the code can not pass the test. >> I found some BUG when I debug this. >What did you test? How did it fail? I test by **spike**. I have report the patch. https://review.coreboot.org/#/c/20043/ https://review.coreboot.org/#/c/20105/ >Regards, >Jonathan Neuschäfer Regards, 王翔 ------------------ 王翔安全研究员广州市腾御安信息科技有限公司广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024

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Re: [coreboot] and here we go again!
by Zoran Stojsavljevic 09 Jun '17

09 Jun '17

[image: Inline image 1] Zoran On Thu, Jun 8, 2017 at 10:59 PM, ron minnich <rminnich(a)gmail.com> wrote: > "Microsoft's security team has come across a malware family that uses > Intel's Active Management Technology (AMT) Serial-over-LAN (SOL) interface > <https://www.bleepingcomputer.com/news/security/malware-uses-obscure-intel-c…> > as a file transfer tool. The problem with Intel AMT SOL is that it's > part of Intel's ME, a separate chip inside Intel CPUs that runs its own OS > and stays on even when the main CPU is off." > > This is getting monotonous. All these AMT exploits, ... > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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riscv: How to debug
by 王翔 09 Jun '17

09 Jun '17

I try to debug coreboot with **spike**. I has apply the **8250 usart patch** to **spike**. But I get from the official website of the code can not pass the test. I found some BUG when I debug this. I want to submit the code but I can't test it. What can i do, who can help me. I get code from `https://review.coreboot.org/coreboot.git` ------------------ 王翔安全研究员广州市腾御安信息科技有限公司广州市天河区珠江新城华穗路406号保利克洛维二期中景A座1020-1024

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Re: [coreboot] AMD EPYC and PSP
by Peter Stuge 08 Jun '17

08 Jun '17

ron minnich wrote: > Ah gee Peter, thanks for making me look at a web page with this sentence: > "Safeguarding the Future of Computing with Intel Embedded Security and > Management Engine" > > My irony-meter immediately went to 11 ... million. Ha! :) I can really recommend eyeing through that book to get confirmation on where Intel has been heading for several platform generations now, or just for fun. (Techie advisory: Intense buzzword bingo) Chapter 1: Cyber Security in the Mobile Age Chapter 2: Intel's Embedded Solutions: from Management to Security Chapter 3: Building Blocks of the Security and Management Engine Chapter 4: The Engine: Safeguarding Itself before Safeguarding Others (Remember to check those password lengths, ey.) Chapter 5: Privacy at the Next Level: Intel's Enhanced Privacy Identification (EPID) Technology Chapter 6: Boot with Integrity, or Don't Boot Chapter 7: Trust Computing, Backed by the Intel Platform Trust Technology Chapter 8: Unleashing Premium Entertainment with Hardware-Based Content Protection Chapter 9: Breaking the Boundaries with Dynamically Loaded Applications (Chapter 9 is my favorite! It describes how the ME OS can dynamically load third-party Java code.) Chapter 10: Intel Identity Protection Technology: the Robust, Convenient, and Cost-Effective Way to Deter Identity Theft Chapter 11: Looking Ahead: Tomorrow's Innovations Built on Today's Foundation //Peter

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and here we go again!
by ron minnich 08 Jun '17

08 Jun '17

"Microsoft's security team has come across a malware family that uses Intel's Active Management Technology (AMT) Serial-over-LAN (SOL) interface <https://www.bleepingcomputer.com/news/security/malware-uses-obscure-intel-c…> as a file transfer tool. The problem with Intel AMT SOL is that it's part of Intel's ME, a separate chip inside Intel CPUs that runs its own OS and stays on even when the main CPU is off." This is getting monotonous. All these AMT exploits, ... ron

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Re: [coreboot] AMD EPYC and PSP
by Peter Stuge 08 Jun '17

08 Jun '17

Rene Shuster wrote: > Not an expert obviously, but I was under the impression the Digital > Restriction Management was achieved through Widevine. No? DRM requires hardware support to be useful. If the Widevine software component was solely responsible for DRM then another software component running on the same system (e.g. in the kernel) would be able to capture all video frames. Please study Intel PAVP and Intel Insider. The best information I have seen on the topic so far is Intel's ME book. Free PDF download after registration. http://www.apress.com/9781430265719 Chapter 8: Unleashing Premium Entertainment with Hardware-Based Content Protection Technology 20 pages explain how it works. //Peter

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coreboot June 2017