coreboot June 2017

coreboot@coreboot.org

57 participants
159 discussions

Re: [coreboot] What does *intelblocks* mean?
by Banik, Subrata 05 Jun '17

05 Jun '17

>> The reason 'intelblocks' is in the include path is because the include headers are namespaced. e.g. #include <intelblocks/blah.h>. My +2 to Aaron's comment, that’s the only reason to create "intelblocks". Thanks, Subrata -----Original Message----- From: Aaron Durbin [mailto:adurbin@google.com] Sent: Monday, June 5, 2017 9:11 PM To: Paul Menzel <paulepanter(a)users.sourceforge.net> Cc: Coreboot <coreboot(a)coreboot.org>; Banik, Subrata <subrata.banik(a)intel.com> Subject: Re: [coreboot] What does *intelblocks* mean? On Mon, Jun 5, 2017 at 2:48 AM, Paul Menzel <paulepanter(a)users.sourceforge.net> wrote: > Dear coreboot folks, > > > In commit a554b0c5b7 (soc/intel/common/block: Add Intel XHCI driver > support) [1] the directory > `src/soc/intel/common/block/include/intelblocks` is created. > > Could somebody please help me, what *intelblocks* means here, and why > *intel* is twice in the path? It's common code to be used for intel SoCs. 'ipblock' would be more appropriate, but I think people didn't want to freak anyone out with the name 'ip'. The reason 'intelblocks' is in the include path is because the include headers are namespaced. e.g. #include <intelblocks/blah.h>. > > > Thanks, > > Paul > > > [1] https://review.coreboot.org/18221/ > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot

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Re: [coreboot] VT-d support
by Himanshu Chauhan 05 Jun '17

05 Jun '17

> On 05-Jun-2017, at 9:41 PM, ron minnich <rminnich(a)gmail.com> wrote: > > > > On Mon, Jun 5, 2017 at 9:00 AM Himanshu Chauhan <hschauhan(a)nulltrace.org> wrote: > Hi, > > VT-d requires support from BIOS. Does coreboot support VT-d? > > > > what support does it need? BIOS adds DMAR and other entries in the ACPI table. I am not quite sure how these entries are formed exactly though. https://www.mjmwired.net/kernel/Documentation/Intel-IOMMU.txt http://www.intel.com/content/dam/www/public/us/en/documents/product-specifi… Is anybody working on this? Regards Himanshu

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VT-d support
by Himanshu Chauhan 05 Jun '17

05 Jun '17

Hi, VT-d requires support from BIOS. Does coreboot support VT-d? Regards Himanshu Chauhan

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What does *intelblocks* mean?
by Paul Menzel 05 Jun '17

05 Jun '17

Dear coreboot folks, In commit a554b0c5b7 (soc/intel/common/block: Add Intel XHCI driver support) [1] the directory `src/soc/intel/common/block/include/intelblocks` is created. Could somebody please help me, what *intelblocks* means here, and why *intel* is twice in the path? Thanks, Paul [1] https://review.coreboot.org/18221/

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Current, BLOB free laptop available Europe?
by Paul Menzel 05 Jun '17

05 Jun '17

Dear coreboot folks, I am looking for a new portable device available in Europe. Is it true, that the Acer Chromebook R 13 [1], is the only current BLOB free device? The device currently costs 400 €. Is MediaTek “a good citizen”, that means, do they provide datasheets and work on drivers? The Samsung Chromebook Plus/Pro with RK3399 [2] are only available in the USA, right? Thanks, Paul [1] https://www.acer.com/ac/en/US/content/series/acerchromebookr13 [2] https://chromeunboxed.com/samsung-chromebook-pros-processor-rk3399-gets-ben…

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MRC Raminit
by Kory Maincent 05 Jun '17

05 Jun '17

Hi, I am working on an embedded board from Interface concept. The chipset is intel QM67 (Cougar point) with a sandybridge Gen2 processor. I think the board doesn’t have any spd because I get the error “Not a DDR3 SPD!” so I try to do the mrc raminit with the systemagent-r6.bin but I am stuck on the initialization: System Agent: Starting up... System Agent: Initializing PCH System Agent: Initializing PCH (SMBUS) System Agent: Initializing PCH (USB) System Agent: Initializing PCH (SA Init) System Agent: Initializing PCH (Me UMA) System Agent: Initializing Memory System Agent: failed to locate restore data hob! System Agent: Done. Can you help me to understand how to do the raminit? Kory

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Re: [coreboot] Port80 isn't working (ASUS P8B75-V) (Konstantin Novikov)
by Константин 05 Jun '17

05 Jun '17

Hello, Peter! The mistake was found in the following part of the code (southbridge/intel/bd82x6x/bootblock.c): static void bootblock_southbridge_init(void) { store_initial_timestamp(); enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); } This mistake was eliminated in the Haswell-code: static void map_rcba(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); } static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC. */ u32 gcs = RCBA32(GCS); gcs = gcs & ~0x4; RCBA32(GCS) = gcs; } static void bootblock_southbridge_init(void) { store_initial_timestamp(); map_rcba(); enable_spi_prefetch(); #if CONFIG_POST_DEVICE_LPC enable_port80_on_lpc(); #endif set_spi_speed(); /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); } After that all the post-codes are sended correctly. Also we have found he mistake in the part of the code for the memory-banks. In the code for SandyBridge/IvyBridge variables are assigned "hardly" while for the Haswell variables are defined dynamically: static void configure_mca(void) { msr_t msr; int i; msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ for (i = 0; i < 7; i++) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } Now I port ASUS P8B75-V motherboard. Everything is OK with using Intel Core i3, but with Intel Celeron G440 on the seventh iteration we have got a mistake because there is not the seventh memory bank there. With using Haswell-code our project runs correctly with both processors: static void configure_mca(void) { msr_t msr; int i; int num_banks; const unsigned int mcg_cap_msr = 0x179; msr = rdmsr(mcg_cap_msr); num_banks = msr.lo & 0xff; msr.lo = msr.hi = 0; /* This should only be done on a cold boot */ for (i = 0; i < num_banks; i++) wrmsr(IA32_MC0_STATUS + (i * 4), msr); }

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Re: [coreboot] minnowmax serial port cord
by ron minnich 05 Jun '17

05 Jun '17

you saved my demo! On Sun, Jun 4, 2017 at 5:21 PM Marshall Dawson <marshalldawson3rd(a)gmail.com> wrote: > Hey Ron, > I'll bring one. > > > On Sun, Jun 4, 2017 at 3:12 PM, ron minnich <rminnich(a)gmail.com> wrote: > >> I forgot to pack my minnowmax serial port cable, it's this one: >> >> http://elinux.org/Minnowboard:MinnowMax#6-Wire_Serial_Console >> >> My demo at the coreboot conf is gonna be boring without the cable, if >> someone can bring one that would be wonderful. >> >> thanks >> >> ron >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://mail.coreboot.org/mailman/listinfo/coreboot >> >

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Re: [coreboot] minnowmax serial port cord
by Marshall Dawson 05 Jun '17

05 Jun '17

Hey Ron, I'll bring one. On Sun, Jun 4, 2017 at 3:12 PM, ron minnich <rminnich(a)gmail.com> wrote: > I forgot to pack my minnowmax serial port cable, it's this one: > > http://elinux.org/Minnowboard:MinnowMax#6-Wire_Serial_Console > > My demo at the coreboot conf is gonna be boring without the cable, if > someone can bring one that would be wonderful. > > thanks > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://mail.coreboot.org/mailman/listinfo/coreboot >

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make crossgcc-i386 : ubsan.c error (with fix!) for GCC
by qma ster 05 Jun '17

05 Jun '17

Good day! While building the coreboot's toolchain by using GCC 7.1.1 version, I am getting the following error: ubsan.c:1474:23: error: ISO C++ forbids comparison between pointer and integer [-fpermissive] || xloc.file == '\0' || xloc.file[0] == '\xff' The fix is very simple - just open ./util/crossgcc/gcc-6.3.0/gcc/ubsan.c and change || xloc.file == '\0' || xloc.file[0] == '\xff' to || xloc.file[0] == '\0' || xloc.file[0] == '\xff' Found this solution here - https://patchwork.openembedded.org/patch/138884/ . Would be great if you could somehow import it to your code Best regards, qmastery

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coreboot June 2017