coreboot October 2015

coreboot@coreboot.org

44 participants
137 discussions

Re: [coreboot] SPD binaries in coreboot
by Peter Stuge 23 Oct '15

23 Oct '15

ron minnich wrote: > Build the tool in go. I have to disagree with that. We want to keep dependencies few and small, neither of which is really true for Go. Hammer and nail.. > It's trivial. I think that's true regardless of which tool we use. //Peter

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Re: [coreboot] SPD binaries in coreboot
by Patrick Georgi 23 Oct '15

23 Oct '15

It's more trivial not to have a tool in the first place. It's also more trivial not to add a new dependency to our build process. Especially a dependency that is lacking in portability (ie. users can't build coreboot anymore because they can't run go) Sorry, but no. 2015-10-23 17:32 GMT+02:00 ron minnich <rminnich(a)gmail.com>: > Build the tool in go. It's trivial. If you have an idea how it ought to work > I can set it up in the playground in a few minutes. > > ron > > On Fri, Oct 23, 2015 at 8:24 AM Patrick Georgi <pgeorgi(a)google.com> wrote: >> >> Hi, >> >> Some mainboards come with soldered-on memory without SPD ROM. For >> these, we carry the SPD data in coreboot. >> >> Currently, they're stored in a hexdump format that is then converted >> to binary at build time. The various mechanisms of doing so fail on >> some platform or another: >> - "echo -e -n $stuff" isn't well-liked by some shells (emits "e -n >> $stuff") >> - "printf '\x42'" isn't well-liked by some shells (or /usr/bin/printf >> tools) that don't support hexadecimal formats >> - "printf '\0377'" isn't well-liked by some non-conforming, but existing >> shells >> - xxd -rg1 $file > $file.bin requires xxd, which comes with vim and >> may just not exist >> >> I see essentially two ways out of this, before we can start reducing >> duplication across the tree in that area: >> We could build our own tool to parse hex files and dump binary, or we >> could ship SPD data as binary from the start (and only have to >> concatenate them). >> >> The second option has the appeal of being much simpler (and there >> isn't really a "preferred form" for editing SPD data that I'm aware of >> - is there?), but looks icky at a glance because it's binary (but it's >> really just as impenetrable as the equivalent hexdump). >> >> So what do these files contain? Parameters (as in: facts) about the >> hardware's size, layout, and timing, and a bunch of vendor/model >> identifier strings. >> >> >> So, is there a third option that I'm missing? Other opinions? >> Patrick >> -- >> Google Germany GmbH, ABC-Str. 19, 20354 Hamburg >> Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: >> Hamburg >> Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle

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Re: [coreboot] SPD binaries in coreboot
by Peter Stuge 23 Oct '15

23 Oct '15

Patrick Georgi wrote: > we carry the SPD data in coreboot. .. > Currently, they're stored in a hexdump format .. > I see essentially two ways out of this .. > We could build our own tool to parse hex files and dump binary, If we create a tool for this process I think we can find a better "source" format than hex files. Someone needs to take a look at the JEDEC standard and think of what might be suitable. > or we could ship SPD data as binary from the start I am actually strongly in favor of this approach. Converting SPD data from human readable to machine readable is an orthogonal problem to fixing the structure of our codebase, and there is no reason not to solve the structural problem without first having to invent a new data format. > The second option has the appeal of being much simpler (and there > isn't really a "preferred form" for editing SPD data that I'm aware of > - is there?) I guess JEDEC does have a structured format. Maybe it's XML or JSON. :) > So, is there a third option that I'm missing? Other opinions? The third option would be a plain text format which is easy to parse but still covers the spec well. Unblobing SPD files is an excellent entry-level project which we could keep on shelf. Maybe for next GSoC.. Fixing structure is more important IMO and shouldn't need to block on that. //Peter

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Re: [coreboot] SPD binaries in coreboot
by ron minnich 23 Oct '15

23 Oct '15

Build the tool in go. It's trivial. If you have an idea how it ought to work I can set it up in the playground in a few minutes. ron On Fri, Oct 23, 2015 at 8:24 AM Patrick Georgi <pgeorgi(a)google.com> wrote: > Hi, > > Some mainboards come with soldered-on memory without SPD ROM. For > these, we carry the SPD data in coreboot. > > Currently, they're stored in a hexdump format that is then converted > to binary at build time. The various mechanisms of doing so fail on > some platform or another: > - "echo -e -n $stuff" isn't well-liked by some shells (emits "e -n > $stuff") > - "printf '\x42'" isn't well-liked by some shells (or /usr/bin/printf > tools) that don't support hexadecimal formats > - "printf '\0377'" isn't well-liked by some non-conforming, but existing > shells > - xxd -rg1 $file > $file.bin requires xxd, which comes with vim and > may just not exist > > I see essentially two ways out of this, before we can start reducing > duplication across the tree in that area: > We could build our own tool to parse hex files and dump binary, or we > could ship SPD data as binary from the start (and only have to > concatenate them). > > The second option has the appeal of being much simpler (and there > isn't really a "preferred form" for editing SPD data that I'm aware of > - is there?), but looks icky at a glance because it's binary (but it's > really just as impenetrable as the equivalent hexdump). > > So what do these files contain? Parameters (as in: facts) about the > hardware's size, layout, and timing, and a bunch of vendor/model > identifier strings. > > > So, is there a third option that I'm missing? Other opinions? > Patrick > -- > Google Germany GmbH, ABC-Str. 19, 20354 Hamburg > Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: > Hamburg > Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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SPD binaries in coreboot
by Patrick Georgi 23 Oct '15

23 Oct '15

Hi, Some mainboards come with soldered-on memory without SPD ROM. For these, we carry the SPD data in coreboot. Currently, they're stored in a hexdump format that is then converted to binary at build time. The various mechanisms of doing so fail on some platform or another: - "echo -e -n $stuff" isn't well-liked by some shells (emits "e -n $stuff") - "printf '\x42'" isn't well-liked by some shells (or /usr/bin/printf tools) that don't support hexadecimal formats - "printf '\0377'" isn't well-liked by some non-conforming, but existing shells - xxd -rg1 $file > $file.bin requires xxd, which comes with vim and may just not exist I see essentially two ways out of this, before we can start reducing duplication across the tree in that area: We could build our own tool to parse hex files and dump binary, or we could ship SPD data as binary from the start (and only have to concatenate them). The second option has the appeal of being much simpler (and there isn't really a "preferred form" for editing SPD data that I'm aware of - is there?), but looks icky at a glance because it's binary (but it's really just as impenetrable as the equivalent hexdump). So what do these files contain? Parameters (as in: facts) about the hardware's size, layout, and timing, and a bunch of vendor/model identifier strings. So, is there a third option that I'm missing? Other opinions? Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Matthew Scott Sucherman, Paul Terence Manicle

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Broadwell IGD (on Auron_Paine)
by Georg Wicherski 23 Oct '15

23 Oct '15

Hi, thanks to Marc Jones' SGD patch for the Auron board (f3214d02482a4104d7276f06d6b326b2a54c4262), I was able to get my Auron_Paine up to ramstage. Unfortunately, the IGD code in soc/intel/broadwell/ appears to be somewhat broken. Based off Aaron's guidance on IRC, I've pin-pointed the issue to be within igd_setup_panel . The first gtt_read there seems to hang already (BIOS_SPEW log attached). Find my current code with those debug prints at <http://review.coreboot.org/#/c/11907/2>. FWIW, I've tested with some commenting-out, etc. that it's any gtt_read that immediately causes a hang there. Also dumped the gtt_res, small excerpt from the log: --8<-- igd's gtt_res = { base=e0000000, size=1000000, limit=e0ffffff, flags=60000201 } igd_init: waited for pre-graphics delay to pass igd_init: went through early init igd_init: RP1 graphics frequency is set gtt_read(PCH_PORT_HOTPLUG) --8<-- People on IRC mentioned that this is an issue that people may have run into before on Broadwell, any suggestions on how to fix the hang there? Thanks, G

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about Ivy Bridge CPU with QM67 PCH
by Iru Cai 23 Oct '15

23 Oct '15

Hi, I've been testing the Lenovo T420 port recently, and now I can install an Ivy Bridge processor and run fine on Linux(except some thermal issues). However, the native graphics initialization doesn't work properly before Linux kernel boots. I can see the GRUB interface but it displays bad as if it's on a panel larger than the laptop panel. Then, Linux kernel boots and the graphics become good again. I read some of the i915 driver code of Linux, and saw some code about PCH, so I think this issue has something to do about the southbridge. I don't know if someone has tried using mixed generation of CPU and chipset combination with coreboot before, and I hope this issue can be resolved. I have pushed the patch that makes coreboot support both SNB and IVB processor for review: http://review.coreboot.org/#/c/12087/ Iru Cai

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Re: [coreboot] GPL license headers
by Stefan Reinauer 23 Oct '15

23 Oct '15

>From my previous discussions with lawyers on the topic, the third paragraph is unproblematic to remove. With resolutions of today's monitors and keyboards often having a page down key, keeping the second paragraph seems like a good compromise to stay friends with the legal experts and err on the safe side. Stefan * ron minnich <rminnich(a)gmail.com> [151021 05:41]: > Let me ask around. > > ron > > On Tue, Oct 20, 2015 at 7:20 PM Martin Roth <gaumless(a)gmail.com> wrote: > > I haven't seen any disagreement that we get rid of the entire third > paragraph. > > Alex votes that we should get rid of the second paragraph of the > header as well, and what Ron posted SEEMS to support that we can, > although the wording in that license header might be different enough > that it doesn't apply to our case. > > Personally, I'm in favor of keeping the second paragraph. It looks to > me like the first paragraph just discusses distribution, not > liability. I don't really see any NEED to get rid of the second > paragraph. > > Are there any other thoughts either way on getting rid of the second > paragraph? > > Martin > > > > On Tue, Oct 20, 2015 at 6:47 PM, Alex G. <mr.nuke.me(a)gmail.com> wrote: > > On 10/20/2015 10:54 AM, ron minnich wrote: > >> Eben Moglen, who ought to know, guided us on the release rules for the > >> Plan 9 GPL release. > >> > >> Here is what he told us could go in each file: > >> /* > >> * This file is part of the UCB release of Plan 9. It is subject to the > >> license > >> * terms in the LICENSE file found in the top-level directory of this > >> * distribution and at http://akaros.cs.berkeley.edu/files/Plan9License. > No > >> * part of the UCB release of Plan 9, including this file, may be > copied, > >> * modified, propagated, or distributed except according to the terms > >> contained > >> * in the LICENSE file. > >> */ > > > > +2 > > > >> On Tue, Oct 20, 2015 at 10:30 AM Patrick Georgi <pgeorgi(a)google.com > >> <mailto:pgeorgi@google.com>> wrote: > >> Get (the right set of) lawyers to sign off on that. > > > > You were saying, Patrick? > > > > Alex > > > > -- > > coreboot mailing list: coreboot(a)coreboot.org > > http://www.coreboot.org/mailman/listinfo/coreboot > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot

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New on blogs.coreboot.org: coreboot changelog
by WordPress 22 Oct '15

22 Oct '15

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Asus M2N-E no boot, post codes A5 80 73
by Balázs Vinarz 22 Oct '15

22 Oct '15

Hi. I compiled from the source about 6 months and now. The mobo is still unable to boot. Serial debugs are attached, i tried with many memory-modules in all sockets. There are two options, when the postcard jumps between codes A5 and 80: #START coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 romstage starting... *sysinfo range: [000c8020,000c8750] bsp_apicid=0x00 Enabling routing table for node 0 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: started ap apicid: SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num: 01 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cff38 Unbuffered 333MHz 333MHz Interleaving disabled RAM end at 0x00100000 kB Ram3 Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 1024MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=ae Total DQS Training : tsc [00]=0000000012a29d35 Total DQS Training : tsc [01]=4d33333300000002 Total DQS Training : tsc [02]=0000000000007a48 Total DQS Training : tsc [03]=fff85d4d00000064 Ram4 Prepare CAR migration and stack regions... Fill [001ff400-001fffff] ... Done Copying data from cache to RAM... Copy [000c8000-000c877f] to [001ff880 - 001fe Switching to use RAM as stack... INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 romstage starting... *sysinfo range: [000c8020,000c8750] bsp_apicid=0x00 Enabling routing table for node 0 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: started ap apicid: SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num: 01 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cff38 Unbuffered 333MHz 333MHz Interleaving disabled RAM end at 0x00100000 kB Ram3 Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 1024MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=ae Total DQS Training : tsc [00]=0000000012a29d35 Total DQS Training : tsc [01]=4d33333300000002 Total DQS Training : tsc [02]=0000000000007a48 Total DQS Training : tsc [03]=fff85d4d00000064 Ram4 Prepare CAR migration and stack regions... Fill [001ff400-001fffff] ... Done Copying data from cache to RAM... Copy [000c8000-000c877f] to [001ff880 - 001fe Switching to use RAM as stack... INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} --- Issuing SOFT_RESET... #END And when it turn off and ends with postcode 73: #START ENDS WITH post 73 coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 romstage starting... *sysinfo range: [000c8020,000c8750] bsp_apicid=0x00 Enabling routing table for node 0 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: started ap apicid: SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x1 after optimize_link_read_pointers_chain, reset_needed=0x1 mcp55_num: 01 ht reset - coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 romstage starting... *sysinfo range: [000c8020,000c8750] bsp_apicid=0x00 Enabling routing table for node 0 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: started ap apicid: SBLink=00 NC node|link=00 entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x7f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 mcp55_num: 01 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000cff38 Unbuffered 333MHz 333MHz Interleaved RAM end at 0x00100000 kB Ram3 Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 1024MB, type WB set DQS timing:RcvrEn:Pass1: 00 CTLRMaxDelay=12 done set DQS timing:DQSPos: 00 TrainDQSRdWrPos: buf_a:000cfa20 TrainDQSPos: MutualCSPassW[48] :000cf8f8 TrainDQSPos: MutualCSPassW[48] :000cf8f8 TrainDQSPos: MutualCSPassW[48] :000cf8f8 TrainDQSPos: MutualCSPassW[48] :000cf908 done set DQS timing:RcvrEn:Pass2: 00 CTLRMaxDelay=57 done Total DQS Training : tsc [00]=0000000012945351 Total DQS Training : tsc [01]=0000000013137d9b Total DQS Training : tsc [02]=000000001f9559cb Total DQS Training : tsc [03]=00000000205fad07 Ram4 Prepare CAR migration and stack regions... Fill [001ff400-001fffff] ... Done Copying data from cache to RAM... Copy [000c8000-000c877f] to [001ff880 – 001f Switching to use RAM as stack... Top about 001ff86c ... Done Disabling cache as ram now Prepare ramstage memory region... Fill [00000000-001ff3ff] ... Done CBFS provider active. CBFS @ 0 size 7fc00 CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset c240 size b72d 'fallback/ramstage' located at offset: c278 size: b72d coreboot-4.1-781-g744729a Tue Oct 20 14:50:25 UTC 2015 ramstage starting... Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:01.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:05.1: enabled 1 PCI: 00:05.2: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:06.1: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 0 PCI: 00:0f.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.6: enabled 1 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:01.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:05.1: enabled 1 PCI: 00:05.2: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:06.1: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 1 PCI: 00:0b.0: enabled 0 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 0 PCI: 00:0f.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Root Device scanning... root_dev_scan_bus for Root Device setup_bsp_ramtop, TOP MEM: msr.lo = 0x40000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000 CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 #[24;9HFound Rev E or Rev F later single core CPU: APIC: 00 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:18.0 scanning... PCI: 00:00.0 [10de/0369] ops PCI: 00:00.0 [10de/0369] enabled Capability: type 0x08 @ 0x44 flags: 0x01e0 PCI: 00:00.0 count: 000f static_count: 0010 PCI: 00:00.0 [10de/0369] enabled next_unitid: 0010 PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [10de/0369] enabled PCI: 00:01.0 [10de/0000] bus ops PCI: 00:01.0 [10de/0360] enabled PCI: 00:01.1 [10de/0368] bus ops PCI: 00:01.1 [10de/0368] enabled PCI: 00:01.2 [10de/036a] enabled PCI: 00:01.3 [10de/036b] enabled PCI: 00:02.0 [10de/036c] ops PCI: 00:02.0 [10de/036c] enabled PCI: 00:02.1 [10de/036d] ops PCI: 00:02.1 [10de/036d] enabled PCI: 00:04.0 [10de/036e] ops PCI: 00:04.0 [10de/036e] enabled PCI: 00:05.0 [10de/037f] ops PCI: 00:05.0 [10de/037f] enabled PCI: 00:05.1 [10de/037f] ops PCI: 00:05.1 [10de/037f] enabled PCI: 00:05.2 [10de/037f] ops PCI: 00:05.2 [10de/037f] enabled PCI: 00:06.0 [10de/0370] bus ops PCI: 00:06.0 [10de/0370] enabled PCI: 00:06.1 [10de/0371] ops PCI: 00:06.1 [10de/0371] enabled PCI: 00:08.0 [10de/0373] ops PCI: 00:08.0 [10de/0373] enabled PCI: 00:0a.0 [10de/0000] bus ops PCI: 00:0a.0 [10de/0376] enabled PCI: 00:0c.0 [10de/0000] bus ops PCI: 00:0c.0 [10de/0374] enabled PCI: 00:0d.0 [10de/0000] bus ops PCI: 00:0d.0 [10de/0378] enabled PCI: 00:0f.0 [10de/0000] bus ops PCI: 00:0f.0 [10de/0377] enabled PCI: 00:01.0 scanning... scan_lpc_bus for PCI: 00:01.0 PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_lpc_bus for PCI: 00:01.0 done PCI: 00:01.1 scanning... scan_smbus for PCI: 00:01.1 smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled scan_smbus for PCI: 00:01.1 done PCI: 00:06.0 scanning... do_pci_scan_bridge for PCI: 00:06.0 PCI: pci_scan_bus for bus 01 PCI: 00:0a.0 scanning... do_pci_scan_bridge for PCI: 00:0a.0 PCI: pci_scan_bus for bus 02 PCI: 00:0c.0 scanning... do_pci_scan_bridge for PCI: 00:0c.0 PCI: pci_scan_bus for bus 03 PCI: 00:0d.0 scanning... do_pci_scan_bridge for PCI: 00:0d.0 PCI: pci_scan_bus for bus 04 PCI: 00:0f.0 scanning... do_pci_scan_bridge for PCI: 00:0f.0 PCI: pci_scan_bus for bus 05 PCI: 05:00.0 [1002/5b63] enabled PCI: 05:00.1 [1002/5b73] enabled DOMAIN: 0000 passpw: enabled root_dev_scan_bus for Root Device done done found VGA at PCI: 05:00.0 Setting up VGA for PCI: 05:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:0f.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 0 link: 0 done PCI: 00:01.1 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources PCI: 00:01.1 read_resources bus 1 link: 0 done PCI: 00:06.0 read_resources bus 1 link: 0 PCI: 00:06.0 read_resources bus 1 link: 0 done PCI: 00:0a.0 read_resources bus 2 link: 0 PCI: 00:0a.0 read_resources bus 2 link: 0 done PCI: 00:0c.0 read_resources bus 3 link: 0 PCI: 00:0c.0 read_resources bus 3 link: 0 done PCI: 00:0d.0 read_resources bus 4 link: 0 PCI: 00:0d.0 read_resources bus 4 link: 0 done PCI: 00:0f.0 read_resources bus 5 link: 0 PCI: 00:0f.0 read_resources bus 5 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 1 PCI: 00:18.0 read_resources bus 0 link: 1 done PCI: 00:18.0 read_resources bus 0 link: 2 PCI: 00:18.0 read_resources bus 0 link: 2 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:18.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 33 size 0 align 0 gran 0 limit 3000 flags 1 index PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff fl PCI: 00:00.0 PCI: 00:01.0 child on link 0 PNP: 002e.0 PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c004010 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flag PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c00001 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 i PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 i PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c00001 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 i PNP: 002e.2 PNP: 002e.2 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 inde PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c00001 PNP: 002e.3 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 i PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 i PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800 i PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags c00001 PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 i PNP: 002e.5 PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0 PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0 PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 i PNP: 002e.6 PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 i PNP: 002e.7 PNP: 002e.7 resource base 0 size 0 align 0 gran 0 limit 0 flags c0000100 i PNP: 002e.7 resource base 800 size 8 align 3 gran 3 limit 7ff flags c00001 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags c0000100 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 inde PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 PNP: 002e.a PCI: 00:01.1 child on link 0 I2C: 01:50 PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 in PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i PCI: 00:01.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 i I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PCI: 00:01.2 PCI: 00:01.3 PCI: 00:01.3 resource base 0 size 40000 align 18 gran 18 limit ffffffff fla PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag PCI: 00:02.1 PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 2 PCI: 00:04.0 PCI: 00:04.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in PCI: 00:05.0 PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind PCI: 00:05.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind PCI: 00:05.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind PCI: 00:05.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in PCI: 00:05.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag PCI: 00:05.1 PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind PCI: 00:05.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind PCI: 00:05.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind PCI: 00:05.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in PCI: 00:05.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag PCI: 00:05.2 PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind PCI: 00:05.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind PCI: 00:05.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 ind PCI: 00:05.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 in PCI: 00:05.2 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag PCI: 00:06.0 PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 8 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 8 PCI: 00:06.1 PCI: 00:06.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flag PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flag PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 ind PCI: 00:08.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 2 PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffffffff flags 20 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8 PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 8 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8 PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 8 PCI: 00:0d.0 PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8 PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 8 PCI: 00:0e.0 PCI: 00:0f.0 child on link 0 PCI: 05:00.0 PCI: 00:0f.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 8 PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff PCI: 00:0f.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 8 PCI: 05:00.0 PCI: 05:00.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffff PCI: 05:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 PCI: 05:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff fl PCI: 05:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff fl PCI: 05:00.1 PCI: 05:00.1 resource base 0 size 10000 align 16 gran 16 limit ffffffff fl PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff fl DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:06.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:06.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:0f.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 05:00.0 14 * [0x0 - 0xff] io PCI: 00:0f.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:0f.0 1c * [0x0 - 0xfff] io PCI: 00:01.1 60 * [0x1000 - 0x10ff] io PCI: 00:01.1 64 * [0x1400 - 0x14ff] io PCI: 00:01.1 68 * [0x1800 - 0x18ff] io PCI: 00:01.1 10 * [0x1c00 - 0x1c3f] io PCI: 00:01.1 20 * [0x1c40 - 0x1c7f] io PCI: 00:01.1 24 * [0x1c80 - 0x1cbf] io PCI: 00:04.0 20 * [0x1cc0 - 0x1ccf] io PCI: 00:05.0 20 * [0x1cd0 - 0x1cdf] io PCI: 00:05.1 20 * [0x1ce0 - 0x1cef] io PCI: 00:05.2 20 * [0x1cf0 - 0x1cff] io PCI: 00:05.0 10 * [0x2000 - 0x2007] io PCI: 00:05.0 18 * [0x2008 - 0x200f] io PCI: 00:05.1 10 * [0x2010 - 0x2017] io PCI: 00:05.1 18 * [0x2018 - 0x201f] io PCI: 00:05.2 10 * [0x2020 - 0x2027] io PCI: 00:05.2 18 * [0x2028 - 0x202f] io PCI: 00:08.0 14 * [0x2030 - 0x2037] io PCI: 00:05.0 14 * [0x2038 - 0x203b] io PCI: 00:05.0 1c * [0x203c - 0x203f] io PCI: 00:05.1 14 * [0x2040 - 0x2043] io PCI: 00:05.1 1c * [0x2044 - 0x2047] io PCI: 00:05.2 14 * [0x2048 - 0x204b] io PCI: 00:05.2 1c * [0x204c - 0x204f] io PCI: 00:18.0 io: base: 2050 size: 3000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 00 * [0x0 - 0x2fff] io DOMAIN: 0000 io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:06.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:06.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffffff PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffffff PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffffff PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffffff PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffffff PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffffff PCI: 00:0f.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffffffffff PCI: 05:00.0 10 * [0x0 - 0x7ffffff] prefmem PCI: 00:0f.0 prefmem: base: 8000000 size: 8000000 align: 27 gran: 20 limit: fff PCI: 00:0f.0 24 * [0x0 - 0x7ffffff] prefmem PCI: 00:18.0 prefmem: base: 8000000 size: 8000000 align: 27 gran: 20 limit: fff PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:06.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:06.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:0f.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 05:00.0 30 * [0x0 - 0x1ffff] mem PCI: 05:00.0 18 * [0x20000 - 0x2ffff] mem PCI: 05:00.1 10 * [0x30000 - 0x3ffff] mem PCI: 00:0f.0 mem: base: 40000 size: 100000 align: 20 gran: 20 limit: ffffffff d PCI: 00:0f.0 20 * [0x0 - 0xfffff] mem PCI: 00:01.3 10 * [0x100000 - 0x13ffff] mem PCI: 00:06.1 10 * [0x140000 - 0x143fff] mem PCI: 00:01.0 14 * [0x144000 - 0x144fff] mem PCI: 00:02.0 10 * [0x145000 - 0x145fff] mem PCI: 00:05.0 24 * [0x146000 - 0x146fff] mem PCI: 00:05.1 24 * [0x147000 - 0x147fff] mem PCI: 00:05.2 24 * [0x148000 - 0x148fff] mem PCI: 00:08.0 10 * [0x149000 - 0x149fff] mem PCI: 00:02.1 10 * [0x14a000 - 0x14a0ff] mem PCI: 00:08.0 18 * [0x14a100 - 0x14a1ff] mem PCI: 00:08.0 1c * [0x14a200 - 0x14a20f] mem PCI: 00:18.0 mem: base: 14a210 size: 200000 align: 20 gran: 20 limit: ffffffff PCI: 00:18.0 02 * [0x0 - 0x7ffffff] prefmem PCI: 00:18.3 94 * [0x8000000 - 0xbffffff] mem PCI: 00:18.0 01 * [0xc000000 - 0xc1fffff] mem DOMAIN: 0000 mem: base: c200000 size: c200000 align: 27 gran: 0 limit: ffffffff avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:18.0 04 base 000a0000 limit 000bffff mem (fixed) constrain_resources: PCI: 00:01.0 10000000 base 00000000 limit 00000fff io (fix constrain_resources: PCI: 00:01.0 10000100 base ff800000 limit ffffffff mem (fi constrain_resources: PCI: 00:01.0 03 base fec00000 limit fec00fff mem (fixed) skipping PNP: 002e.3@62 fixed resource, size=0! avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit febfffff Setting resources... DOMAIN: 0000 io: base:1000 size:3000 align:12 gran:0 limit:ffff PCI: 00:18.0 00 * [0x1000 - 0x3fff] io DOMAIN: 0000 io: next_base: 4000 size: 3000 align: 12 gran: 0 done PCI: 00:18.0 io: base:1000 size:3000 align:12 gran:12 limit:3fff PCI: 00:0f.0 1c * [0x1000 - 0x1fff] io PCI: 00:01.1 60 * [0x2000 - 0x20ff] io PCI: 00:01.1 64 * [0x2400 - 0x24ff] io PCI: 00:01.1 68 * [0x2800 - 0x28ff] io PCI: 00:01.1 10 * [0x2c00 - 0x2c3f] io PCI: 00:01.1 20 * [0x2c40 - 0x2c7f] io PCI: 00:01.1 24 * [0x2c80 - 0x2cbf] io PCI: 00:04.0 20 * [0x2cc0 - 0x2ccf] io PCI: 00:05.0 20 * [0x2cd0 - 0x2cdf] io PCI: 00:05.1 20 * [0x2ce0 - 0x2cef] io PCI: 00:05.2 20 * [0x2cf0 - 0x2cff] io PCI: 00:05.0 10 * [0x3000 - 0x3007] io PCI: 00:05.0 18 * [0x3008 - 0x300f] io PCI: 00:05.1 10 * [0x3010 - 0x3017] io PCI: 00:05.1 18 * [0x3018 - 0x301f] io PCI: 00:05.2 10 * [0x3020 - 0x3027] io PCI: 00:05.2 18 * [0x3028 - 0x302f] io PCI: 00:08.0 14 * [0x3030 - 0x3037] io PCI: 00:05.0 14 * [0x3038 - 0x303b] io PCI: 00:05.0 1c * [0x303c - 0x303f] io PCI: 00:05.1 14 * [0x3040 - 0x3043] io PCI: 00:05.1 1c * [0x3044 - 0x3047] io PCI: 00:05.2 14 * [0x3048 - 0x304b] io PCI: 00:05.2 1c * [0x304c - 0x304f] io PCI: 00:18.0 io: next_base: 3050 size: 3000 align: 12 gran: 12 done PCI: 00:06.0 io: base:3fff size:0 align:12 gran:12 limit:3fff PCI: 00:06.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done PCI: 00:0a.0 io: base:3fff size:0 align:12 gran:12 limit:3fff PCI: 00:0a.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done PCI: 00:0c.0 io: base:3fff size:0 align:12 gran:12 limit:3fff PCI: 00:0c.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done PCI: 00:0d.0 io: base:3fff size:0 align:12 gran:12 limit:3fff PCI: 00:0d.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done PCI: 00:0f.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff PCI: 05:00.0 14 * [0x1000 - 0x10ff] io PCI: 00:0f.0 io: next_base: 1100 size: 1000 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:c200000 align:27 gran:0 limit:febfffff PCI: 00:18.0 02 * [0xf0000000 - 0xf7ffffff] prefmem PCI: 00:18.3 94 * [0xf8000000 - 0xfbffffff] mem PCI: 00:18.0 01 * [0xfc000000 - 0xfc1fffff] mem DOMAIN: 0000 mem: next_base: fc200000 size: c200000 align: 27 gran: 0 done PCI: 00:18.0 prefmem: base:f0000000 size:8000000 align:27 gran:20 limit:f7fffff PCI: 00:0f.0 24 * [0xf0000000 - 0xf7ffffff] prefmem PCI: 00:18.0 prefmem: next_base: f8000000 size: 8000000 align: 27 gran: 20 done PCI: 00:06.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:06.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:0a.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:0a.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:0c.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:0d.0 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:0f.0 prefmem: base:f0000000 size:8000000 align:27 gran:20 limit:f7fffff PCI: 05:00.0 10 * [0xf0000000 - 0xf7ffffff] prefmem PCI: 00:0f.0 prefmem: next_base: f8000000 size: 8000000 align: 27 gran: 20 done PCI: 00:18.0 mem: base:fc000000 size:200000 align:20 gran:20 limit:fc1fffff PCI: 00:0f.0 20 * [0xfc000000 - 0xfc0fffff] mem PCI: 00:01.3 10 * [0xfc100000 - 0xfc13ffff] mem PCI: 00:06.1 10 * [0xfc140000 - 0xfc143fff] mem PCI: 00:01.0 14 * [0xfc144000 - 0xfc144fff] mem PCI: 00:02.0 10 * [0xfc145000 - 0xfc145fff] mem PCI: 00:05.0 24 * [0xfc146000 - 0xfc146fff] mem PCI: 00:05.1 24 * [0xfc147000 - 0xfc147fff] mem PCI: 00:05.2 24 * [0xfc148000 - 0xfc148fff] mem PCI: 00:08.0 10 * [0xfc149000 - 0xfc149fff] mem PCI: 00:02.1 10 * [0xfc14a000 - 0xfc14a0ff] mem PCI: 00:08.0 18 * [0xfc14a100 - 0xfc14a1ff] mem PCI: 00:08.0 1c * [0xfc14a200 - 0xfc14a20f] mem PCI: 00:18.0 mem: next_base: fc14a210 size: 200000 align: 20 gran: 20 done PCI: 00:06.0 mem: base:fc1fffff size:0 align:20 gran:20 limit:fc1fffff PCI: 00:06.0 mem: next_base: fc1fffff size: 0 align: 20 gran: 20 done PCI: 00:0a.0 mem: base:fc1fffff size:0 align:20 gran:20 limit:fc1fffff PCI: 00:0a.0 mem: next_base: fc1fffff size: 0 align: 20 gran: 20 done PCI: 00:0c.0 mem: base:fc1fffff size:0 align:20 gran:20 limit:fc1fffff PCI: 00:0c.0 mem: next_base: fc1fffff size: 0 align: 20 gran: 20 done PCI: 00:0d.0 mem: base:fc1fffff size:0 align:20 gran:20 limit:fc1fffff PCI: 00:0d.0 mem: next_base: fc1fffff size: 0 align: 20 gran: 20 done PCI: 00:0f.0 mem: base:fc000000 size:100000 align:20 gran:20 limit:fc0fffff PCI: 05:00.0 30 * [0xfc000000 - 0xfc01ffff] mem PCI: 05:00.0 18 * [0xfc020000 - 0xfc02ffff] mem PCI: 05:00.1 10 * [0xfc030000 - 0xfc03ffff] mem PCI: 00:0f.0 mem: next_base: fc040000 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 0: mmio_basek=003c0000, basek=00000300, limitk=00100000 DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0 PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io PCI: 00:18.0 1b8 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 pre PCI: 00:18.0 1b0 <- [0x00fc000000 - 0x00fc1fffff] size 0x00200000 gran 0x14 mem PCI: 00:18.0 1a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:01.0 14 <- [0x00fc144000 - 0x00fc144fff] size 0x00001000 gran 0x0c mem PCI: 00:01.0 assign_resources, bus 0 link: 0 PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.3 62 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.4 62 <- [0x0000000000 - 0x0000000007] size 0x00000008 gran 0x03 io PNP: 002e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PCI: 00:01.0 assign_resources, bus 0 link: 0 PCI: 00:01.1 10 <- [0x0000002c00 - 0x0000002c3f] size 0x00000040 gran 0x06 io PCI: 00:01.1 20 <- [0x0000002c40 - 0x0000002c7f] size 0x00000040 gran 0x06 io PCI: 00:01.1 24 <- [0x0000002c80 - 0x0000002cbf] size 0x00000040 gran 0x06 io PCI: 00:01.1 60 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 64 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 68 <- [0x0000002800 - 0x00000028ff] size 0x00000100 gran 0x08 io PCI: 00:01.1 assign_resources, bus 1 link: 0 PCI: 00:01.1 assign_resources, bus 1 link: 0 PCI: 00:01.3 10 <- [0x00fc100000 - 0x00fc13ffff] size 0x00040000 gran 0x12 mem PCI: 00:02.0 10 <- [0x00fc145000 - 0x00fc145fff] size 0x00001000 gran 0x0c mem PCI: 00:02.1 10 <- [0x00fc14a000 - 0x00fc14a0ff] size 0x00000100 gran 0x08 mem PCI: 00:04.0 20 <- [0x0000002cc0 - 0x0000002ccf] size 0x00000010 gran 0x04 io PCI: 00:05.0 10 <- [0x0000003000 - 0x0000003007] size 0x00000008 gran 0x03 io PCI: 00:05.0 14 <- [0x0000003038 - 0x000000303b] size 0x00000004 gran 0x02 io PCI: 00:05.0 18 <- [0x0000003008 - 0x000000300f] size 0x00000008 gran 0x03 io PCI: 00:05.0 1c <- [0x000000303c - 0x000000303f] size 0x00000004 gran 0x02 io PCI: 00:05.0 20 <- [0x0000002cd0 - 0x0000002cdf] size 0x00000010 gran 0x04 io PCI: 00:05.0 24 <- [0x00fc146000 - 0x00fc146fff] size 0x00001000 gran 0x0c mem PCI: 00:05.1 10 <- [0x0000003010 - 0x0000003017] size 0x00000008 gran 0x03 io PCI: 00:05.1 14 <- [0x0000003040 - 0x0000003043] size 0x00000004 gran 0x02 io PCI: 00:05.1 18 <- [0x0000003018 - 0x000000301f] size 0x00000008 gran 0x03 io PCI: 00:05.1 1c <- [0x0000003044 - 0x0000003047] size 0x00000004 gran 0x02 io PCI: 00:05.1 20 <- [0x0000002ce0 - 0x0000002cef] size 0x00000010 gran 0x04 io PCI: 00:05.1 24 <- [0x00fc147000 - 0x00fc147fff] size 0x00001000 gran 0x0c mem PCI: 00:05.2 10 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran 0x03 io PCI: 00:05.2 14 <- [0x0000003048 - 0x000000304b] size 0x00000004 gran 0x02 io PCI: 00:05.2 18 <- [0x0000003028 - 0x000000302f] size 0x00000008 gran 0x03 io PCI: 00:05.2 1c <- [0x000000304c - 0x000000304f] size 0x00000004 gran 0x02 io PCI: 00:05.2 20 <- [0x0000002cf0 - 0x0000002cff] size 0x00000010 gran 0x04 io PCI: 00:05.2 24 <- [0x00fc148000 - 0x00fc148fff] size 0x00001000 gran 0x0c mem PCI: 00:06.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus PCI: 00:06.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus PCI: 00:06.0 20 <- [0x00fc1fffff - 0x00fc1ffffe] size 0x00000000 gran 0x14 bus PCI: 00:06.1 10 <- [0x00fc140000 - 0x00fc143fff] size 0x00004000 gran 0x0e mem PCI: 00:08.0 10 <- [0x00fc149000 - 0x00fc149fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 14 <- [0x0000003030 - 0x0000003037] size 0x00000008 gran 0x03 io PCI: 00:08.0 18 <- [0x00fc14a100 - 0x00fc14a1ff] size 0x00000100 gran 0x08 mem PCI: 00:08.0 1c <- [0x00fc14a200 - 0x00fc14a20f] size 0x00000010 gran 0x04 mem PCI: 00:0a.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus PCI: 00:0a.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus PCI: 00:0a.0 20 <- [0x00fc1fffff - 0x00fc1ffffe] size 0x00000000 gran 0x14 bus PCI: 00:0c.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus PCI: 00:0c.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus PCI: 00:0c.0 20 <- [0x00fc1fffff - 0x00fc1ffffe] size 0x00000000 gran 0x14 bus PCI: 00:0d.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus PCI: 00:0d.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus PCI: 00:0d.0 20 <- [0x00fc1fffff - 0x00fc1ffffe] size 0x00000000 gran 0x14 bus PCI: 00:0f.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus PCI: 00:0f.0 24 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 bus PCI: 00:0f.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus PCI: 00:0f.0 assign_resources, bus 5 link: 0 PCI: 05:00.0 10 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b pref PCI: 05:00.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 05:00.0 18 <- [0x00fc020000 - 0x00fc02ffff] size 0x00010000 gran 0x10 mem PCI: 05:00.0 30 <- [0x00fc000000 - 0x00fc01ffff] size 0x00020000 gran 0x11 rome PCI: 05:00.1 10 <- [0x00fc030000 - 0x00fc03ffff] size 0x00010000 gran 0x10 mem PCI: 00:0f.0 assign_resources, bus 5 link: 0 PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 g#� #END I've marked the logs, i hope it helps. Thanks

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coreboot October 2015