January 2014 - coreboot - mail.coreboot.org

Coreboot for DQ77KB
by Krzysztof Pierwieniecki Jan. 6, 2014

Jan. 6, 2014

Hello, My name is Chris. I would like to adjust the coreboot to my DQ77KB board. For payload I used seabios. I managed to reach point when OS starts but I have a problem with Intel ME PCI devices (ME1, ME2, KT, IDE-R). A device manager in Windows7 reports an error 10 or 12 with these devices and that depends of irq configuration and how many ME devices are on. There is no problem with other PCi devices. Is it may caused by incorrect irq configuration or something else, like insufficient initialization of ME Firmware? During booting coreboot ME FW reports that firmware initialization is complete and established communication with host. Best regards, Chris

1 0

Systemagent hangs on PCH init with H61 chipset
by Alex G. Jan. 6, 2014

Jan. 6, 2014

Is there anything special that systemagent needs before it will actually do something useful. I've tried to run it on a board with a H61 chipset, and it just hangs at "System Agent: Initializing PCH". I remember Damien had a similar problem a few months back. Alex coreboot-4.0-5198-g2588498-dirty Mon Jan 6 02:30:48 CST 2014 starting... Setting up static southbridge registers... done. Disabling Watchdog reboot... done. Setting up static northbridge registers... done. Graphics not supported by this CPU/chipset. Back from sandybridge_early_initialization() POST: 0x38 SMBus controller enabled. POST: 0x39 POST: 0x3a CPU id(306a9): Intel(R) Celeron(R) CPU G1610 @ 2.60GHz AES NOT supported, TXT NOT supported, VT supported PCH type: H61, device id: 1c5c, rev id 5 Intel ME early init Intel ME firmware is ready ME: Requested 16MB UMA Starting UEFI PEI System Agent Read scrambler seed 0x0000b341 from CMOS 0x98 Read S3 scrambler seed 0x00009b9a from CMOS 0x9c find_current_mrc_cache_local: No valid MRC cache found. System Agent: Starting up... System Agent: Initializing PCH

1 0

Re: [coreboot] New laptop: Lenovo ThinkPad X230 tablet, with dumps to go with it
by Vladimir 'φ-coder/phcoder' Serbinenko Jan. 4, 2014

Jan. 4, 2014

On 15.09.2012 05:47, Keith Hui wrote: > Hi all, > > I'm back. With a new laptop. > > I'm now rocking a Lenovo x230 tablet, http://review.coreboot.org/#/c/4614/

1 0

Re: [coreboot] Are any Chromebooks able to run fully libre?
by David Hubbard Jan. 4, 2014

Jan. 4, 2014

On Sat, Jan 4, 2014 at 4:14 AM, Sam Kuper <sam.kuper(a)uclmail.net> wrote: > What would you recommend as a good primer (textbook; website; manual; > whatever) that would give someone with limited experience enough knowledge > to avoid making that mistake and others like it? > > I think Peter means the IBM PC architecture: the legacy layer on layer from the original IBM PC to modern laptops. To a first approximation, Coreboot can be considered an attempt to replace a big chunk of it with free software, so I'd guess most people on this list would never confuse the Programmable Interrupt Controller with the Microchip PIC CPU. After Coreboot hands over control to the OS kernel, it's really amazing how much abstraction hides the reality of the system from the OS. (And then the OS hides even more details from userspace, and so forth.) To directly answer what you asked, start here: http://wiki.osdev.org/Main_Page - it may take a while, especially if you're not the intended audience (writing a custom OS from scratch), but it's a good overview. Regards, David

1 0

Re: [coreboot] Are any Chromebooks able to run fully libre?
by Peter Stuge Jan. 4, 2014

Jan. 4, 2014

Sam Kuper wrote: > Brossard Not a very nice word around here. Don't take people's word for things, Sam, but do more research yourself. The internet and even people presenting at conferences are not indisputable sources. Brossard included the abbreviation PIC in one of the slides for his talk about how he supposedly created a backdoored BIOS (using an open source x86 firmware implementation). He identified PIC as one of the components on PC mainboards. Unfortunately he seems to think that PIC refers to the family of microcontrollers developed by Microchip instead of what it really refers to; something very different, a quite well-understood and rather fundamental component for everyone with strong knowledge about PC technology. //Peter

2 2

Re: [coreboot] Are any Chromebooks able to run fully libre?
by Peter Stuge Jan. 3, 2014

Jan. 3, 2014

Gabe Black wrote: > #2 has already largely been addressed in the Exynos, Tegra and > Beaglebone ports. Is that once in each port or once in the entire tree? //Peter

3 2

Re: [coreboot] Are any Chromebooks able to run fully libre?
by mrnuke Jan. 3, 2014

Jan. 3, 2014

On Thursday, January 02, 2014 11:28:14 PM Sam Kuper wrote: > On the C7/C710 and Pavilion 14 as shipped, where are those microcode > updates stored? > This [1] should help you extract a stock coreboot.rom that you can cbfstool with. The rest is left as an exercise to the reader. (Short answer: cpu_microcode_blob.bin in CBFS) > > And > > how exactly is a CPU different if the microcode update is patched in the > > factory rather than uploaded at boot? It's the same microcode in the end. > > First of all, if some microcode is in the CPU from the factory rather > [yada, yada, yada] I don't care for any Stallmanian lecturing on how microcode updates work. I've worked with them, I've written code to upload them, and I've seen firsthand how their absence bricks a system. With the risk of sounding arrogant, that gives me the credit to avoid your uninformed lecturing. You have the option in coreboot to not include them. Period. What I gather from your description is that you want is the CPU that works best without microcode updates. Ask around, or test yourself. I don't think many people have tested without microcode updates. Alex [1] http://www.chromium.org/chromium-os/developer-information-for-chrome-os-dev…

3 2

Re: [coreboot] Are any Chromebooks able to run fully libre?
by mrnuke Jan. 2, 2014

Jan. 2, 2014

On Friday, January 03, 2014 12:37:34 AM Sam Kuper wrote: > Thank you, but unfortunately, I don't own a Samsung Series 5 550 or a > Series 3 Chromebox, nor any other CrOS device from which to extract a > stock coreboot.rom. > There was some guide somewhere on how to download the stock ROM. > I freely admit I'm not terribly well-informed on the subject. That's > why I'm reading to learn as much as I can and asking questions here to > fill in the gaps. > The presence of CPU microcode should be the least of your concerns. Really. How about an out-of-band processor with full DMA access, and networking access transparent to the OS? Seriously, the CPU microcode is nothing. Besides, nobody cares if an internal PLL is configured properly so that the CPU can switch to its highest clock without hanging. > - Server: x86, not necessarily Intel, with Core Solo performance or > better, that supports 16GB+ of RAM with double bit error correction > (e.g. Chipkill). AMD is your best bet, but be prepared to get your feet wet. Server boards are hard to find, and you'll most likely need to port it. > - Laptop/netbook: not necessarily x86, with Core Solo performance or > better, that supports 2GB+ of RAM. > Chromebook, if you actually want to vote on free firmware. If you want to stick it to Intel (which I think you should), there are ARM models available. I also hear rumours of an octa-core coming soon. There are also some well-supported Lenovos, but getting one counts as not voting. > Some Trisquel folks are running without microcode updates.[2] > Sounds like a foul's paradise. Their firmware most likely installs some microcode updates. > Anyhow, since I've managed inadvertently to generate a couple of > slightly tetchy replies here since I started this thread (i.e. yours > and the earlier one from Gregg Levine), maybe that's a hint that I'm > asking too many questions or something, and that I should take my > leave for now? > Ask away, but please keep Stallmanism out of it. CPU microcode is better compared to a hardware descriptor than a set of instructions, and it's probably a mix of both. It's definitely not software in the normal sense of the word. Alex

2 1

Re: [coreboot] Are any Chromebooks able to run fully libre?
by mrnuke Jan. 2, 2014

Jan. 2, 2014

On Thursday, January 02, 2014 09:16:25 PM Sam Kuper wrote: > My earlier question about the Acer C7/C710 and HP Pavilion 14 was > motivated by the following consideration: if they have not been found > to have CPU errata warranting uploading of CPU microcode, then they > might be (at least in this respect) preferable to the X60 which forces > the user to choose between uploading microcode or running with known > vulnerabilities.* > What are you talking about? x86 Chromebooks ship with microcode updates. And how exactly is a CPU different if the microcode update is patched in the factory rather than uploaded at boot? It's the same microcode in the end. This microcode discussion is ridiculous: I'm not going to change the oil in my engine because I don't understand how it lubricates the crankshaft. Alex

2 1

Re: [coreboot] Are any Chromebooks able to run fully libre?
by Patrick Georgi Jan. 2, 2014

Jan. 2, 2014

Am 02.01.2014 21:31, schrieb Sam Kuper: > I see that coming within case 2. The Intel CPU microcode I gave as an > example has this problem, IIUC. Perhaps I'm wrong, but I see it as > being like the Content Scramble System (CSS), AACS, etc, and we're > waiting for someone to create the equivalent of DeCSS, etc, so that > libre (or at least open source) alternative microcode can be made to > exist that would actually work on the CPU. For CSS and AACS, the organizing body has to provide keys to vendors, and keep all of them compatible with pretty much every disc out there. Here we have one vendor, and the files are typically not transferrable across chip versions, so they can create a new key for every version, limiting the impact. If I remember things correctly, Intel uses RSA-2048 signatures on a SHA256 hash. The capability to crack such a scheme probably provides more lucrative opportunities than firmware freedom and that makes me guess people would routinely do it, if possible. How about simply refusing to pay for malfeatures like these instead of increasing the platform's value for vendors that absolutely don't want you to do it for them (as expressed by both their conduct and their signature scheme)? Patrick

2 1