coreboot June 2012

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New patch to review for coreboot: 38762c8 libpayload: Detach unresponsive usb mass storage devices
by Nico Huber 20 Jun '12

20 Jun '12

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1121 -gerrit commit 38762c83cc8071aebdaaa35cb5befe6682f9fdc3 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Jun 1 09:50:11 2012 +0200 libpayload: Detach unresponsive usb mass storage devices This enables logical detachment of unresponsive usb devices (i.e. devices not responding to control transfers) in the usb mass storage driver. Without the detection of unresponsive devices we wait way too long for the device to become ready. Change-Id: I8b8cf327f49dde25afaca4d3066f16ea86b99d3d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/drivers/usb/usb.c | 23 +++-- payloads/libpayload/drivers/usb/usbmsc.c | 151 +++++++++++++++++++---------- payloads/libpayload/include/usb/usb.h | 2 +- 3 files changed, 116 insertions(+), 60 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 07735a2..aa47c4a 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -205,7 +205,7 @@ set_configuration (usbdev_t *dev) dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0); } -void +int clear_feature (usbdev_t *dev, int endp, int feature, int rtype) { dev_req_t dr; @@ -216,7 +216,7 @@ clear_feature (usbdev_t *dev, int endp, int feature, int rtype) dr.wValue = feature; dr.wIndex = endp; dr.wLength = 0; - dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0); + return dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0); } int @@ -227,9 +227,9 @@ clear_stall (endpoint_t *ep) int rtype = gen_bmRequestType (host_to_device, standard_type, endp ? endp_recp : dev_recp); - clear_feature (dev, endp, ENDPOINT_HALT, rtype); + int ret = clear_feature (dev, endp, ENDPOINT_HALT, rtype); ep->toggle = 0; - return 0; + return ret; } /* returns free address or -1 */ @@ -458,12 +458,21 @@ set_address (hci_t *controller, int speed, int hubport, int hubaddr) return adr; } +/* + * Should be called by the hub drivers whenever a physical detach occurs + * and can be called by usb class drivers if they are unsatisfied with a + * malfunctioning device. + */ void usb_detach_device(hci_t *controller, int devno) { - controller->devices[devno]->destroy (controller->devices[devno]); - free(controller->devices[devno]); - controller->devices[devno] = 0; + /* check if device exists, as we may have + been called yet by the usb class driver */ + if (controller->devices[devno]) { + controller->devices[devno]->destroy (controller->devices[devno]); + free(controller->devices[devno]); + controller->devices[devno] = NULL; + } } int diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index fd6517a..d1e3302 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -106,10 +106,22 @@ typedef struct { unsigned char bCSWStatus; } __attribute__ ((packed)) csw_t; +enum { + /* + * MSC commands can be + * successful, + * fail with proper response or + * fail totally, which results in detaching of the usb device. + * In the latter case the caller has to make sure, that he won't + * use the device any more. + */ + MSC_COMMAND_OK = 0, MSC_COMMAND_FAIL, MSC_COMMAND_DETACHED +}; + static int request_sense (usbdev_t *dev); -static void +static int reset_transport (usbdev_t *dev) { dev_req_t dr; @@ -124,9 +136,17 @@ reset_transport (usbdev_t *dev) dr.wValue = 0; dr.wIndex = 0; dr.wLength = 0; - dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0); - clear_stall (MSC_INST (dev)->bulk_in); - clear_stall (MSC_INST (dev)->bulk_out); + + /* if any of these fails, detach device, as we are lost */ + if (dev->controller->control (dev, OUT, sizeof (dr), &dr, 0, 0) || + clear_stall (MSC_INST (dev)->bulk_in) || + clear_stall (MSC_INST (dev)->bulk_out)) { + printf ("Detaching unresponsive device.\n"); + usb_detach_device (dev->controller, dev->address); + return MSC_COMMAND_DETACHED; + } + /* return fail as we are only called in case of failure */ + return MSC_COMMAND_FAIL; } /* device may stall this command, so beware! */ @@ -177,20 +197,18 @@ get_csw (endpoint_t *ep, csw_t *csw) clear_stall (ep); if (ep->dev->controller->bulk (ep, sizeof (csw_t), (u8 *) csw, 1)) { - reset_transport (ep->dev); - return 1; + return reset_transport (ep->dev); } } if (csw->dCSWTag != tag) { - reset_transport (ep->dev); - return 1; + return reset_transport (ep->dev); } - return 0; + return MSC_COMMAND_OK; } static int execute_command (usbdev_t *dev, cbw_direction dir, const u8 *cb, int cblen, - u8 *buf, int buflen) + u8 *buf, int buflen, int residue_ok) { cbw_t cbw; csw_t csw; @@ -202,43 +220,48 @@ execute_command (usbdev_t *dev, cbw_direction dir, const u8 *cb, int cblen, wrap_cbw (&cbw, buflen, dir, cb, cblen); if (dev->controller-> bulk (MSC_INST (dev)->bulk_out, sizeof (cbw), (u8 *) &cbw, 0)) { - reset_transport (dev); - return 1; + return reset_transport (dev); } if (buflen > 0) { if (dir == cbw_direction_data_in) { if (dev->controller-> bulk (MSC_INST (dev)->bulk_in, buflen, buf, 0)) { clear_stall (MSC_INST (dev)->bulk_in); - return 1; + return MSC_COMMAND_FAIL; } } else { if (dev->controller-> bulk (MSC_INST (dev)->bulk_out, buflen, buf, 0)) { clear_stall (MSC_INST (dev)->bulk_out); - return 1; + return MSC_COMMAND_FAIL; } } } - if (get_csw (MSC_INST (dev)->bulk_in, &csw)) - return 1; - if (always_succeed == 1) { - // return success, regardless of message - return 0; - } - if (csw.bCSWStatus == 2) { - // phase error, reset transport - reset_transport (dev); - return 1; - } - if (csw.bCSWStatus == 0) { - // no error, exit - return 0; + int ret = get_csw (MSC_INST (dev)->bulk_in, &csw); + if (ret) { + return ret; + } else if (always_succeed == 1) { + /* return success, regardless of message */ + return MSC_COMMAND_OK; + } else if (csw.bCSWStatus == 2) { + /* phase error, reset transport */ + return reset_transport (dev); + } else if (csw.bCSWStatus == 0) { + if ((csw.dCSWDataResidue == 0) || residue_ok) + /* no error, exit */ + return MSC_COMMAND_OK; + else + /* missed some bytes */ + return MSC_COMMAND_FAIL; + } else { + if (cb[0] == 0x03) + /* requesting sense failed, that's bad */ + return MSC_COMMAND_FAIL; + /* error "check condition" or reserved error */ + ret = request_sense (dev); + /* return fail or the status of request_sense if it's worse */ + return ret ? ret : MSC_COMMAND_FAIL; } - if (cb[0] != 0x03) /* 0x03 == request sense */ - // error "check condition" or reserved error - request_sense (dev); - return 1; } typedef struct { @@ -309,7 +332,8 @@ readwrite_blocks (usbdev_t *dev, int start, int n, cbw_direction dir, u8 *buf) cb.numblocks = htonw (n); return execute_command (dev, dir, (u8 *) &cb, sizeof (cb), buf, - n * MSC_INST(dev)->blocksize); + n * MSC_INST(dev)->blocksize, 0) + != MSC_COMMAND_OK ? 1 : 0; } /* Only request it, we don't interpret it. @@ -324,7 +348,7 @@ request_sense (usbdev_t *dev) cb.command = 0x3; return execute_command (dev, cbw_direction_data_in, (u8 *) &cb, - sizeof (cb), buf, 19); + sizeof (cb), buf, 19, 1); } static int @@ -333,7 +357,7 @@ test_unit_ready (usbdev_t *dev) cmdblock6_t cb; memset (&cb, 0, sizeof (cb)); // full initialization for T-U-R return execute_command (dev, cbw_direction_data_out, (u8 *) &cb, - sizeof (cb), 0, 0); + sizeof (cb), 0, 0, 0); } static int @@ -344,10 +368,10 @@ spin_up (usbdev_t *dev) cb.command = 0x1b; cb.lun = 1; return execute_command (dev, cbw_direction_data_out, (u8 *) &cb, - sizeof (cb), 0, 0); + sizeof (cb), 0, 0, 0); } -static void +static int read_capacity (usbdev_t *dev) { cmdblock_t cb; @@ -356,12 +380,20 @@ read_capacity (usbdev_t *dev) u8 buf[8]; debug ("Reading capacity of mass storage device.\n"); - int count = 0; - while ((count++ < 20) - && - (execute_command - (dev, cbw_direction_data_in, (u8 *) &cb, sizeof (cb), buf, - 8) == 1)); + int count = 0, ret; + while (count++ < 20) { + switch (ret = execute_command + (dev, cbw_direction_data_in, (u8 *) &cb, + sizeof (cb), buf, 8, 0)) { + case MSC_COMMAND_OK: + break; + case MSC_COMMAND_FAIL: + continue; + default: /* if it's worse return */ + return ret; + } + break; + } if (count >= 20) { // still not successful, assume 2tb in 512byte sectors, which is just the same garbage as any other number, but probably more usable. printf (" assuming 2 TB with 512-byte sectors as READ CAPACITY didn't answer.\n"); @@ -377,6 +409,7 @@ read_capacity (usbdev_t *dev) MSC_INST (dev)->numblocks > 1000000 ? (MSC_INST (dev)->numblocks / 1000) * MSC_INST (dev)->blocksize / 1000 : MSC_INST (dev)->numblocks * MSC_INST (dev)->blocksize / 1000 / 1000); + return MSC_COMMAND_OK; } void @@ -444,12 +477,21 @@ usb_msc_init (usbdev_t *dev) printf (" Waiting for device to become ready..."); timeout = 30 * 10; /* SCSI/ATA specs say we have to wait up to 30s. Ugh */ - while (test_unit_ready (dev) && --timeout) { - mdelay (100); - if (!(timeout % 10)) - printf ("."); + while (timeout--) { + switch (test_unit_ready (dev)) { + case MSC_COMMAND_OK: + break; + case MSC_COMMAND_FAIL: + mdelay (100); + if (!(timeout % 10)) + printf ("."); + continue; + default: /* if it's worse return */ + return; + } + break; } - if (test_unit_ready (dev)) { + if (timeout < 0) { printf ("timeout. Device not ready. Still trying...\n"); } else { printf ("ok.\n"); @@ -458,15 +500,20 @@ usb_msc_init (usbdev_t *dev) debug (" spin up"); for (i = 0; i < 30; i++) { debug ("."); - if (!spin_up (dev)) { + switch (spin_up (dev)) { + case MSC_COMMAND_OK: debug (" OK."); break; + case MSC_COMMAND_FAIL: + mdelay (100); + continue; + default: /* if it's worse return */ + return; } - mdelay (100); + break; } debug ("\n"); - read_capacity (dev); - if (usbdisk_create) + if ((read_capacity (dev) == MSC_COMMAND_OK) && usbdisk_create) usbdisk_create (dev); } diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index ee9c50b..ecfee54 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -215,7 +215,7 @@ void init_device_entry (hci_t *controller, int num); void set_feature (usbdev_t *dev, int endp, int feature, int rtype); void get_status (usbdev_t *dev, int endp, int rtype, int len, void *data); -void clear_feature (usbdev_t *dev, int endp, int feature, int rtype); +int clear_feature (usbdev_t *dev, int endp, int feature, int rtype); int clear_stall (endpoint_t *ep); void usb_nop_init (usbdev_t *dev);

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New patch to review for coreboot: 2135803 libpayload: Adjust timeout in EHCI driver
by Nico Huber 20 Jun '12

20 Jun '12

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1120 -gerrit commit 2135803937676a68fba0a6ccaba9424874b454ff Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Jun 1 08:54:29 2012 +0200 libpayload: Adjust timeout in EHCI driver Tested with a bunch of usb flash sticks. The slowest non-TUR (test unit ready) turn around took about 1.3s, so this commit increases the timeout to 2s. Change-Id: Iec64b5cc48d51912b2bdeeebb5885399a71311b2 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/drivers/usb/ehci.c | 12 ++++++++---- 1 files changed, 8 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 1094c78..9e17571 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -169,11 +169,15 @@ static int wait_for_tds(qtd_t *head) if (0) dump_td(virt_to_phys(cur)); /* wait for results */ - /* TOTEST: how long to wait? - * tested with some USB2.0 flash sticks: - * slowest took around 180ms + /* how long to wait? + * tested with some USB2.0 flash sticks: + * TUR turn around took + * about 2s for the slowest (14cd:121c) + * max. 250ms for the others + * slowest non-TUR turn around took about 1.3s + * try 2s for now as a failed TUR is not fatal */ - int timeout = 10000; /* time out after 10000 * 50us == 500ms */ + int timeout = 40000; /* time out after 40000 * 50us == 2s */ while ((cur->token & QTD_ACTIVE) && !(cur->token & QTD_HALTED) && timeout--) udelay(50);

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Patch set updated for coreboot: 4e52072 libpayload: Better error detection in USB mass storage
by Nico Huber 20 Jun '12

20 Jun '12

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1072 -gerrit commit 4e520725dd227ade37be9274ac499671e50e7b93 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon May 21 14:05:41 2012 +0200 libpayload: Better error detection in USB mass storage This implements status transport (CSW) more closely to the standard (usbmassbulk_10). Change-Id: Ife516316e054d4e87ebe698dc487eeb9ebcfd38d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/drivers/usb/usbmsc.c | 29 +++++++++++++++++++++-------- 1 files changed, 21 insertions(+), 8 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c index 8d57736..fd6517a 100644 --- a/payloads/libpayload/drivers/usb/usbmsc.c +++ b/payloads/libpayload/drivers/usb/usbmsc.c @@ -151,8 +151,8 @@ get_max_luns (usbdev_t *dev) return luns; } -int tag; -int lun = 0; +unsigned int tag; +unsigned char lun = 0; static void wrap_cbw (cbw_t *cbw, int datalen, cbw_direction dir, const u8 *cmd, @@ -161,7 +161,7 @@ wrap_cbw (cbw_t *cbw, int datalen, cbw_direction dir, const u8 *cmd, memset (cbw, 0, sizeof (cbw_t)); cbw->dCBWSignature = cbw_signature; - cbw->dCBWTag = tag++; + cbw->dCBWTag = ++tag; cbw->bCBWLUN = lun; // static value per device cbw->dCBWDataTransferLength = datalen; @@ -170,11 +170,22 @@ wrap_cbw (cbw_t *cbw, int datalen, cbw_direction dir, const u8 *cmd, cbw->bCBWCBLength = cmdlen; } -static void +static int get_csw (endpoint_t *ep, csw_t *csw) { - if (ep->dev->controller->bulk (ep, sizeof (csw_t), (u8 *) csw, 1)) + if (ep->dev->controller->bulk (ep, sizeof (csw_t), (u8 *) csw, 1)) { clear_stall (ep); + if (ep->dev->controller->bulk + (ep, sizeof (csw_t), (u8 *) csw, 1)) { + reset_transport (ep->dev); + return 1; + } + } + if (csw->dCSWTag != tag) { + reset_transport (ep->dev); + return 1; + } + return 0; } static int @@ -209,7 +220,8 @@ execute_command (usbdev_t *dev, cbw_direction dir, const u8 *cb, int cblen, } } } - get_csw (MSC_INST (dev)->bulk_in, &csw); + if (get_csw (MSC_INST (dev)->bulk_in, &csw)) + return 1; if (always_succeed == 1) { // return success, regardless of message return 0; @@ -223,8 +235,9 @@ execute_command (usbdev_t *dev, cbw_direction dir, const u8 *cb, int cblen, // no error, exit return 0; } - // error "check condition" or reserved error - request_sense (dev); + if (cb[0] != 0x03) /* 0x03 == request sense */ + // error "check condition" or reserved error + request_sense (dev); return 1; }

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Patch set updated for coreboot: 1d0fd11 i5000: fix another typo
by Sven Schnelle 20 Jun '12

20 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1119 -gerrit commit 1d0fd1106c1ec73d4d5d02d2ce2c88ed59ac5d87 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 16:59:15 2012 +0200 i5000: fix another typo As Mathias Krause pointed out, using movw/outw on %al is clearly invalid. Let's do another typo fix... Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i5000/halt_second_bsp.S | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S index 30e6d89..041807e 100644 --- a/src/northbridge/intel/i5000/halt_second_bsp.S +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -14,8 +14,8 @@ /* perform hard reset */ movw $0xcf9, %dx - movw $0x06, %al - outw %al, %dx + movb $0x06, %al + outb %al, %dx loop0: hlt jmp loop0

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Patch set updated for coreboot: 810f6d3 Fix another typo
by Sven Schnelle 20 Jun '12

20 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1119 -gerrit commit 810f6d3b5fef690b4e50113114493cc1d0f6e768 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 16:59:15 2012 +0200 Fix another typo As minipli pointed out, using movw/outw on %al is clearly invalid. Let's do another typo fix... Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i5000/halt_second_bsp.S | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S index 30e6d89..041807e 100644 --- a/src/northbridge/intel/i5000/halt_second_bsp.S +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -14,8 +14,8 @@ /* perform hard reset */ movw $0xcf9, %dx - movw $0x06, %al - outw %al, %dx + movb $0x06, %al + outb %al, %dx loop0: hlt jmp loop0

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New patch to review for coreboot: 86d76da Fix another typo
by Sven Schnelle 20 Jun '12

20 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1119 -gerrit commit 86d76da2e746a58878529452e783482192fbb18c Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 16:59:15 2012 +0200 Fix another typo As minipli pointed out, movw %al, %dx is clearly invalid. Let's do another typo fix... Change-Id: Ib95832a11097f599a236ab30c64c26ef429a1699 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i5000/halt_second_bsp.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S index 30e6d89..eb3d295 100644 --- a/src/northbridge/intel/i5000/halt_second_bsp.S +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -15,7 +15,7 @@ /* perform hard reset */ movw $0xcf9, %dx movw $0x06, %al - outw %al, %dx + outb %al, %dx loop0: hlt jmp loop0

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Patch merged into coreboot/master: f42c3ba i5000: fix typos
by gerrit＠coreboot.org 20 Jun '12

20 Jun '12

the following patch was just integrated into master: commit f42c3ba0bd2cbc4fca87ce38b2e134679b84e126 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 15:36:53 2012 +0200 i5000: fix typos Peter and Ron pointed out two typos. They have no side effects, but it's still worth to fix them. Change-Id: I9aecccdbc72beb2623fbe558a06e4f1b050f6e74 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Wed Jun 20 16:36:56 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Wed Jun 20 16:37:18 2012, giving +2 See http://review.coreboot.org/1117 for details. -gerrit

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New patch to review for coreboot: e1cf05d i3100: Enable second IOAPIC for PCI-X
by Sven Schnelle 20 Jun '12

20 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1118 -gerrit commit e1cf05d4172b1335fc39481b0f4a0cd8a5d5decf Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 16:25:55 2012 +0200 i3100: Enable second IOAPIC for PCI-X i3100/i5000 have a second IOAPIC which handles IRQs for PCI-X. Add code to enable it. Change-Id: Ib447628f501b152c8adc9c7c89bd09b5615b9e5a Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i3100/Makefile.inc | 1 + src/southbridge/intel/i3100/ioapic.c | 61 ++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 0 deletions(-) diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc index fa6caf1..ddcb0f9 100644 --- a/src/southbridge/intel/i3100/Makefile.inc +++ b/src/southbridge/intel/i3100/Makefile.inc @@ -5,5 +5,6 @@ driver-y += sata.c driver-y += ehci.c driver-y += smbus.c driver-y += pci.c +driver-y += ioapic.c ramstage-y += reset.c ramstage-y += pciexp_portb.c diff --git a/src/southbridge/intel/i3100/ioapic.c b/src/southbridge/intel/i3100/ioapic.c new file mode 100644 index 0000000..446be9e --- /dev/null +++ b/src/southbridge/intel/i3100/ioapic.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "i3100.h" + + +static void read_resources(struct device *dev) +{ + u32 tmp; + + /* Enable IO(X)APIC config space */ + tmp = pci_read_config16(dev, 0x40); + pci_write_config16(dev, 0x40, tmp & ~(1 << 13)); + /* Enable I/O APIC space at 0xfec80000 */ + dev->path.pci.devfn |= 1; + pci_write_config16(dev, 0x04, 0x06); + pci_write_config32(dev, 0x10, 0xfec80000); + dev->path.pci.devfn &= ~1; + pci_write_config16(dev, 0x40, tmp); + + pci_bus_read_resources(dev); +} + +static struct device_operations pci_ops = { + .read_resources = read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = 0, + +}; + +static const struct pci_driver pci_driver0 __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x3500, +}; +

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Patch set updated for coreboot: 90ccbbf i3100: add smbus_write_byte()
by Sven Schnelle 20 Jun '12

20 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1116 -gerrit commit 90ccbbf58200298cdec3194bcae25a24de0c787b Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 14:54:08 2012 +0200 i3100: add smbus_write_byte() Required for Supermicro X7DB8, which needs the FBDIMM clock generator setup during romstage. Change-Id: I30ca8354087e851487aee0614595782131d4d9bc Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/southbridge/intel/i3100/early_smbus.c | 7 ++++- src/southbridge/intel/i3100/smbus.h | 43 +++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 1 deletions(-) diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c index f3d4450..3908390 100644 --- a/src/southbridge/intel/i3100/early_smbus.c +++ b/src/southbridge/intel/i3100/early_smbus.c @@ -37,7 +37,12 @@ static void enable_smbus(void) outb(0, SMBUS_IO_BASE + SMBHSTCTL); } -static int smbus_read_byte(u32 device, u32 address) +static __attribute__((unused)) int smbus_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } + +static __attribute__((unused)) int smbus_write_byte(unsigned device, u8 address, u8 data) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); +} diff --git a/src/southbridge/intel/i3100/smbus.h b/src/southbridge/intel/i3100/smbus.h index 7023a5b..6879f0b 100644 --- a/src/southbridge/intel/i3100/smbus.h +++ b/src/southbridge/intel/i3100/smbus.h @@ -110,3 +110,46 @@ static int do_smbus_read_byte(u32 smbus_io_base, u16 device, u8 address) } return byte; } + +static __attribute__((unused)) int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data) +{ + unsigned char global_status_register; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(data, smbus_base + SMBHSTDAT0); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + + global_status_register = inb(smbus_base + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + if (global_status_register != (1 << 1)) + return SMBUS_ERROR; + + return 0; +}

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Patch set updated for coreboot: 74405c0 Add Supermicro X7DB8 motherboard
by Sven Schnelle 20 Jun '12

20 Jun '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/493 -gerrit commit 74405c0e323586fe84b4f46d99ae9e7c99564b14 Author: Sven Schnelle <svens(a)stackframe.org> Date: Wed Jun 20 14:56:46 2012 +0200 Add Supermicro X7DB8 motherboard This adds basic supported for the Supermicro X7DB8. Basic means that almost all onboard peripherals are working. Known problems are: - mptable needs to be written dynamically. If you plan to use Add on cards, modify mptable.c according to your needs. A patch to add generic mptable autogeneration based on devicetree is coming up. Change-Id: I5eaac32a8bafa69a05929cf08d869127b9464661 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/supermicro/Kconfig | 3 + src/mainboard/supermicro/x7db8/Kconfig | 47 +++++++ src/mainboard/supermicro/x7db8/Makefile.inc | 1 + src/mainboard/supermicro/x7db8/chip.h | 21 +++ src/mainboard/supermicro/x7db8/cmos.layout | 142 +++++++++++++++++++++ src/mainboard/supermicro/x7db8/devicetree.cb | 121 ++++++++++++++++++ src/mainboard/supermicro/x7db8/ioapic.h | 2 + src/mainboard/supermicro/x7db8/irq_tables.c | 57 +++++++++ src/mainboard/supermicro/x7db8/mainboard.c | 41 ++++++ src/mainboard/supermicro/x7db8/mptable.c | 90 ++++++++++++++ src/mainboard/supermicro/x7db8/romstage.c | 170 ++++++++++++++++++++++++++ 11 files changed, 695 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig index 80ffd6a..5b59110 100644 --- a/src/mainboard/supermicro/Kconfig +++ b/src/mainboard/supermicro/Kconfig @@ -25,6 +25,8 @@ config BOARD_SUPERMICRO_X6DHR_IG2 bool "X6DHR-iG2" config BOARD_SUPERMICRO_X6DHR_IG bool "X6DHR-iG" +config BOARD_SUPERMICRO_X7DB8 + bool "X7DB8 / X7DB8+ endchoice @@ -39,6 +41,7 @@ source "src/mainboard/supermicro/x6dhe_g2/Kconfig" source "src/mainboard/supermicro/x6dhe_g/Kconfig" source "src/mainboard/supermicro/x6dhr_ig2/Kconfig" source "src/mainboard/supermicro/x6dhr_ig/Kconfig" +source "src/mainboard/supermicro/x7db8/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/supermicro/x7db8/Kconfig b/src/mainboard/supermicro/x7db8/Kconfig new file mode 100644 index 0000000..393088f --- /dev/null +++ b/src/mainboard/supermicro/x7db8/Kconfig @@ -0,0 +1,47 @@ +if BOARD_SUPERMICRO_X7DB8 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA771 + select SOUTHBRIDGE_INTEL_I3100 + select NORTHBRIDGE_INTEL_I5000 + select SUPERIO_WINBOND_W83627HF + select MMCONF_SUPPORT + select BOARD_ROMSIZE_KB_512 + select HAVE_MP_TABLE + select HAVE_PIRQ_TABLE + +config MAINBOARD_DIR + string + default supermicro/x7db8 + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +config MAINBOARD_PART_NUMBER + string + default "X7DB8 / X7DB8+" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config IRQ_SLOT_COUNT + int + default 48 + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +endif diff --git a/src/mainboard/supermicro/x7db8/Makefile.inc b/src/mainboard/supermicro/x7db8/Makefile.inc new file mode 100644 index 0000000..8572512 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/Makefile.inc @@ -0,0 +1 @@ +#ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/supermicro/x7db8/chip.h b/src/mainboard/supermicro/x7db8/chip.h new file mode 100644 index 0000000..70f9bb4 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/chip.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/x7db8/cmos.layout b/src/mainboard/supermicro/x7db8/cmos.layout new file mode 100644 index 0000000..29e78ad --- /dev/null +++ b/src/mainboard/supermicro/x7db8/cmos.layout @@ -0,0 +1,142 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt +#938 46 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb new file mode 100644 index 0000000..7c90ba2 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/devicetree.cb @@ -0,0 +1,121 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/i5000 + + device lapic_cluster 0 on + chip cpu/intel/socket_LGA771 + device lapic 0 on end + end + end + + device pci_domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x15d9 0x2017 + end + + device pci 02.0 on # PCIe bridge + device pci 00.0 on + device pci 00.0 on + device pci 00.0 on end + device pci 02.0 on end + end + device pci 02.0 on + device pci 00.0 on + device pci 02.0 on + device pci 00.0 on end # e1000 #1 + device pci 00.1 on end # e1000 #2 + end + end + device pci 00.1 on end + end + end + device pci 00.1 on end + device pci 00.3 on end + end + + device pci 03.0 on end + device pci 04.0 on end + device pci 05.0 on end + device pci 06.0 on end + device pci 07.0 on end + device pci 10.0 on end # FBD + device pci 10.1 on end # FBD + device pci 10.2 on end # FBD + device pci 11.0 on end # FBD reserved + device pci 13.0 on end # FBD reserved + device pci 15.0 on end # FBD + device pci 16.0 on end # FBD + + chip southbridge/intel/i3100 + register "pirq_a_d" = "0x0b0b0b0b" + register "pirq_e_h" = "0x80808080" + register "sata_ports_implemented" = "0x3f" + + device pci 1c.0 on end # PCIe bridge + device pci 1d.0 on end # USB UHCI + device pci 1d.1 on end # USB UHCI + device pci 1d.2 on end # USB UHCI + device pci 1d.3 on end # USB UHCI + device pci 1d.7 on end # USB2 EHCI + device pci 1e.0 on + device pci 01.0 on + end + end + + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x15d9 0x2009 + chip superio/winbond/w83627hf + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 off end + device pnp 2e.5 on # KBC + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + + end + + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # Game port / MIDI + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 on end # GPIO3 + device pnp 2e.a on end # ACPI + device pnp 2e.b off end # HWMON + end + end + device pci 1f.1 off end # IDE + device pci 1f.2 on end # SATA + device pci 1f.3 off end # SMBUS + + end + end +end diff --git a/src/mainboard/supermicro/x7db8/ioapic.h b/src/mainboard/supermicro/x7db8/ioapic.h new file mode 100644 index 0000000..4ac7d62 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/ioapic.h @@ -0,0 +1,2 @@ +#define IOAPIC_I3100 2 +#define INTEL_IOAPIC_NUM_INTERRUPTS 24 diff --git a/src/mainboard/supermicro/x7db8/irq_tables.c b/src/mainboard/supermicro/x7db8/irq_tables.c new file mode 100644 index 0000000..84f456a --- /dev/null +++ b/src/mainboard/supermicro/x7db8/irq_tables.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x2670, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x1c << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1c << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x1, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x2, {{0x00, 0x0000}, {0x00, 0x0000}, {0x62, 0x1ef8}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1d << 3) | 0x3, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x63, 0x1ef8}}, 0, 0}, + {0x00, (0x1d << 3) | 0x7, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x1, {{0x60, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + {0x00, (0x1f << 3) | 0x2, {{0x00, 0x0000}, {0x61, 0x1ef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0, 0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c new file mode 100644 index 0000000..27a26f9 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/mainboard.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <delay.h> +#include <arch/coreboot_tables.h> +#include "chip.h" +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <arch/io.h> + +static void mainboard_enable(device_t dev) +{ +} + +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER) + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/supermicro/x7db8/mptable.c b/src/mainboard/supermicro/x7db8/mptable.c new file mode 100644 index 0000000..d0ddada --- /dev/null +++ b/src/mainboard/supermicro/x7db8/mptable.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int isa_bus; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + + mptable_write_buses(mc, NULL, &isa_bus); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, 9, 0x20, IO_APIC_ADDR + 0x80000); + + /* Legacy Interrupts */ + mptable_add_isa_interrupts(mc, isa_bus, 0x8, 0); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x00 << 2), 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x03 << 2), 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x04 << 2), 0x08, 0x10); + + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x02, (0x02 << 2), 0x08, 0x10); + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x08, 0x11); /* HD Audio 0:1b.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x08, 0x14); /* PCIe 0:1c.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x08, 0x15); /* PCIe 0:1c.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x08, 0x16); /* PCIe 0:1c.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x08, 0x17); /* PCIe 0:1c.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x08, 0x10); /* USB 0:1d.0 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x08, 0x11); /* USB 0:1d.1 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x08, 0x12); /* USB 0:1d.2 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x08, 0x13); /* USB 0:1d.3 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2), 0x08, 0x11); /* SATA 0:1f.2 */ + + /* e1000 */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x07, (0x00 << 2) | 0x00, 0x08, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x07, (0x00 << 2) | 0x01, 0x08, 0x13); + + /* SCSI on board */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x04, (0x02 << 2) | 0x00, 0x08, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x04, (0x02 << 2) | 0x01, 0x08, 0x11); + /* SCSI add on */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x08, (0x01 << 2) | 0x00, 0x09, 0x00); + + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0x00, MP_APIC_ALL, 0x00); + smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); + + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c new file mode 100644 index 0000000..6824111 --- /dev/null +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <superio/winbond/w83627hf/early_serial.c> +#include <northbridge/intel/i5000/raminit.h> +#include "northbridge/intel/i3100/i3100.h" +#include "southbridge/intel/i3100/i3100.h" +#include <southbridge/intel/i3100/early_smbus.c> + +#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) +#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) + +#define RCBA_RPC 0x0224 /* 32 bit */ + +#define RCBA_TCTL 0x3000 /* 8 bit */ + +#define RCBA_D31IP 0x3100 /* 32 bit */ +#define RCBA_D30IP 0x3104 /* 32 bit */ +#define RCBA_D29IP 0x3108 /* 32 bit */ +#define RCBA_D28IP 0x310C /* 32 bit */ +#define RCBA_D31IR 0x3140 /* 16 bit */ +#define RCBA_D30IR 0x3142 /* 16 bit */ +#define RCBA_D29IR 0x3144 /* 16 bit */ +#define RCBA_D28IR 0x3146 /* 16 bit */ + +#define RCBA_RTC 0x3400 /* 32 bit */ +#define RCBA_HPTC 0x3404 /* 32 bit */ +#define RCBA_GCS 0x3410 /* 32 bit */ +#define RCBA_BUC 0x3414 /* 8 bit */ +#define RCBA_FD 0x3418 /* 32 bit */ +#define RCBA_PRC 0x341C /* 32 bit */ + +static void early_config(void) +{ + u32 gcs, rpc, fd; + + /* Enable RCBA */ + pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1); + + /* Disable watchdog */ + gcs = read32(DEFAULT_RCBA + RCBA_GCS); + gcs |= (1 << 5); /* No reset */ + write32(DEFAULT_RCBA + RCBA_GCS, gcs); + + /* Configure PCIe port B as 4x */ + rpc = read32(DEFAULT_RCBA + RCBA_RPC); + rpc |= (3 << 0); + write32(DEFAULT_RCBA + RCBA_RPC, rpc); + + /* Disable Modem, Audio, PCIe ports 2/3/4 */ + fd = read32(DEFAULT_RCBA + RCBA_FD); + fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5); + write32(DEFAULT_RCBA + RCBA_FD, fd); + + /* Enable HPET */ + write32(DEFAULT_RCBA + RCBA_HPTC, (1 << 7)); + + /* Setup sata mode */ + pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, 0x40); +} + +#define DEFAULT_GPIOBASE 0x1180 +static void setup_gpio(void) +{ + pci_write_config32(PCI_DEV(0, 31, 0), 0x48, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCI_DEV(0, 31, 0), 0x4c, (1 << 4)); + + + outl(0xff0c79cf, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe700ffff, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0x65b70000, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x0000718a, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x00000106, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000301, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00030301, DEFAULT_GPIOBASE + 0x38); /* GPIO_LVL2 */ + +} + +static void i5000_lpc_config(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); +} + +int mainboard_set_fbd_clock(int speed) +{ + switch(speed) { + case 533: + smbus_write_byte(0x6f, 0x80, 0x21); + return 0; + case 667: + smbus_write_byte(0x6f, 0x80, 0x23); + return 0; + default: + printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed); + die(""); + return -1; + } +} + +void main(unsigned long bist) +{ + volatile int i; + if (bist == 0) + enable_lapic(); + + i5000_lpc_config(); + + w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + early_config(); + + setup_gpio(); + + enable_smbus(); + + /* setup PCIe MMCONF base address */ + pci_write_config32(PCI_DEV(0, 16, 0), 0x64, + CONFIG_MMCONF_BASE_ADDRESS >> 16); + + outb(0x07, 0x11b8); + + /* These are smbus write captured with serialice. They + seem to setup the clock generator */ + + smbus_write_byte(0x6f, 0x88, 0x1f); + smbus_write_byte(0x6f, 0x81, 0xff); + smbus_write_byte(0x6f, 0x82, 0xff); + smbus_write_byte(0x6f, 0x80, 0x23); + + outb(0x03, 0x11b8); + outb(0x01, 0x11b8); + for(i = 0; i <0xffffff; i++); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1); + i5000_fbdimm_init(); + smbus_write_byte(0x69, 0x01, 0x01); +}

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coreboot June 2012