coreboot November 2012

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New patch to review for coreboot: 1d90ce9 Persimmon: Disable the unused PCI clocks
by Dave Frodin 16 Nov '12

16 Nov '12

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1875 -gerrit commit 1d90ce9c9b91d1c0405bb8bc2a54aa60e52e6324 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri Nov 16 14:16:02 2012 -0700 Persimmon: Disable the unused PCI clocks Change-Id: I4b735fe4e6441f99236e43b34695fdac95b8888a Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/mainboard/amd/persimmon/platform_cfg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 1065cda..7051e7d 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -90,7 +90,7 @@ * PCI SLOT 3 define at BIT3 * PCI SLOT 4 define at BIT4 */ -#define PCI_CLOCK_CTRL 0x1F +#define PCI_CLOCK_CTRL 0x07 /** * @def SATA_CONTROLLER

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New patch to review for coreboot: 9483060 Unify use of bool config variables
by Stefan Reinauer 16 Nov '12

16 Nov '12

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1874 -gerrit commit 9483060bdbcd381edf7ce16f623cf0a9123b79ec Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Nov 16 13:34:48 2012 -0800 Unify use of bool config variables e.g. -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS This will make it easier to switch over to use the config_enabled() macro later on. Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/lib/c_start.S | 4 ++-- src/cpu/amd/agesa/family15tn/model_15_init.c | 6 +++--- src/devices/pci_device.c | 2 +- src/include/cpu/x86/lapic.h | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 2 +- src/mainboard/amd/parmer/get_bus_conf.c | 4 ++-- src/mainboard/amd/parmer/mainboard.c | 2 +- src/mainboard/amd/parmer/romstage.c | 2 +- src/mainboard/amd/thatcher/agesawrapper.c | 2 +- src/mainboard/amd/thatcher/get_bus_conf.c | 4 ++-- src/mainboard/amd/thatcher/mainboard.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/siemens/sitemp_g1p1/acpi_tables.c | 4 ---- src/mainboard/tyan/s8226/buildOpts.c | 6 +++--- src/mainboard/tyan/s8226/rd890_cfg.h | 4 ++-- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/hudson.c | 2 +- src/southbridge/amd/cs5530/vga.c | 2 +- src/southbridge/amd/rs780/early_setup.c | 14 +++++++------- src/southbridge/amd/sr5650/early_setup.c | 4 ++-- 21 files changed, 36 insertions(+), 40 deletions(-) diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index 9c1fdb1..a84724d 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -82,7 +82,7 @@ _start: /* Restore the stack location */ movl %ebp, %esp -#if CONFIG_GDB_WAIT == 1 +#if CONFIG_GDB_WAIT call gdb_stub_breakpoint #endif /* The boot_complete flag has already been pushed */ @@ -235,7 +235,7 @@ int_hand: iret -#if CONFIG_GDB_WAIT == 1 +#if CONFIG_GDB_WAIT .globl gdb_stub_breakpoint gdb_stub_breakpoint: diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 02580ee..39533bb 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -62,7 +62,7 @@ static void model_15_init(device_t dev) u8 i; msr_t msr; int msrno; -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS u32 siblings; #endif @@ -90,7 +90,7 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type == 3) restore_mtrr(); #endif @@ -109,7 +109,7 @@ static void model_15_init(device_t dev) /* Enable the local cpu apics */ setup_lapic(); -#if CONFIG_LOGICAL_CPUS == 1 +#if CONFIG_LOGICAL_CPUS siblings = cpuid_ecx(0x80000008) & 0xff; if (siblings > 0) { diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c index 94f68ea..e2a4940 100644 --- a/src/devices/pci_device.c +++ b/src/devices/pci_device.c @@ -663,7 +663,7 @@ int oprom_is_loaded = 0; /** Default handler: only runs the relevant PCI BIOS. */ void pci_dev_init(struct device *dev) { -#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1 +#if CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN struct rom_header *rom, *ram; if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */ diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 078f2a7..54b2f54 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -52,7 +52,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void) } #ifndef __ROMCC__ -#if CONFIG_AP_IN_SIPI_WAIT != 1 +#if !CONFIG_AP_IN_SIPI_WAIT /* If we need to go back to sipi wait, we use the long non-inlined version of * this function in lapic_cpu_init.c */ diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index b82c1c1..c180800 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -479,7 +479,7 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume(VOID) { diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index ad5e1d7..2636b9e 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -47,7 +47,7 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif void get_bus_conf(void) @@ -78,7 +78,7 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) { status = agesawrapper_amdinitlate(); if(status) { diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 40ad8c5..a83cd42 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -39,7 +39,7 @@ static void parmer_enable(device_t dev) * The mainboard is the first place that we get control in ramstage. Check * for S3 resume and call the approriate AGESA/CIMx resume functions. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); if (acpi_slp_type == 3) agesawrapper_fchs3earlyrestore(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 56fcb57..335e56d 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -44,7 +44,7 @@ void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif val = agesawrapper_amdinitmmio(); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 509f472..67ac8e9 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -479,7 +479,7 @@ agesawrapper_amdlaterunaptask ( return (UINT32)Status; } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME UINT32 agesawrapper_amdinitresume(VOID) { diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index ad5e1d7..2636b9e 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -47,7 +47,7 @@ u32 sbdn_sb800; static u32 get_bus_conf_done = 0; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME extern u8 acpi_slp_type; #endif void get_bus_conf(void) @@ -78,7 +78,7 @@ void get_bus_conf(void) * of each of the write functions called prior to the ACPI write functions, so this * becomes the best place for this call. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME if (acpi_slp_type != 3) { status = agesawrapper_amdinitlate(); if(status) { diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index 8d4eae2..bc1d591 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -55,7 +55,7 @@ static void thatcher_enable(device_t dev) * The mainboard is the first place that we get control in ramstage. Check * for S3 resume and call the approriate AGESA/CIMx resume functions. */ -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME acpi_slp_type = acpi_get_sleep_type(); if (acpi_slp_type == 3) agesawrapper_fchs3earlyrestore(); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index e0cfd02..445fe45 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -49,7 +49,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 byte; device_t dev; -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif val = agesawrapper_amdinitmmio(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index f0be2f7..1fe7b49 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -246,7 +246,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { -#ifndef CONFIG_BOARD_ASUS_M4A785TM +#if !CONFIG_BOARD_ASUS_M4A785TM static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; /* If the BUID was adjusted in early_ht we need to do the manual override */ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index ea69034..cf17e76 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -36,10 +36,6 @@ #define DUMP_ACPI_TABLES 0 -#ifndef CONFIG_LINT01_CONVERSION -#define CONFIG_LINT01_CONVERSION 1 -#endif - extern u16 pm_base; /* diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index 0f618ec..63c587a 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -202,7 +202,7 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA s8226_manual_swaplist[2] = } }; -#if CONFIG_HT3_SUPPORT == 1 +#if CONFIG_HT3_SUPPORT /** * The socket and link match values are platform specific * @@ -439,10 +439,10 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] = #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* -#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1) +#if CONFIG_CPU_AMD_AGESA_FAMILY15 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE #endif -#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1) +#if CONFIG_CPU_AMD_AGESA_FAMILY10 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE #endif */ diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h index 8f45019..3ba25d5 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.h +++ b/src/mainboard/tyan/s8226/rd890_cfg.h @@ -31,10 +31,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#if CONFIG_CPU_AMD_AGESA_FAMILY10 #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#if CONFIG_CPU_AMD_AGESA_FAMILY15 #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 8cf380b..ed52108 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -79,7 +79,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void) { u16 tmp = inw(PM1_CNT_BLK_ADDRESS); @@ -89,7 +89,7 @@ int acpi_get_sleep_type(void) } #endif -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int acpi_is_wakeup_early(void) { return (acpi_get_sleep_type() == 3); diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index ce45042..ce541fc 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -30,7 +30,7 @@ #include "hudson.h" #include "smbus.h" -#if CONFIG_HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void) { u16 tmp = inw(PM1_CNT_BLK_ADDRESS); diff --git a/src/southbridge/amd/cs5530/vga.c b/src/southbridge/amd/cs5530/vga.c index 56bea45..66ab239 100644 --- a/src/southbridge/amd/cs5530/vga.c +++ b/src/southbridge/amd/cs5530/vga.c @@ -492,4 +492,4 @@ static const struct pci_driver vga_pci_driver __pci_driver = { .device = PCI_DEVICE_ID_CYRIX_5530_VIDEO, }; -#endif /* #if CONFIG_GX1_VIDEO == 1 */ +#endif /* #if CONFIG_GX1_VIDEO */ diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index 0540823..31b3173 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -147,7 +147,7 @@ static u8 is_famly10(void) return (cpuid_eax(1) & 0xff00000) != 0; } -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 static u8 l3_cache(void) { return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0; @@ -246,7 +246,7 @@ static void rs780_htinit(void) } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { printk(BIOS_INFO, "rs780_htinit: HT3 mode\n"); - #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ + #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 /* HT3 mode, RPR 8.4.3 */ set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0); @@ -282,11 +282,11 @@ static void rs780_htinit(void) /* Sets Training 0 Time. See T0Time table for encodings */ set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20); /* TODO: */ - #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ + #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ } } -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 /* save some spaces */ +#if !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 /******************************************************* * Optimize k8 with UMA. * See BKDG_NPT_0F guide for details. @@ -340,9 +340,9 @@ static void k8_optimization(void) } #else #define k8_optimization() do{}while(0) -#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */ +#endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ -#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ +#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 static void fam10_optimization(void) { device_t cpu_f0, cpu_f2, cpu_f3; @@ -405,7 +405,7 @@ static void fam10_optimization(void) } #else #define fam10_optimization() do{}while(0) -#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ +#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ /***************************************** * rs780_por_pcicfg_init() diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 0f54ba3..c613163 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -266,7 +266,7 @@ void sr5650_htinit(void) //set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26); /* HT Buffer Allocation for Ganged Links!!! */ -#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ +#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */ } } @@ -299,7 +299,7 @@ void fam10_optimization(void) } #else #define fam10_optimization() do{}while(0) -#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */ +#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */ /***************************************** * Compliant with CIM_33's ATINB_PCICFG_POR_TABLE

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New patch to review for coreboot: b413c79 Enable the FCH GPP port prior to device enumeration
by Dave Frodin 16 Nov '12

16 Nov '12

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1873 -gerrit commit b413c79d164b316a48472ce16bb1024e2cc0561a Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Nov 13 07:09:12 2012 -0700 Enable the FCH GPP port prior to device enumeration Change-Id: Ib4401897570f9e4d31c18d05144b5deb6f4523bc Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/cimx/sb800/late.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 7286a6d..dacbbe3 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -31,7 +31,7 @@ #include "cfg.h" /* sb800 Cimx configuration */ #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ - +#include "smbus.h" /*implement in mainboard.c*/ void set_pcie_reset(void); @@ -306,6 +306,7 @@ struct device_operations bridge_ops = { .ops_pci = &lops_pci, }; +#if 0 /* use the default PCIe chip driver */ /* 0:15:0 PCIe PortA */ static const struct pci_driver PORTA_driver __pci_driver = { .ops = &bridge_ops, @@ -333,7 +334,7 @@ static const struct pci_driver PORTD_driver __pci_driver = { .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_SB800_PCIED, }; - +#endif /** * South Bridge CIMx ramstage entry point wrapper. @@ -387,6 +388,21 @@ static void sb800_enable(device_t dev) switch (dev->path.pci.devfn) { case (0x11 << 3) | 0: /* 0:11.0 SATA */ /* the first sb800 device */ + switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ + case GPP_CFGMODE_X2200: + abcfg_reg(0xc0, 0x01FF, 0x030); /* x2 Port_0, x2 Port_1 */ + break; + case GPP_CFGMODE_X2110: + abcfg_reg(0xc0, 0x01FF, 0x070); /* x2 Port_0, x1 Port_1&2 */ + break; + case GPP_CFGMODE_X1111: + abcfg_reg(0xc0, 0x01FF, 0x0F0); /* x1 Port_0&1&2&3 */ + break; + case GPP_CFGMODE_X4000: + default: + abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */ + break; + } sb800_cimx_config(sb_config); if (dev->enabled) {

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Patch merged into coreboot/master: 17b77ab buildgcc: Print error if flex is missing
by gerrit＠coreboot.org 16 Nov '12

16 Nov '12

the following patch was just integrated into master: commit 17b77ab6aa4833f6b369a12dd9da87c8104f482c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Nov 15 11:31:38 2012 -0800 buildgcc: Print error if flex is missing flex is needed by acpica. This patch makes the build fail early instead of after gcc has been compiled, if flex is not there. Change-Id: Idfd71bdf704ab25de655f1a72c266c5220b15048 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/1860 Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Nov 16 10:48:53 2012, giving +2 Build-Tested: build bot (Jenkins) at Thu Nov 15 21:04:56 2012, giving +1 See http://review.coreboot.org/1860 for details. -gerrit

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Re: [coreboot] i915tool
by Denis 'GNUtoo' Carikli 16 Nov '12

16 Nov '12

On Thu, 4 Oct 2012 09:27:53 -0700 ron minnich <rminnich(a)gmail.com> wrote: > I'm quite impressed that your tried the tool. the one in coreboot is > way out of date, let me try to get more current version in today. > > Also, due to driver churn, it turns out you have to be really careful > about which kernel version you get ... you'll see with the new code. > > ron > ping? Denis.

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New patch to review for coreboot: f1f76b0 Get rid of drivers class
by Patrick Georgi 16 Nov '12

16 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1872 -gerrit commit f1f76b01dff875b30f1b158720b80a53a416870c Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Nov 16 14:50:32 2012 +0100 Get rid of drivers class The use of ramstage.a required the build system to handle some object files in a special way, which were put in the drivers class. These object files didn't provide any symbols that were used directly (but only via linker magic), and so the linker never considered them for inclusion. With ramstage.a gone, we can drop this special class, too. Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- Makefile.inc | 2 +- src/arch/x86/Makefile.inc | 6 +++--- src/console/Makefile.inc | 12 +++++------ src/cpu/amd/agesa/family10/Makefile.inc | 2 +- src/cpu/amd/agesa/family12/Makefile.inc | 2 +- src/cpu/amd/agesa/family14/Makefile.inc | 2 +- src/cpu/amd/agesa/family15/Makefile.inc | 2 +- src/cpu/amd/agesa/family15tn/Makefile.inc | 2 +- src/cpu/amd/geode_gx1/Makefile.inc | 2 +- src/cpu/amd/geode_gx2/Makefile.inc | 2 +- src/cpu/amd/geode_lx/Makefile.inc | 2 +- src/cpu/amd/model_10xxx/Makefile.inc | 2 +- src/cpu/amd/model_fxx/Makefile.inc | 2 +- src/cpu/intel/ep80579/Makefile.inc | 2 +- src/cpu/intel/model_1067x/Makefile.inc | 2 +- src/cpu/intel/model_106cx/Makefile.inc | 2 +- src/cpu/intel/model_206ax/Makefile.inc | 2 +- src/cpu/intel/model_65x/Makefile.inc | 2 +- src/cpu/intel/model_67x/Makefile.inc | 2 +- src/cpu/intel/model_68x/Makefile.inc | 2 +- src/cpu/intel/model_69x/Makefile.inc | 2 +- src/cpu/intel/model_6bx/Makefile.inc | 2 +- src/cpu/intel/model_6dx/Makefile.inc | 2 +- src/cpu/intel/model_6ex/Makefile.inc | 2 +- src/cpu/intel/model_6fx/Makefile.inc | 2 +- src/cpu/intel/model_6xx/Makefile.inc | 2 +- src/cpu/intel/model_f0x/Makefile.inc | 2 +- src/cpu/intel/model_f1x/Makefile.inc | 2 +- src/cpu/intel/model_f2x/Makefile.inc | 2 +- src/cpu/intel/model_f3x/Makefile.inc | 2 +- src/cpu/intel/model_f4x/Makefile.inc | 2 +- src/cpu/via/c3/Makefile.inc | 2 +- src/cpu/via/c7/Makefile.inc | 2 +- src/cpu/via/nano/Makefile.inc | 2 +- src/drivers/ati/ragexl/Makefile.inc | 2 +- src/drivers/dec/21143/Makefile.inc | 2 +- src/drivers/emulation/qemu/Makefile.inc | 2 +- src/drivers/generic/ioapic/Makefile.inc | 2 +- src/drivers/i2c/adm1026/Makefile.inc | 2 +- src/drivers/i2c/adm1027/Makefile.inc | 2 +- src/drivers/i2c/adt7463/Makefile.inc | 2 +- src/drivers/i2c/i2cmux/Makefile.inc | 2 +- src/drivers/i2c/i2cmux2/Makefile.inc | 2 +- src/drivers/i2c/lm63/Makefile.inc | 2 +- src/drivers/i2c/w83793/Makefile.inc | 2 +- src/drivers/i2c/w83795/Makefile.inc | 2 +- src/drivers/ics/954309/Makefile.inc | 2 +- src/drivers/ipmi/Makefile.inc | 2 +- src/drivers/oxford/oxpcie/Makefile.inc | 2 +- src/drivers/realtek/Makefile.inc | 2 +- src/drivers/sil/3114/Makefile.inc | 2 +- src/drivers/trident/blade3d/Makefile.inc | 2 +- src/ec/lenovo/h8/Makefile.inc | 2 +- src/ec/lenovo/pmh7/Makefile.inc | 2 +- src/ec/smsc/mec1308/Makefile.inc | 2 +- src/lib/Makefile.inc | 2 +- src/mainboard/ibase/mb899/Makefile.inc | 2 +- src/northbridge/amd/agesa/family10/Makefile.inc | 2 +- src/northbridge/amd/agesa/family12/Makefile.inc | 2 +- src/northbridge/amd/agesa/family14/Makefile.inc | 2 +- src/northbridge/amd/agesa/family15/Makefile.inc | 2 +- src/northbridge/amd/agesa/family15tn/Makefile.inc | 2 +- src/northbridge/amd/amdfam10/Makefile.inc | 4 ++-- src/northbridge/amd/amdk8/Makefile.inc | 4 ++-- src/northbridge/amd/gx1/Makefile.inc | 2 +- src/northbridge/amd/gx2/Makefile.inc | 2 +- src/northbridge/amd/lx/Makefile.inc | 2 +- src/northbridge/intel/e7520/Makefile.inc | 10 ++++----- src/northbridge/intel/e7525/Makefile.inc | 10 ++++----- src/northbridge/intel/i3100/Makefile.inc | 6 +++--- src/northbridge/intel/i440bx/Makefile.inc | 2 +- src/northbridge/intel/i440lx/Makefile.inc | 2 +- src/northbridge/intel/i5000/Makefile.inc | 2 +- src/northbridge/intel/i82810/Makefile.inc | 2 +- src/northbridge/intel/i82830/Makefile.inc | 4 ++-- src/northbridge/intel/i945/Makefile.inc | 4 ++-- src/northbridge/intel/sandybridge/Makefile.inc | 4 ++-- src/northbridge/intel/sch/Makefile.inc | 6 +++--- src/northbridge/rdc/r8610/Makefile.inc | 2 +- src/northbridge/via/cn400/Makefile.inc | 8 +++---- src/northbridge/via/cn700/Makefile.inc | 6 +++--- src/northbridge/via/cx700/Makefile.inc | 8 +++---- src/northbridge/via/vt8601/Makefile.inc | 2 +- src/northbridge/via/vt8623/Makefile.inc | 4 ++-- src/northbridge/via/vx800/Makefile.inc | 8 +++---- src/southbridge/amd/agesa/hudson/Makefile.inc | 18 ++++++++-------- src/southbridge/amd/amd8111/Makefile.inc | 20 ++++++++--------- src/southbridge/amd/amd8131/Makefile.inc | 2 +- src/southbridge/amd/amd8132/Makefile.inc | 2 +- src/southbridge/amd/amd8151/Makefile.inc | 2 +- src/southbridge/amd/cimx/sb700/Makefile.inc | 4 ++-- src/southbridge/amd/cimx/sb800/Makefile.inc | 4 ++-- src/southbridge/amd/cimx/sb900/Makefile.inc | 4 ++-- src/southbridge/amd/cs5530/Makefile.inc | 10 ++++----- src/southbridge/amd/cs5535/Makefile.inc | 6 +++--- src/southbridge/amd/cs5536/Makefile.inc | 8 +++---- src/southbridge/amd/rs690/Makefile.inc | 10 ++++----- src/southbridge/amd/rs780/Makefile.inc | 10 ++++----- src/southbridge/amd/sb600/Makefile.inc | 18 ++++++++-------- src/southbridge/amd/sb700/Makefile.inc | 18 ++++++++-------- src/southbridge/amd/sb800/Makefile.inc | 18 ++++++++-------- src/southbridge/amd/sr5650/Makefile.inc | 6 +++--- src/southbridge/broadcom/bcm21000/Makefile.inc | 2 +- src/southbridge/broadcom/bcm5780/Makefile.inc | 6 +++--- src/southbridge/broadcom/bcm5785/Makefile.inc | 12 +++++------ src/southbridge/intel/bd82x6x/Makefile.inc | 20 ++++++++--------- src/southbridge/intel/esb6300/Makefile.inc | 24 ++++++++++----------- src/southbridge/intel/i3100/Makefile.inc | 16 +++++++------- src/southbridge/intel/i82371eb/Makefile.inc | 18 ++++++++-------- src/southbridge/intel/i82801ax/Makefile.inc | 14 ++++++------ src/southbridge/intel/i82801bx/Makefile.inc | 16 +++++++------- src/southbridge/intel/i82801cx/Makefile.inc | 14 ++++++------ src/southbridge/intel/i82801dx/Makefile.inc | 14 ++++++------ src/southbridge/intel/i82801ex/Makefile.inc | 18 ++++++++-------- src/southbridge/intel/i82801gx/Makefile.inc | 24 ++++++++++----------- src/southbridge/intel/i82870/Makefile.inc | 6 +++--- src/southbridge/intel/pxhd/Makefile.inc | 2 +- src/southbridge/intel/sch/Makefile.inc | 20 ++++++++--------- src/southbridge/nvidia/ck804/Makefile.inc | 24 ++++++++++----------- src/southbridge/nvidia/mcp55/Makefile.inc | 26 +++++++++++------------ src/southbridge/rdc/r8610/Makefile.inc | 2 +- src/southbridge/ricoh/rl5c476/Makefile.inc | 2 +- src/southbridge/sis/sis966/Makefile.inc | 20 ++++++++--------- src/southbridge/ti/pci1x2x/Makefile.inc | 2 +- src/southbridge/ti/pci7420/Makefile.inc | 4 ++-- src/southbridge/ti/pcixx12/Makefile.inc | 2 +- src/southbridge/via/k8t890/Makefile.inc | 18 ++++++++-------- src/southbridge/via/vt8231/Makefile.inc | 12 +++++------ src/southbridge/via/vt8235/Makefile.inc | 10 ++++----- src/southbridge/via/vt8237r/Makefile.inc | 14 ++++++------ 130 files changed, 382 insertions(+), 382 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 4e31e83..37cd8a6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -59,7 +59,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage driver smm cpu_microcode +classes-y := ramstage romstage smm cpu_microcode romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fe74959..a7446df 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -161,12 +161,12 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $< endif -$(objgenerated)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(driver-objs) $$(ramstage-objs) $(LIBGCC_FILE_NAME) +$(objgenerated)/coreboot_ram.o: $(obj)/arch/x86/lib/c_start.ramstage.o $$(ramstage-objs) $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(filter-out $(obj)/arch/x86/lib/c_start.ramstage.o,$(ramstage-objs)) $(LIBGCC_FILE_NAME) --end-group + $(LD) -m elf_i386 -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(filter-out $(obj)/arch/x86/lib/c_start.ramstage.o,$(ramstage-objs)) $(LIBGCC_FILE_NAME) --end-group else - $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o $(driver-objs) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(filter-out $(obj)/arch/x86/lib/c_start.ramstage.o,$(ramstage-objs)) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -r -o $@ $(obj)/arch/x86/lib/c_start.ramstage.o -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(filter-out $(obj)/arch/x86/lib/c_start.ramstage.o,$(ramstage-objs)) $(LIBGCC_FILE_NAME) -Wl,--end-group endif ################################################################################ diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index f8928ad..a712486 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -14,12 +14,12 @@ romstage-$(CONFIG_CACHE_AS_RAM) += console.c romstage-y += post.c romstage-y += die.c -driver-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c -driver-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c -driver-$(CONFIG_USBDEBUG) += usbdebug_console.c -driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c -driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c -driver-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c +ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c +ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c +ramstage-$(CONFIG_USBDEBUG) += usbdebug_console.c +ramstage-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c +ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c +ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c $(obj)/console/console.ramstage.o : $(obj)/build.h diff --git a/src/cpu/amd/agesa/family10/Makefile.inc b/src/cpu/amd/agesa/family10/Makefile.inc index 6981a47..068cbfe 100755 --- a/src/cpu/amd/agesa/family10/Makefile.inc +++ b/src/cpu/amd/agesa/family10/Makefile.inc @@ -18,7 +18,7 @@ # ramstage-y += chip_name.c -driver-y += model_10_init.c +ramstage-y += model_10_init.c AGESA_ROOT = ../../../../vendorcode/amd/agesa/f10 diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 4c7b2fd..10d64dd 100755 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -28,7 +28,7 @@ #***************************************************************************** ramstage-y += chip_name.c -driver-y += model_12_init.c +ramstage-y += model_12_init.c AGESA_ROOT = ../../../../vendorcode/amd/agesa/f12 diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index b08ceeb..97959b3 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -18,7 +18,7 @@ # ramstage-y += chip_name.c -driver-y += model_14_init.c +ramstage-y += model_14_init.c AGESA_ROOT = ../../../../vendorcode/amd/agesa/f14 diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc index 936d3c8..2d413ac 100644 --- a/src/cpu/amd/agesa/family15/Makefile.inc +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -26,5 +26,5 @@ subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm ramstage-y += chip_name.c -driver-y += model_15_init.c +ramstage-y += model_15_init.c diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index b4d213e..5474571 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -18,7 +18,7 @@ # ramstage-y += chip_name.c -driver-y += model_15_init.c +ramstage-y += model_15_init.c AGESA_ROOT = ../../../../vendorcode/amd/agesa/f15tn diff --git a/src/cpu/amd/geode_gx1/Makefile.inc b/src/cpu/amd/geode_gx1/Makefile.inc index d5bb1ef..4b3aff1 100644 --- a/src/cpu/amd/geode_gx1/Makefile.inc +++ b/src/cpu/amd/geode_gx1/Makefile.inc @@ -22,7 +22,7 @@ subdirs-y += ../../x86/tsc subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm -driver-y += geode_gx1_init.c +ramstage-y += geode_gx1_init.c cpu_incs += $(src)/cpu/amd/geode_gx1/cpu_setup.inc cpu_incs += $(src)/cpu/amd/geode_gx1/gx_setup.inc diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc index d3777a6..b3f3de9 100644 --- a/src/cpu/amd/geode_gx2/Makefile.inc +++ b/src/cpu/amd/geode_gx2/Makefile.inc @@ -3,7 +3,7 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm -driver-y += geode_gx2_init.c +ramstage-y += geode_gx2_init.c ramstage-y += cpubug.c cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc index 4b2b37c..c9df888 100644 --- a/src/cpu/amd/geode_lx/Makefile.inc +++ b/src/cpu/amd/geode_lx/Makefile.inc @@ -3,7 +3,7 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm -driver-y += geode_lx_init.c +ramstage-y += geode_lx_init.c ramstage-y += cpubug.c cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc diff --git a/src/cpu/amd/model_10xxx/Makefile.inc b/src/cpu/amd/model_10xxx/Makefile.inc index 35f32c2..c9becbd 100644 --- a/src/cpu/amd/model_10xxx/Makefile.inc +++ b/src/cpu/amd/model_10xxx/Makefile.inc @@ -1,4 +1,4 @@ -driver-y += model_10xxx_init.c +ramstage-y += model_10xxx_init.c ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c ramstage-y += apic_timer.c ramstage-y += processor_name.c diff --git a/src/cpu/amd/model_fxx/Makefile.inc b/src/cpu/amd/model_fxx/Makefile.inc index 50b6f61..99c09c8 100644 --- a/src/cpu/amd/model_fxx/Makefile.inc +++ b/src/cpu/amd/model_fxx/Makefile.inc @@ -1,5 +1,5 @@ # no conditionals here. If you include this file from a socket, then you get all the binaries. -driver-y += model_fxx_init.c +ramstage-y += model_fxx_init.c ramstage-y += apic_timer.c ramstage-y += model_fxx_update_microcode.c ramstage-y += processor_name.c diff --git a/src/cpu/intel/ep80579/Makefile.inc b/src/cpu/intel/ep80579/Makefile.inc index 7aaedba..080e2ee 100644 --- a/src/cpu/intel/ep80579/Makefile.inc +++ b/src/cpu/intel/ep80579/Makefile.inc @@ -1,5 +1,5 @@ ramstage-y += ep80579.c -driver-y += ep80579_init.c +ramstage-y += ep80579_init.c subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index b2b7606..c0e98bc 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -1,3 +1,3 @@ -driver-y += model_1067x_init.c +ramstage-y += model_1067x_init.c subdirs-y += ../../x86/name diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 0b506b3..1f217fe 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,4 +1,4 @@ -driver-y += model_106cx_init.c +ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name cpu_incs += $(src)/cpu/intel/car/cache_as_ram_ht.inc diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 6ab4840..a324b64 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -1,4 +1,4 @@ -driver-y += model_206ax_init.c +ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c diff --git a/src/cpu/intel/model_65x/Makefile.inc b/src/cpu/intel/model_65x/Makefile.inc index 52c8fef..b0b6f0f 100644 --- a/src/cpu/intel/model_65x/Makefile.inc +++ b/src/cpu/intel/model_65x/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += model_65x_init.c +ramstage-y += model_65x_init.c diff --git a/src/cpu/intel/model_67x/Makefile.inc b/src/cpu/intel/model_67x/Makefile.inc index 44085d9..d7d7f31 100644 --- a/src/cpu/intel/model_67x/Makefile.inc +++ b/src/cpu/intel/model_67x/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += model_67x_init.c +ramstage-y += model_67x_init.c diff --git a/src/cpu/intel/model_68x/Makefile.inc b/src/cpu/intel/model_68x/Makefile.inc index 5b5f166..64869db 100644 --- a/src/cpu/intel/model_68x/Makefile.inc +++ b/src/cpu/intel/model_68x/Makefile.inc @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += model_68x_init.c +ramstage-y += model_68x_init.c subdirs-y += ../../x86/name diff --git a/src/cpu/intel/model_69x/Makefile.inc b/src/cpu/intel/model_69x/Makefile.inc index 329bfeb..927bfeb 100644 --- a/src/cpu/intel/model_69x/Makefile.inc +++ b/src/cpu/intel/model_69x/Makefile.inc @@ -1 +1 @@ -driver-y += model_69x_init.c +ramstage-y += model_69x_init.c diff --git a/src/cpu/intel/model_6bx/Makefile.inc b/src/cpu/intel/model_6bx/Makefile.inc index 4632815..2d33f85 100644 --- a/src/cpu/intel/model_6bx/Makefile.inc +++ b/src/cpu/intel/model_6bx/Makefile.inc @@ -1,2 +1,2 @@ -driver-y += model_6bx_init.c +ramstage-y += model_6bx_init.c subdirs-y += ../../x86/name diff --git a/src/cpu/intel/model_6dx/Makefile.inc b/src/cpu/intel/model_6dx/Makefile.inc index 47525be..cc88a2c 100644 --- a/src/cpu/intel/model_6dx/Makefile.inc +++ b/src/cpu/intel/model_6dx/Makefile.inc @@ -1 +1 @@ -driver-y += model_6dx_init.c +ramstage-y += model_6dx_init.c diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index cc4dc7b..b515c4f 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,3 +1,3 @@ -driver-y += model_6ex_init.c +ramstage-y += model_6ex_init.c subdirs-y += ../../x86/name diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index 3743547..b75cde3 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -1,2 +1,2 @@ -driver-y += model_6fx_init.c +ramstage-y += model_6fx_init.c subdirs-y += ../../x86/name diff --git a/src/cpu/intel/model_6xx/Makefile.inc b/src/cpu/intel/model_6xx/Makefile.inc index 157ca90..5fdd71c 100644 --- a/src/cpu/intel/model_6xx/Makefile.inc +++ b/src/cpu/intel/model_6xx/Makefile.inc @@ -1 +1 @@ -driver-y += model_6xx_init.c +ramstage-y += model_6xx_init.c diff --git a/src/cpu/intel/model_f0x/Makefile.inc b/src/cpu/intel/model_f0x/Makefile.inc index 55efa14..79ea2a0 100644 --- a/src/cpu/intel/model_f0x/Makefile.inc +++ b/src/cpu/intel/model_f0x/Makefile.inc @@ -1 +1 @@ -driver-y += model_f0x_init.c +ramstage-y += model_f0x_init.c diff --git a/src/cpu/intel/model_f1x/Makefile.inc b/src/cpu/intel/model_f1x/Makefile.inc index e3a02e9..6449ae9 100644 --- a/src/cpu/intel/model_f1x/Makefile.inc +++ b/src/cpu/intel/model_f1x/Makefile.inc @@ -1 +1 @@ -driver-y += model_f1x_init.c +ramstage-y += model_f1x_init.c diff --git a/src/cpu/intel/model_f2x/Makefile.inc b/src/cpu/intel/model_f2x/Makefile.inc index c393343..9b366d6 100644 --- a/src/cpu/intel/model_f2x/Makefile.inc +++ b/src/cpu/intel/model_f2x/Makefile.inc @@ -1 +1 @@ -driver-y += model_f2x_init.c +ramstage-y += model_f2x_init.c diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index b2f2138..cf8f918 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1 +1 @@ -driver-y += model_f3x_init.c +ramstage-y += model_f3x_init.c diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 0a38adf..ac99095 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1 +1 @@ -driver-y += model_f4x_init.c +ramstage-y += model_f4x_init.c diff --git a/src/cpu/via/c3/Makefile.inc b/src/cpu/via/c3/Makefile.inc index e6b889a..d5e02a9 100644 --- a/src/cpu/via/c3/Makefile.inc +++ b/src/cpu/via/c3/Makefile.inc @@ -5,4 +5,4 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../../intel/microcode -driver-y += c3_init.c +ramstage-y += c3_init.c diff --git a/src/cpu/via/c7/Makefile.inc b/src/cpu/via/c7/Makefile.inc index 5300f5d..417d762 100644 --- a/src/cpu/via/c7/Makefile.inc +++ b/src/cpu/via/c7/Makefile.inc @@ -5,6 +5,6 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../../intel/microcode -driver-y += c7_init.c +ramstage-y += c7_init.c cpu_incs += $(src)/cpu/via/car/cache_as_ram.inc diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc index 6b0c1e9..f08b482 100644 --- a/src/cpu/via/nano/Makefile.inc +++ b/src/cpu/via/nano/Makefile.inc @@ -23,7 +23,7 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm -driver-y += nano_init.c +ramstage-y += nano_init.c ramstage-y += update_ucode.c # We need to hear from VIA to get permission to include this file in the diff --git a/src/drivers/ati/ragexl/Makefile.inc b/src/drivers/ati/ragexl/Makefile.inc index 8b59597..fbec414 100644 --- a/src/drivers/ati/ragexl/Makefile.inc +++ b/src/drivers/ati/ragexl/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_ATI_RAGEXL) += xlinit.c +ramstage-$(CONFIG_DRIVERS_ATI_RAGEXL) += xlinit.c diff --git a/src/drivers/dec/21143/Makefile.inc b/src/drivers/dec/21143/Makefile.inc index f1e24f2..f768918 100644 --- a/src/drivers/dec/21143/Makefile.inc +++ b/src/drivers/dec/21143/Makefile.inc @@ -1,2 +1,2 @@ -driver-y += 21143.c +ramstage-y += 21143.c diff --git a/src/drivers/emulation/qemu/Makefile.inc b/src/drivers/emulation/qemu/Makefile.inc index ce7b224..8bd3e57 100644 --- a/src/drivers/emulation/qemu/Makefile.inc +++ b/src/drivers/emulation/qemu/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_EMULATION_QEMU) += init.c +ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU) += init.c diff --git a/src/drivers/generic/ioapic/Makefile.inc b/src/drivers/generic/ioapic/Makefile.inc index 35d0934..d34542b 100644 --- a/src/drivers/generic/ioapic/Makefile.inc +++ b/src/drivers/generic/ioapic/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_GENERIC_IOAPIC) += ioapic.c +ramstage-$(CONFIG_DRIVERS_GENERIC_IOAPIC) += ioapic.c diff --git a/src/drivers/i2c/adm1026/Makefile.inc b/src/drivers/i2c/adm1026/Makefile.inc index 15b07c3..7652a75 100644 --- a/src/drivers/i2c/adm1026/Makefile.inc +++ b/src/drivers/i2c/adm1026/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_I2C_ADM1026) += adm1026.c +ramstage-$(CONFIG_DRIVERS_I2C_ADM1026) += adm1026.c diff --git a/src/drivers/i2c/adm1027/Makefile.inc b/src/drivers/i2c/adm1027/Makefile.inc index 942fbd2..2eb1038 100644 --- a/src/drivers/i2c/adm1027/Makefile.inc +++ b/src/drivers/i2c/adm1027/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_I2C_ADM1027) += adm1027.c +ramstage-$(CONFIG_DRIVERS_I2C_ADM1027) += adm1027.c diff --git a/src/drivers/i2c/adt7463/Makefile.inc b/src/drivers/i2c/adt7463/Makefile.inc index 4a6dc0d..d75981b 100644 --- a/src/drivers/i2c/adt7463/Makefile.inc +++ b/src/drivers/i2c/adt7463/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_I2C_ADT7463) += adt7463.c +ramstage-$(CONFIG_DRIVERS_I2C_ADT7463) += adt7463.c diff --git a/src/drivers/i2c/i2cmux/Makefile.inc b/src/drivers/i2c/i2cmux/Makefile.inc index 0645b15..64bbdce 100644 --- a/src/drivers/i2c/i2cmux/Makefile.inc +++ b/src/drivers/i2c/i2cmux/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_I2C_I2CMUX) += i2cmux.c +ramstage-$(CONFIG_DRIVERS_I2C_I2CMUX) += i2cmux.c diff --git a/src/drivers/i2c/i2cmux2/Makefile.inc b/src/drivers/i2c/i2cmux2/Makefile.inc index df6b2d3..34e3613 100644 --- a/src/drivers/i2c/i2cmux2/Makefile.inc +++ b/src/drivers/i2c/i2cmux2/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_I2C_I2CMUX2) += i2cmux2.c +ramstage-$(CONFIG_DRIVERS_I2C_I2CMUX2) += i2cmux2.c diff --git a/src/drivers/i2c/lm63/Makefile.inc b/src/drivers/i2c/lm63/Makefile.inc index 782d63d..bd1c7ef 100644 --- a/src/drivers/i2c/lm63/Makefile.inc +++ b/src/drivers/i2c/lm63/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_I2C_LM63) += lm63.c +ramstage-$(CONFIG_DRIVERS_I2C_LM63) += lm63.c diff --git a/src/drivers/i2c/w83793/Makefile.inc b/src/drivers/i2c/w83793/Makefile.inc index c25ddd5..f7843a5 100644 --- a/src/drivers/i2c/w83793/Makefile.inc +++ b/src/drivers/i2c/w83793/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_I2C_W83793) += w83793.c +ramstage-$(CONFIG_DRIVERS_I2C_W83793) += w83793.c diff --git a/src/drivers/i2c/w83795/Makefile.inc b/src/drivers/i2c/w83795/Makefile.inc index 708a170..330f6a7 100644 --- a/src/drivers/i2c/w83795/Makefile.inc +++ b/src/drivers/i2c/w83795/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_I2C_W83795) += w83795.c +ramstage-$(CONFIG_DRIVERS_I2C_W83795) += w83795.c diff --git a/src/drivers/ics/954309/Makefile.inc b/src/drivers/ics/954309/Makefile.inc index ede9639..1c66a8c 100644 --- a/src/drivers/ics/954309/Makefile.inc +++ b/src/drivers/ics/954309/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_ICS_954309) += ics954309.c +ramstage-$(CONFIG_DRIVERS_ICS_954309) += ics954309.c diff --git a/src/drivers/ipmi/Makefile.inc b/src/drivers/ipmi/Makefile.inc index ecee28f..e9e7ff3 100644 --- a/src/drivers/ipmi/Makefile.inc +++ b/src/drivers/ipmi/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_IPMI_KCS) += ipmi_kcs.c +ramstage-$(CONFIG_IPMI_KCS) += ipmi_kcs.c diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 7f4aa58..6cc29c4 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -1,4 +1,4 @@ -driver-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c +ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c diff --git a/src/drivers/realtek/Makefile.inc b/src/drivers/realtek/Makefile.inc index 910d4b4..c583b9e 100644 --- a/src/drivers/realtek/Makefile.inc +++ b/src/drivers/realtek/Makefile.inc @@ -17,4 +17,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-$(CONFIG_RTL8168_ROM_DISABLE) += rtl8168.c +ramstage-$(CONFIG_RTL8168_ROM_DISABLE) += rtl8168.c diff --git a/src/drivers/sil/3114/Makefile.inc b/src/drivers/sil/3114/Makefile.inc index 77c348f..a3f3ffb 100644 --- a/src/drivers/sil/3114/Makefile.inc +++ b/src/drivers/sil/3114/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_SIL_3114) += sil_sata.c +ramstage-$(CONFIG_DRIVERS_SIL_3114) += sil_sata.c diff --git a/src/drivers/trident/blade3d/Makefile.inc b/src/drivers/trident/blade3d/Makefile.inc index 390ae13..c4a8c8c 100644 --- a/src/drivers/trident/blade3d/Makefile.inc +++ b/src/drivers/trident/blade3d/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_DRIVERS_TRIDENT_BLADE3D) += blade3d.c +ramstage-$(CONFIG_DRIVERS_TRIDENT_BLADE3D) += blade3d.c diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index 86bc663..9fef94c 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -1 +1 @@ -driver-y += h8.c +ramstage-y += h8.c diff --git a/src/ec/lenovo/pmh7/Makefile.inc b/src/ec/lenovo/pmh7/Makefile.inc index e441980..f42e0e4 100644 --- a/src/ec/lenovo/pmh7/Makefile.inc +++ b/src/ec/lenovo/pmh7/Makefile.inc @@ -1,3 +1,3 @@ -driver-y += pmh7.c +ramstage-y += pmh7.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmh7.c romstage-y += pmh7.c diff --git a/src/ec/smsc/mec1308/Makefile.inc b/src/ec/smsc/mec1308/Makefile.inc index 95c6c03..0accda3 100644 --- a/src/ec/smsc/mec1308/Makefile.inc +++ b/src/ec/smsc/mec1308/Makefile.inc @@ -1,2 +1,2 @@ -driver-y += ec.c +ramstage-y += ec.c smm-y += ec.c diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ec57bc2..5becc42 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -52,7 +52,7 @@ ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c +ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) smm-y += memset.c diff --git a/src/mainboard/ibase/mb899/Makefile.inc b/src/mainboard/ibase/mb899/Makefile.inc index c2c861d..4fb55f5 100644 --- a/src/mainboard/ibase/mb899/Makefile.inc +++ b/src/mainboard/ibase/mb899/Makefile.inc @@ -17,4 +17,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += mv88e8053.c +ramstage-y += mv88e8053.c diff --git a/src/northbridge/amd/agesa/family10/Makefile.inc b/src/northbridge/amd/agesa/family10/Makefile.inc index 8f0fe0d..ea1a146 100755 --- a/src/northbridge/amd/agesa/family10/Makefile.inc +++ b/src/northbridge/amd/agesa/family10/Makefile.inc @@ -17,6 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -driver-y += northbridge.c +ramstage-y += northbridge.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl diff --git a/src/northbridge/amd/agesa/family12/Makefile.inc b/src/northbridge/amd/agesa/family12/Makefile.inc index 8f0fe0d..ea1a146 100755 --- a/src/northbridge/amd/agesa/family12/Makefile.inc +++ b/src/northbridge/amd/agesa/family12/Makefile.inc @@ -17,6 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -driver-y += northbridge.c +ramstage-y += northbridge.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc index d3a125c..8cdd0a0 100644 --- a/src/northbridge/amd/agesa/family14/Makefile.inc +++ b/src/northbridge/amd/agesa/family14/Makefile.inc @@ -17,4 +17,4 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -driver-y += northbridge.c +ramstage-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc index 255fe10..121bf22 100644 --- a/src/northbridge/amd/agesa/family15/Makefile.inc +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -17,4 +17,4 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -driver-y += northbridge.c +ramstage-y += northbridge.c diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index 255fe10..121bf22 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -17,4 +17,4 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -driver-y += northbridge.c +ramstage-y += northbridge.c diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc index 2ab9c0f..a24783b 100644 --- a/src/northbridge/amd/amdfam10/Makefile.inc +++ b/src/northbridge/amd/amdfam10/Makefile.inc @@ -1,5 +1,5 @@ -driver-y += northbridge.c -driver-y += misc_control.c +ramstage-y += northbridge.c +ramstage-y += misc_control.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc index e35b9ed..38b0201 100644 --- a/src/northbridge/amd/amdk8/Makefile.inc +++ b/src/northbridge/amd/amdk8/Makefile.inc @@ -1,5 +1,5 @@ -driver-y += northbridge.c -driver-y += misc_control.c +ramstage-y += northbridge.c +ramstage-y += misc_control.c ramstage-y += get_sblk_pci1234.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c diff --git a/src/northbridge/amd/gx1/Makefile.inc b/src/northbridge/amd/gx1/Makefile.inc index 16d702a..ab619fc 100644 --- a/src/northbridge/amd/gx1/Makefile.inc +++ b/src/northbridge/amd/gx1/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.c +ramstage-y += northbridge.c diff --git a/src/northbridge/amd/gx2/Makefile.inc b/src/northbridge/amd/gx2/Makefile.inc index 482aff9..ad904c4 100644 --- a/src/northbridge/amd/gx2/Makefile.inc +++ b/src/northbridge/amd/gx2/Makefile.inc @@ -1,3 +1,3 @@ -driver-y += northbridge.c +ramstage-y += northbridge.c ramstage-y += northbridgeinit.c ramstage-y += grphinit.c diff --git a/src/northbridge/amd/lx/Makefile.inc b/src/northbridge/amd/lx/Makefile.inc index 482aff9..ad904c4 100644 --- a/src/northbridge/amd/lx/Makefile.inc +++ b/src/northbridge/amd/lx/Makefile.inc @@ -1,3 +1,3 @@ -driver-y += northbridge.c +ramstage-y += northbridge.c ramstage-y += northbridgeinit.c ramstage-y += grphinit.c diff --git a/src/northbridge/intel/e7520/Makefile.inc b/src/northbridge/intel/e7520/Makefile.inc index 32c6836..370477b 100644 --- a/src/northbridge/intel/e7520/Makefile.inc +++ b/src/northbridge/intel/e7520/Makefile.inc @@ -1,5 +1,5 @@ -driver-y += northbridge.c -driver-y += pciexp_porta.c -driver-y += pciexp_porta1.c -driver-y += pciexp_portb.c -driver-y += pciexp_portc.c +ramstage-y += northbridge.c +ramstage-y += pciexp_porta.c +ramstage-y += pciexp_porta1.c +ramstage-y += pciexp_portb.c +ramstage-y += pciexp_portc.c diff --git a/src/northbridge/intel/e7525/Makefile.inc b/src/northbridge/intel/e7525/Makefile.inc index 32c6836..370477b 100644 --- a/src/northbridge/intel/e7525/Makefile.inc +++ b/src/northbridge/intel/e7525/Makefile.inc @@ -1,5 +1,5 @@ -driver-y += northbridge.c -driver-y += pciexp_porta.c -driver-y += pciexp_porta1.c -driver-y += pciexp_portb.c -driver-y += pciexp_portc.c +ramstage-y += northbridge.c +ramstage-y += pciexp_porta.c +ramstage-y += pciexp_porta1.c +ramstage-y += pciexp_portb.c +ramstage-y += pciexp_portc.c diff --git a/src/northbridge/intel/i3100/Makefile.inc b/src/northbridge/intel/i3100/Makefile.inc index c2de0fc..3ad40f5 100644 --- a/src/northbridge/intel/i3100/Makefile.inc +++ b/src/northbridge/intel/i3100/Makefile.inc @@ -1,3 +1,3 @@ -driver-y += northbridge.c -driver-y += pciexp_porta.c -driver-y += pciexp_porta_ep80579.c +ramstage-y += northbridge.c +ramstage-y += pciexp_porta.c +ramstage-y += pciexp_porta_ep80579.c diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index 0c0a3c8..ef4be2e 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -18,7 +18,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.c +ramstage-y += northbridge.c romstage-y += raminit.c romstage-y += debug.c diff --git a/src/northbridge/intel/i440lx/Makefile.inc b/src/northbridge/intel/i440lx/Makefile.inc index 16d702a..ab619fc 100644 --- a/src/northbridge/intel/i440lx/Makefile.inc +++ b/src/northbridge/intel/i440lx/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.c +ramstage-y += northbridge.c diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index 5e75159..e3ab0bb 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -17,6 +17,6 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -driver-y += northbridge.c +ramstage-y += northbridge.c romstage-y += raminit.c udelay.c cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S diff --git a/src/northbridge/intel/i82810/Makefile.inc b/src/northbridge/intel/i82810/Makefile.inc index 0c0a3c8..ef4be2e 100644 --- a/src/northbridge/intel/i82810/Makefile.inc +++ b/src/northbridge/intel/i82810/Makefile.inc @@ -18,7 +18,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.c +ramstage-y += northbridge.c romstage-y += raminit.c romstage-y += debug.c diff --git a/src/northbridge/intel/i82830/Makefile.inc b/src/northbridge/intel/i82830/Makefile.inc index c8cf0f4..2394570 100644 --- a/src/northbridge/intel/i82830/Makefile.inc +++ b/src/northbridge/intel/i82830/Makefile.inc @@ -1,4 +1,4 @@ -driver-y += northbridge.c -driver-y += vga.c +ramstage-y += northbridge.c +ramstage-y += vga.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 7d7cb5d..89b0308 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -17,8 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -driver-y += northbridge.c -driver-y += gma.c +ramstage-y += northbridge.c +ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c romstage-y += udelay.c diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 6193abe..bef3da5 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -17,8 +17,8 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -driver-y += northbridge.c -driver-y += gma.c +ramstage-y += northbridge.c +ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c diff --git a/src/northbridge/intel/sch/Makefile.inc b/src/northbridge/intel/sch/Makefile.inc index ecd2a27..2e26450 100644 --- a/src/northbridge/intel/sch/Makefile.inc +++ b/src/northbridge/intel/sch/Makefile.inc @@ -17,7 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -driver-y += northbridge.c -driver-y += gma.c -driver-y += port_access.c +ramstage-y += northbridge.c +ramstage-y += gma.c +ramstage-y += port_access.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c diff --git a/src/northbridge/rdc/r8610/Makefile.inc b/src/northbridge/rdc/r8610/Makefile.inc index c976967..2bc7c57 100644 --- a/src/northbridge/rdc/r8610/Makefile.inc +++ b/src/northbridge/rdc/r8610/Makefile.inc @@ -18,4 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.c +ramstage-y += northbridge.c diff --git a/src/northbridge/via/cn400/Makefile.inc b/src/northbridge/via/cn400/Makefile.inc index 64eab38..d5d06cf 100644 --- a/src/northbridge/via/cn400/Makefile.inc +++ b/src/northbridge/via/cn400/Makefile.inc @@ -18,8 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.c -driver-y += agp.c -driver-y += vga.c -driver-y += vlink.c +ramstage-y += northbridge.c +ramstage-y += agp.c +ramstage-y += vga.c +ramstage-y += vlink.c diff --git a/src/northbridge/via/cn700/Makefile.inc b/src/northbridge/via/cn700/Makefile.inc index 1654111..3ccdd5e 100644 --- a/src/northbridge/via/cn700/Makefile.inc +++ b/src/northbridge/via/cn700/Makefile.inc @@ -18,7 +18,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.c -driver-y += agp.c -driver-y += vga.c +ramstage-y += northbridge.c +ramstage-y += agp.c +ramstage-y += vga.c diff --git a/src/northbridge/via/cx700/Makefile.inc b/src/northbridge/via/cx700/Makefile.inc index b833013..a4172bb 100644 --- a/src/northbridge/via/cx700/Makefile.inc +++ b/src/northbridge/via/cx700/Makefile.inc @@ -20,7 +20,7 @@ ramstage-y += reset.c ramstage-y += northbridge.c -driver-y += agp.c -driver-y += lpc.c -driver-y += sata.c -driver-y += vga.c +ramstage-y += agp.c +ramstage-y += lpc.c +ramstage-y += sata.c +ramstage-y += vga.c diff --git a/src/northbridge/via/vt8601/Makefile.inc b/src/northbridge/via/vt8601/Makefile.inc index 126fe91..4a14320 100644 --- a/src/northbridge/via/vt8601/Makefile.inc +++ b/src/northbridge/via/vt8601/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.c +ramstage-y += northbridge.c diff --git a/src/northbridge/via/vt8623/Makefile.inc b/src/northbridge/via/vt8623/Makefile.inc index 7f6f77d..084e4e0 100644 --- a/src/northbridge/via/vt8623/Makefile.inc +++ b/src/northbridge/via/vt8623/Makefile.inc @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.c -driver-y += vga.c +ramstage-y += northbridge.c +ramstage-y += vga.c diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc index 670a3e9..188db46 100644 --- a/src/northbridge/via/vx800/Makefile.inc +++ b/src/northbridge/via/vx800/Makefile.inc @@ -18,10 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += northbridge.c -driver-y += vga.c -driver-y += lpc.c -driver-y += ide.c +ramstage-y += northbridge.c +ramstage-y += vga.c +ramstage-y += lpc.c +ramstage-y += ide.c chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc chipset_bootblock_lds += $(src)/northbridge/via/vx800/romstrap.lds diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 4bd1523..9d61b59 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -1,12 +1,12 @@ -driver-y += hudson.c -driver-y += usb.c -driver-y += lpc.c -driver-y += sm.c -driver-y += ide.c -driver-y += sata.c -driver-y += hda.c -driver-y += pci.c -driver-y += pcie.c +ramstage-y += hudson.c +ramstage-y += usb.c +ramstage-y += lpc.c +ramstage-y += sm.c +ramstage-y += ide.c +ramstage-y += sata.c +ramstage-y += hda.c +ramstage-y += pci.c +ramstage-y += pcie.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-y += enable_usbdebug.c diff --git a/src/southbridge/amd/amd8111/Makefile.inc b/src/southbridge/amd/amd8111/Makefile.inc index cdad4a6..c5b2688 100644 --- a/src/southbridge/amd/amd8111/Makefile.inc +++ b/src/southbridge/amd/amd8111/Makefile.inc @@ -1,11 +1,11 @@ -driver-y += amd8111.c -driver-y += usb.c -driver-y += lpc.c -driver-y += ide.c -driver-y += acpi.c -driver-y += usb2.c -driver-y += ac97.c -driver-y += nic.c -driver-y += pci.c -driver-y += smbus.c +ramstage-y += amd8111.c +ramstage-y += usb.c +ramstage-y += lpc.c +ramstage-y += ide.c +ramstage-y += acpi.c +ramstage-y += usb2.c +ramstage-y += ac97.c +ramstage-y += nic.c +ramstage-y += pci.c +ramstage-y += smbus.c ramstage-y += reset.c diff --git a/src/southbridge/amd/amd8131/Makefile.inc b/src/southbridge/amd/amd8131/Makefile.inc index d5b3a5f..ce96c97 100644 --- a/src/southbridge/amd/amd8131/Makefile.inc +++ b/src/southbridge/amd/amd8131/Makefile.inc @@ -1 +1 @@ -driver-y += bridge.c +ramstage-y += bridge.c diff --git a/src/southbridge/amd/amd8132/Makefile.inc b/src/southbridge/amd/amd8132/Makefile.inc index d5b3a5f..ce96c97 100644 --- a/src/southbridge/amd/amd8132/Makefile.inc +++ b/src/southbridge/amd/amd8132/Makefile.inc @@ -1 +1 @@ -driver-y += bridge.c +ramstage-y += bridge.c diff --git a/src/southbridge/amd/amd8151/Makefile.inc b/src/southbridge/amd/amd8151/Makefile.inc index b251391..dcb3c73 100644 --- a/src/southbridge/amd/amd8151/Makefile.inc +++ b/src/southbridge/amd/amd8151/Makefile.inc @@ -1 +1 @@ -driver-y += agp3.c +ramstage-y += agp3.c diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc index 7929cf7..465fa9e 100644 --- a/src/southbridge/amd/cimx/sb700/Makefile.inc +++ b/src/southbridge/amd/cimx/sb700/Makefile.inc @@ -25,7 +25,7 @@ romstage-y += smbus.c ramstage-y += late.c -driver-y += smbus.c -driver-y += lpc.c +ramstage-y += smbus.c +ramstage-y += lpc.c diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index f02f0f7..bea9763 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -30,8 +30,8 @@ ramstage-y += late.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c -driver-y += smbus.c -driver-y += lpc.c +ramstage-y += smbus.c +ramstage-y += lpc.c ifeq ($(CONFIG_SB800_SATA_AHCI), y) ifdef CONFIG_SB800_AHCI_ROM diff --git a/src/southbridge/amd/cimx/sb900/Makefile.inc b/src/southbridge/amd/cimx/sb900/Makefile.inc index 49eb604..737c354 100755 --- a/src/southbridge/amd/cimx/sb900/Makefile.inc +++ b/src/southbridge/amd/cimx/sb900/Makefile.inc @@ -28,7 +28,7 @@ ramstage-y += cfg.c ramstage-y += early.c ramstage-y += late.c -driver-y += smbus.c -driver-y += lpc.c +ramstage-y += smbus.c +ramstage-y += lpc.c diff --git a/src/southbridge/amd/cs5530/Makefile.inc b/src/southbridge/amd/cs5530/Makefile.inc index 4bde476..9013611 100644 --- a/src/southbridge/amd/cs5530/Makefile.inc +++ b/src/southbridge/amd/cs5530/Makefile.inc @@ -18,8 +18,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += cs5530.c -driver-y += isa.c -driver-y += ide.c -driver-y += vga.c -driver-y += pirq.c +ramstage-y += cs5530.c +ramstage-y += isa.c +ramstage-y += ide.c +ramstage-y += vga.c +ramstage-y += pirq.c diff --git a/src/southbridge/amd/cs5535/Makefile.inc b/src/southbridge/amd/cs5535/Makefile.inc index 5fecea8..6f65e2e 100644 --- a/src/southbridge/amd/cs5535/Makefile.inc +++ b/src/southbridge/amd/cs5535/Makefile.inc @@ -1,4 +1,4 @@ -driver-y += cs5535.c -#driver-y += pci.c -#driver-y += ide.c +ramstage-y += cs5535.c +#ramstage-y += pci.c +#ramstage-y += ide.c ramstage-y += chipsetinit.c diff --git a/src/southbridge/amd/cs5536/Makefile.inc b/src/southbridge/amd/cs5536/Makefile.inc index 3d2613b..fb8e547 100644 --- a/src/southbridge/amd/cs5536/Makefile.inc +++ b/src/southbridge/amd/cs5536/Makefile.inc @@ -17,8 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += cs5536.c -driver-y += ide.c -driver-y += pirq.c -driver-y += smbus.c +ramstage-y += cs5536.c +ramstage-y += ide.c +ramstage-y += pirq.c +ramstage-y += smbus.c romstage-y += smbus.c \ No newline at end of file diff --git a/src/southbridge/amd/rs690/Makefile.inc b/src/southbridge/amd/rs690/Makefile.inc index 5849340..e0cf927 100644 --- a/src/southbridge/amd/rs690/Makefile.inc +++ b/src/southbridge/amd/rs690/Makefile.inc @@ -1,5 +1,5 @@ -driver-y += rs690.c -driver-y += cmn.c -driver-y += pcie.c -driver-y += ht.c -driver-y += gfx.c +ramstage-y += rs690.c +ramstage-y += cmn.c +ramstage-y += pcie.c +ramstage-y += ht.c +ramstage-y += gfx.c diff --git a/src/southbridge/amd/rs780/Makefile.inc b/src/southbridge/amd/rs780/Makefile.inc index db42570..bf51d83 100644 --- a/src/southbridge/amd/rs780/Makefile.inc +++ b/src/southbridge/amd/rs780/Makefile.inc @@ -1,5 +1,5 @@ -driver-y += rs780.c -driver-y += cmn.c -driver-y += pcie.c -driver-y += ht.c -driver-y += gfx.c +ramstage-y += rs780.c +ramstage-y += cmn.c +ramstage-y += pcie.c +ramstage-y += ht.c +ramstage-y += gfx.c diff --git a/src/southbridge/amd/sb600/Makefile.inc b/src/southbridge/amd/sb600/Makefile.inc index d7451d2..57ef4de 100644 --- a/src/southbridge/amd/sb600/Makefile.inc +++ b/src/southbridge/amd/sb600/Makefile.inc @@ -1,12 +1,12 @@ -driver-y += sb600.c -driver-y += usb.c -driver-y += lpc.c -driver-y += sm.c -driver-y += ide.c -driver-y += sata.c -driver-y += hda.c -driver-y += ac97.c -driver-y += pci.c +ramstage-y += sb600.c +ramstage-y += usb.c +ramstage-y += lpc.c +ramstage-y += sm.c +ramstage-y += ide.c +ramstage-y += sata.c +ramstage-y += hda.c +ramstage-y += ac97.c +ramstage-y += pci.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c diff --git a/src/southbridge/amd/sb700/Makefile.inc b/src/southbridge/amd/sb700/Makefile.inc index 49caedf..6f699f0 100644 --- a/src/southbridge/amd/sb700/Makefile.inc +++ b/src/southbridge/amd/sb700/Makefile.inc @@ -1,12 +1,12 @@ -driver-y += sb700.c -driver-y += usb.c -driver-y += lpc.c -driver-y += smbus.c -driver-y += sm.c -driver-y += ide.c -driver-y += sata.c -driver-y += hda.c -driver-y += pci.c +ramstage-y += sb700.c +ramstage-y += usb.c +ramstage-y += lpc.c +ramstage-y += smbus.c +ramstage-y += sm.c +ramstage-y += ide.c +ramstage-y += sata.c +ramstage-y += hda.c +ramstage-y += pci.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c romstage-y += reset.c ramstage-y += reset.c diff --git a/src/southbridge/amd/sb800/Makefile.inc b/src/southbridge/amd/sb800/Makefile.inc index 38b7d50..3e7bf11 100644 --- a/src/southbridge/amd/sb800/Makefile.inc +++ b/src/southbridge/amd/sb800/Makefile.inc @@ -1,12 +1,12 @@ -driver-y += sb800.c -driver-y += usb.c -driver-y += lpc.c -driver-y += sm.c -driver-y += ide.c -driver-y += sata.c -driver-y += hda.c -driver-y += pci.c -driver-y += pcie.c +ramstage-y += sb800.c +ramstage-y += usb.c +ramstage-y += lpc.c +ramstage-y += sm.c +ramstage-y += ide.c +ramstage-y += sata.c +ramstage-y += hda.c +ramstage-y += pci.c +ramstage-y += pcie.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c diff --git a/src/southbridge/amd/sr5650/Makefile.inc b/src/southbridge/amd/sr5650/Makefile.inc index 0a4ce39..3c17be0 100644 --- a/src/southbridge/amd/sr5650/Makefile.inc +++ b/src/southbridge/amd/sr5650/Makefile.inc @@ -1,5 +1,5 @@ -driver-y += sr5650.c -driver-y += pcie.c -driver-y += ht.c +ramstage-y += sr5650.c +ramstage-y += pcie.c +ramstage-y += ht.c romstage-y += early_setup.c diff --git a/src/southbridge/broadcom/bcm21000/Makefile.inc b/src/southbridge/broadcom/bcm21000/Makefile.inc index 8e5ba74..f85aeb1 100644 --- a/src/southbridge/broadcom/bcm21000/Makefile.inc +++ b/src/southbridge/broadcom/bcm21000/Makefile.inc @@ -1 +1 @@ -driver-y += pcie.c +ramstage-y += pcie.c diff --git a/src/southbridge/broadcom/bcm5780/Makefile.inc b/src/southbridge/broadcom/bcm5780/Makefile.inc index b8a1b96..4eb834a 100644 --- a/src/southbridge/broadcom/bcm5780/Makefile.inc +++ b/src/southbridge/broadcom/bcm5780/Makefile.inc @@ -1,3 +1,3 @@ -driver-y += nic.c -driver-y += pcix.c -driver-y += pcie.c +ramstage-y += nic.c +ramstage-y += pcix.c +ramstage-y += pcie.c diff --git a/src/southbridge/broadcom/bcm5785/Makefile.inc b/src/southbridge/broadcom/bcm5785/Makefile.inc index 9ad67cc..b8427c4 100644 --- a/src/southbridge/broadcom/bcm5785/Makefile.inc +++ b/src/southbridge/broadcom/bcm5785/Makefile.inc @@ -1,7 +1,7 @@ -driver-y += bcm5785.c -driver-y += usb.c -driver-y += lpc.c -driver-y += sb_pci_main.c -driver-y += ide.c -driver-y += sata.c +ramstage-y += bcm5785.c +ramstage-y += usb.c +ramstage-y += lpc.c +ramstage-y += sb_pci_main.c +ramstage-y += ide.c +ramstage-y += sata.c ramstage-y += reset.c diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 7fd6ca8..bc067ca 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -22,16 +22,16 @@ # image outside of CBFS INTERMEDIATE+=bd82x6x_add_me -driver-y += pch.c -driver-y += azalia.c -driver-y += lpc.c -driver-y += pci.c -driver-y += pcie.c -driver-y += sata.c -driver-y += usb_ehci.c -driver-y += me.c -driver-y += me_8.x.c -driver-y += smbus.c +ramstage-y += pch.c +ramstage-y += azalia.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c +ramstage-y += usb_ehci.c +ramstage-y += me.c +ramstage-y += me_8.x.c +ramstage-y += smbus.c ramstage-y += me_status.c ramstage-y += reset.c diff --git a/src/southbridge/intel/esb6300/Makefile.inc b/src/southbridge/intel/esb6300/Makefile.inc index 004ff13..bb70fdc 100644 --- a/src/southbridge/intel/esb6300/Makefile.inc +++ b/src/southbridge/intel/esb6300/Makefile.inc @@ -1,12 +1,12 @@ -driver-y += esb6300.c -driver-y += reset.c -driver-y += uhci.c -driver-y += lpc.c -driver-y += ide.c -driver-y += sata.c -driver-y += ehci.c -driver-y += smbus.c -driver-y += pci.c -driver-y += pic.c -driver-y += bridge1c.c -driver-y += ac97.c +ramstage-y += esb6300.c +ramstage-y += reset.c +ramstage-y += uhci.c +ramstage-y += lpc.c +ramstage-y += ide.c +ramstage-y += sata.c +ramstage-y += ehci.c +ramstage-y += smbus.c +ramstage-y += pci.c +ramstage-y += pic.c +ramstage-y += bridge1c.c +ramstage-y += ac97.c diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc index ddcb0f9..dc3d039 100644 --- a/src/southbridge/intel/i3100/Makefile.inc +++ b/src/southbridge/intel/i3100/Makefile.inc @@ -1,10 +1,10 @@ -driver-y += i3100.c -driver-y += uhci.c -driver-y += lpc.c -driver-y += sata.c -driver-y += ehci.c -driver-y += smbus.c -driver-y += pci.c -driver-y += ioapic.c +ramstage-y += i3100.c +ramstage-y += uhci.c +ramstage-y += lpc.c +ramstage-y += sata.c +ramstage-y += ehci.c +ramstage-y += smbus.c +ramstage-y += pci.c +ramstage-y += ioapic.c ramstage-y += reset.c ramstage-y += pciexp_portb.c diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc index 9e2c3eb..af4c705 100644 --- a/src/southbridge/intel/i82371eb/Makefile.inc +++ b/src/southbridge/intel/i82371eb/Makefile.inc @@ -18,15 +18,15 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += i82371eb.c -driver-y += isa.c -driver-y += ide.c -driver-y += usb.c -driver-y += smbus.c -driver-y += reset.c -driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c -driver-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c -driver-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c +ramstage-y += i82371eb.c +ramstage-y += isa.c +ramstage-y += ide.c +ramstage-y += usb.c +ramstage-y += smbus.c +ramstage-y += reset.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi_tables.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c romstage-y += early_pm.c romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801ax/Makefile.inc b/src/southbridge/intel/i82801ax/Makefile.inc index de0c722..6396650 100644 --- a/src/southbridge/intel/i82801ax/Makefile.inc +++ b/src/southbridge/intel/i82801ax/Makefile.inc @@ -18,13 +18,13 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += i82801ax.c -driver-y += ac97.c -driver-y += ide.c -driver-y += lpc.c -driver-y += pci.c -driver-y += smbus.c -driver-y += usb.c +ramstage-y += i82801ax.c +ramstage-y += ac97.c +ramstage-y += ide.c +ramstage-y += lpc.c +ramstage-y += pci.c +ramstage-y += smbus.c +ramstage-y += usb.c ramstage-y += reset.c ramstage-y += watchdog.c diff --git a/src/southbridge/intel/i82801bx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc index b3587f2..2b368bb 100644 --- a/src/southbridge/intel/i82801bx/Makefile.inc +++ b/src/southbridge/intel/i82801bx/Makefile.inc @@ -18,14 +18,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += i82801bx.c -driver-y += ac97.c -driver-y += ide.c -driver-y += lpc.c -driver-y += nic.c -driver-y += pci.c -driver-y += smbus.c -driver-y += usb.c +ramstage-y += i82801bx.c +ramstage-y += ac97.c +ramstage-y += ide.c +ramstage-y += lpc.c +ramstage-y += nic.c +ramstage-y += pci.c +ramstage-y += smbus.c +ramstage-y += usb.c ramstage-y += reset.c ramstage-y += watchdog.c diff --git a/src/southbridge/intel/i82801cx/Makefile.inc b/src/southbridge/intel/i82801cx/Makefile.inc index 9c5c7fb..c375476 100644 --- a/src/southbridge/intel/i82801cx/Makefile.inc +++ b/src/southbridge/intel/i82801cx/Makefile.inc @@ -1,8 +1,8 @@ -driver-y += i82801cx.c -driver-y += usb.c -driver-y += lpc.c -driver-y += ide.c -driver-y += ac97.c -#driver-y += nic.c -driver-y += pci.c +ramstage-y += i82801cx.c +ramstage-y += usb.c +ramstage-y += lpc.c +ramstage-y += ide.c +ramstage-y += ac97.c +#ramstage-y += nic.c +ramstage-y += pci.c ramstage-y += reset.c diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 9644210..e412ef9 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -19,13 +19,13 @@ ## MA 02110-1301 USA ## -driver-y += i82801dx.c -driver-y += ac97.c -driver-y += ide.c -driver-y += lpc.c -#driver-y += pci.c -driver-y += usb.c -driver-y += usb2.c +ramstage-y += i82801dx.c +ramstage-y += ac97.c +ramstage-y += ide.c +ramstage-y += lpc.c +#ramstage-y += pci.c +ramstage-y += usb.c +ramstage-y += usb2.c ramstage-y += reset.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc index e0d3148..fb76a98 100644 --- a/src/southbridge/intel/i82801ex/Makefile.inc +++ b/src/southbridge/intel/i82801ex/Makefile.inc @@ -1,11 +1,11 @@ -driver-y += i82801ex.c -driver-y += uhci.c -driver-y += lpc.c -driver-y += ide.c -driver-y += sata.c -driver-y += ehci.c -driver-y += smbus.c -driver-y += pci.c -driver-y += ac97.c +ramstage-y += i82801ex.c +ramstage-y += uhci.c +ramstage-y += lpc.c +ramstage-y += ide.c +ramstage-y += sata.c +ramstage-y += ehci.c +ramstage-y += smbus.c +ramstage-y += pci.c +ramstage-y += ac97.c ramstage-y += watchdog.c ramstage-y += reset.c diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index c23a314..b286576 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -17,18 +17,18 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += i82801gx.c -driver-y += ac97.c -driver-y += azalia.c -driver-y += ide.c -driver-y += lpc.c -driver-y += nic.c -driver-y += pci.c -driver-y += pcie.c -driver-y += sata.c -driver-y += smbus.c -driver-y += usb.c -driver-y += usb_ehci.c +ramstage-y += i82801gx.c +ramstage-y += ac97.c +ramstage-y += azalia.c +ramstage-y += ide.c +ramstage-y += lpc.c +ramstage-y += nic.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c +ramstage-y += smbus.c +ramstage-y += usb.c +ramstage-y += usb_ehci.c ramstage-y += reset.c ramstage-y += watchdog.c diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc index 7ca6fb5..190aa4f 100644 --- a/src/southbridge/intel/i82870/Makefile.inc +++ b/src/southbridge/intel/i82870/Makefile.inc @@ -1,3 +1,3 @@ -driver-y += ioapic.c -driver-y += pcibridge.c -#driver-y += pci_parity.c +ramstage-y += ioapic.c +ramstage-y += pcibridge.c +#ramstage-y += pci_parity.c diff --git a/src/southbridge/intel/pxhd/Makefile.inc b/src/southbridge/intel/pxhd/Makefile.inc index d5b3a5f..ce96c97 100644 --- a/src/southbridge/intel/pxhd/Makefile.inc +++ b/src/southbridge/intel/pxhd/Makefile.inc @@ -1 +1 @@ -driver-y += bridge.c +ramstage-y += bridge.c diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc index 42ff877..d7c245a 100644 --- a/src/southbridge/intel/sch/Makefile.inc +++ b/src/southbridge/intel/sch/Makefile.inc @@ -17,16 +17,16 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += south.c -driver-y += audio.c -driver-y += lpc.c -driver-y += ide.c -driver-y += pcie.c -driver-y += usb.c -driver-y += usb_ehci.c -driver-y += usb_client.c -driver-y += mmc.c -driver-y += smbus.c +ramstage-y += south.c +ramstage-y += audio.c +ramstage-y += lpc.c +ramstage-y += ide.c +ramstage-y += pcie.c +ramstage-y += usb.c +ramstage-y += usb_ehci.c +ramstage-y += usb_client.c +ramstage-y += mmc.c +ramstage-y += smbus.c ramstage-y += reset.c diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index debe227..bfafa23 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -1,15 +1,15 @@ -driver-y += ck804.c -driver-y += usb.c -driver-y += lpc.c -driver-y += smbus.c -driver-y += ide.c -driver-y += sata.c -driver-y += usb2.c -driver-y += ac97.c -driver-y += nic.c -driver-y += pci.c -driver-y += pcie.c -driver-y += ht.c +ramstage-y += ck804.c +ramstage-y += usb.c +ramstage-y += lpc.c +ramstage-y += smbus.c +ramstage-y += ide.c +ramstage-y += sata.c +ramstage-y += usb2.c +ramstage-y += ac97.c +ramstage-y += nic.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += ht.c ramstage-y += reset.c diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 26844da..b20804a 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -1,17 +1,17 @@ -driver-y += mcp55.c -driver-y += azalia.c -driver-y += ht.c -driver-y += ide.c -driver-y += lpc.c -driver-y += nic.c -driver-y += pci.c -driver-y += pcie.c -driver-y += sata.c -driver-y += smbus.c -driver-y += usb2.c -driver-y += usb.c +ramstage-y += mcp55.c +ramstage-y += azalia.c +ramstage-y += ht.c +ramstage-y += ide.c +ramstage-y += lpc.c +ramstage-y += nic.c +ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-y += sata.c +ramstage-y += smbus.c +ramstage-y += usb2.c +ramstage-y += usb.c -driver-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-y += reset.c diff --git a/src/southbridge/rdc/r8610/Makefile.inc b/src/southbridge/rdc/r8610/Makefile.inc index 24d76a8..8820b09 100644 --- a/src/southbridge/rdc/r8610/Makefile.inc +++ b/src/southbridge/rdc/r8610/Makefile.inc @@ -17,4 +17,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += r8610.c +ramstage-y += r8610.c diff --git a/src/southbridge/ricoh/rl5c476/Makefile.inc b/src/southbridge/ricoh/rl5c476/Makefile.inc index 71604b7..3156706 100644 --- a/src/southbridge/ricoh/rl5c476/Makefile.inc +++ b/src/southbridge/ricoh/rl5c476/Makefile.inc @@ -1 +1 @@ -driver-y += rl5c476.c +ramstage-y += rl5c476.c diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index 76dd31a..b25aa9e 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -1,13 +1,13 @@ -driver-y += sis761.c -driver-y += sis966.c -driver-y += lpc.c -driver-y += ide.c -driver-y += usb.c -driver-y += usb2.c -driver-y += nic.c -driver-y += sata.c -driver-y += pcie.c -driver-y += aza.c +ramstage-y += sis761.c +ramstage-y += sis966.c +ramstage-y += lpc.c +ramstage-y += ide.c +ramstage-y += usb.c +ramstage-y += usb2.c +ramstage-y += nic.c +ramstage-y += sata.c +ramstage-y += pcie.c +ramstage-y += aza.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c diff --git a/src/southbridge/ti/pci1x2x/Makefile.inc b/src/southbridge/ti/pci1x2x/Makefile.inc index d6a9c0c..7c0e4aa 100644 --- a/src/southbridge/ti/pci1x2x/Makefile.inc +++ b/src/southbridge/ti/pci1x2x/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x.c +ramstage-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x.c diff --git a/src/southbridge/ti/pci7420/Makefile.inc b/src/southbridge/ti/pci7420/Makefile.inc index 5081694..7d27b96 100644 --- a/src/southbridge/ti/pci7420/Makefile.inc +++ b/src/southbridge/ti/pci7420/Makefile.inc @@ -17,6 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += cardbus.c -driver-y += firewire.c +ramstage-y += cardbus.c +ramstage-y += firewire.c diff --git a/src/southbridge/ti/pcixx12/Makefile.inc b/src/southbridge/ti/pcixx12/Makefile.inc index a14ad0e..99ef4dd 100644 --- a/src/southbridge/ti/pcixx12/Makefile.inc +++ b/src/southbridge/ti/pcixx12/Makefile.inc @@ -17,5 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += pcixx12.c +ramstage-y += pcixx12.c diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 972ff70..6d9407d 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -1,12 +1,12 @@ -driver-y += ctrl.c -driver-y += dram.c -driver-y += bridge.c -driver-y += host.c -driver-y += host_ctrl.c -driver-y += pcie.c -driver-y += traf_ctrl.c -driver-y += error.c -driver-y += chrome.c +ramstage-y += ctrl.c +ramstage-y += dram.c +ramstage-y += bridge.c +ramstage-y += host.c +ramstage-y += host_ctrl.c +ramstage-y += pcie.c +ramstage-y += traf_ctrl.c +ramstage-y += error.c +ramstage-y += chrome.c chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds diff --git a/src/southbridge/via/vt8231/Makefile.inc b/src/southbridge/via/vt8231/Makefile.inc index b9e7ef6..0f5f507 100644 --- a/src/southbridge/via/vt8231/Makefile.inc +++ b/src/southbridge/via/vt8231/Makefile.inc @@ -17,9 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += vt8231.c -driver-y += lpc.c -driver-y += acpi.c -driver-y += ide.c -driver-y += nic.c -#driver-y += usb.c +ramstage-y += vt8231.c +ramstage-y += lpc.c +ramstage-y += acpi.c +ramstage-y += ide.c +ramstage-y += nic.c +#ramstage-y += usb.c diff --git a/src/southbridge/via/vt8235/Makefile.inc b/src/southbridge/via/vt8235/Makefile.inc index 02e2264..a5469c9 100644 --- a/src/southbridge/via/vt8235/Makefile.inc +++ b/src/southbridge/via/vt8235/Makefile.inc @@ -17,8 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += vt8235.c -driver-y += ide.c -driver-y += lpc.c -driver-y += nic.c -driver-y += usb.c +ramstage-y += vt8235.c +ramstage-y += ide.c +ramstage-y += lpc.c +ramstage-y += nic.c +ramstage-y += usb.c diff --git a/src/southbridge/via/vt8237r/Makefile.inc b/src/southbridge/via/vt8237r/Makefile.inc index 6474e58..73d8f5a 100644 --- a/src/southbridge/via/vt8237r/Makefile.inc +++ b/src/southbridge/via/vt8237r/Makefile.inc @@ -17,13 +17,13 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -driver-y += vt8237r.c -driver-y += ctrl.c -driver-y += ide.c -driver-y += lpc.c -driver-y += sata.c -driver-y += usb.c -driver-$(CONFIG_PIRQ_ROUTE) += pirq.c +ramstage-y += vt8237r.c +ramstage-y += ctrl.c +ramstage-y += ide.c +ramstage-y += lpc.c +ramstage-y += sata.c +ramstage-y += usb.c +ramstage-$(CONFIG_PIRQ_ROUTE) += pirq.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

1 0

New patch to review for coreboot: b5c7768 Add nvramcui
by Patrick Georgi 16 Nov '12

16 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1871 -gerrit commit b5c7768ecadcdda8ab12204fd40b9f153da82027 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Nov 16 15:05:11 2012 +0100 Add nvramcui nvramcui is a small libpayload based utility that provides an interactive CMOS editor for pre-boot environments. Change-Id: I514b8a7682f89d242d1b31b6907cc6bff34da4bf Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/nvramcui/nvramcui.c | 247 +++++++++++++++++++++++++++++++++++++++++++ payloads/nvramcui/payload.sh | 7 ++ 2 files changed, 254 insertions(+) diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c new file mode 100644 index 0000000..e980130 --- /dev/null +++ b/payloads/nvramcui/nvramcui.c @@ -0,0 +1,247 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <string.h> + +#include <libpayload.h> +#include <coreboot_tables.h> + +#include <curses.h> +#include <menu.h> +#include <form.h> + +#ifndef HOSTED +#define HOSTED 0 +#endif + +static int min(int x, int y) +{ + if (x < y) + return x; + return y; +} + +static int max(int x, int y) +{ + if (x > y) + return x; + return y; +} + +void render_form(FORM *form) +{ + int y, x, line; + WINDOW *w = form_win(form); + WINDOW *inner_w = form_sub(form); + int numlines = getmaxy(w)-2; + getyx(inner_w, y, x); + line = y - (y % numlines); + WINDOW *der = derwin(w, getmaxy(w)-2, getmaxx(w)-2, 1, 1); + wclear(der); + wrefresh(der); + delwin(der); + copywin(inner_w, w, line, 0, 1, 1, min(numlines, getmaxy(inner_w)-line), 68, 0); + wmove(w, y + 1 - line, x + 1); + wrefresh(w); +} + +int main() +{ + int ch, done; + ITEM *cur; + + /* coreboot data structures */ + lib_get_sysinfo(); + + struct cb_cmos_option_table *opttbl = get_system_option_table(); + + if (opttbl == NULL) { + printf("Could not find coreboot option table\n"); + halt(); + } + + /* display initialization */ + initscr(); + keypad(stdscr, TRUE); + cbreak(); + noecho(); + start_color(); + leaveok(stdscr, TRUE); + curs_set(1); + + erase(); + box(stdscr, 0, 0); + mvaddstr(0, 2, "coreboot configuration utility"); + + /* prep CMOS layout into libcurses data structures */ + + /* determine number of options, and maximum option name length */ + int numopts=0; + int maxlength=0; + struct cb_cmos_entries *option = first_cmos_entry(opttbl); + while (option) { + if ((option->config != 'r') && (strcmp("check_sum", option->name) != 0)) { + maxlength = max(maxlength, strlen(option->name)); + numopts++; + } + option = next_cmos_entry(option); + } + if (numopts == 0) { + printf("NO CMOS OPTIONS FOUND. EXITING!!!"); + return 1; + } + FIELD **fields = malloc(sizeof(FIELD*)*(2*numopts+1)); + int i; + + /* walk over options, fetch details */ + option = first_cmos_entry(opttbl); + for (i=0;i<numopts;i++) { + while ((option->config == 'r') || (strcmp("check_sum", option->name) == 0)) { + option = next_cmos_entry(option); + } + fields[2*i] = new_field(1, strlen(option->name), i*2, 1, 0, 0); + set_field_buffer(fields[2*i], 0, option->name); + field_opts_off(fields[2*i], O_ACTIVE); + + fields[2*i+1] = new_field(1, 40, i*2, maxlength+2, 0, 0); + char *buf = NULL; + int fail = get_option_as_string(use_nvram, opttbl, &buf, option->name); + switch (option->config) { + case 'h': { + set_field_type(fields[2*i+1], TYPE_INTEGER, 0, 0, (1<<option->length)-1); + field_opts_on(fields[2*i+1], O_BLANK); + break; + } + case 's': { + set_max_field(fields[2*i+1], option->length/8); + field_opts_off(fields[2*i+1], O_STATIC); + break; + } + case 'e': { + int numvals = 0; + struct cb_cmos_enums *cmos_enum = first_cmos_enum_of_id(opttbl, option->config_id); + + /* if invalid data in CMOS, set buf to first enum */ + if (fail && cmos_enum) { + buf = cmos_enum->text; + } + + while (cmos_enum) { + numvals++; + cmos_enum = next_cmos_enum_of_id(cmos_enum, option->config_id); + } + + char **values = malloc(sizeof(char*)*numvals + 1); + int cnt = 0; + + cmos_enum = first_cmos_enum_of_id(opttbl, option->config_id); + while (cmos_enum) { + values[cnt] = cmos_enum->text; + cnt++; + cmos_enum = next_cmos_enum_of_id(cmos_enum, option->config_id); + } + values[cnt] = NULL; + field_opts_off(fields[2*i+1], O_EDIT); + set_field_type(fields[2*i+1], TYPE_ENUM, values, 1, 1); + free(values); // copied by set_field_type + break; + } + default: + break; + } + if (buf) set_field_buffer(fields[2*i+1], 0, buf); +#if HOSTED +// underline is non-trivial on VGA text + set_field_back(fields[2*i+1], A_UNDERLINE); +#endif + field_opts_off(fields[2*i+1], O_BLANK | O_AUTOSKIP | O_NULLOK); + + option = next_cmos_entry(option); + } + fields[2*numopts]=NULL; + + FORM *form = new_form(fields); + int numlines = min(numopts*2, 16); + WINDOW *w = newwin(numlines+2, 70, 2, 1); + WINDOW *inner_w = newpad(numopts*2, 68); + box(w, 0, 0); + mvwaddstr(w, 0, 2, "Press F1 when done"); + set_form_win(form, w); + set_form_sub(form, inner_w); + post_form(form); + + done = 0; + while(!done) { + ch=getch(); + if (ch == ERR) continue; + switch (ch) { + case KEY_DOWN: + form_driver(form, REQ_NEXT_FIELD); + break; + case KEY_UP: + form_driver(form, REQ_PREV_FIELD); + break; + case KEY_LEFT: + if (field_type(current_field(form)) == TYPE_ENUM) { + form_driver(form, REQ_PREV_CHOICE); + } else { + form_driver(form, REQ_LEFT_CHAR); + } + break; + case KEY_RIGHT: + if (field_type(current_field(form)) == TYPE_ENUM) { + form_driver(form, REQ_NEXT_CHOICE); + } else { + form_driver(form, REQ_RIGHT_CHAR); + } + break; + case KEY_BACKSPACE: + case '\b': + form_driver(form, REQ_DEL_PREV); + break; + case KEY_DC: + form_driver(form, REQ_DEL_CHAR); + break; + case KEY_F(1): + done=1; + break; + default: + form_driver(form, ch); + break; + } + render_form(form); + } + + for (i = 0; i < numopts; i++) { + char *name = field_buffer(fields[2*i], 0); + char *value = field_buffer(fields[2*i+1], 0); + set_option_from_string(use_nvram, opttbl, value, name); + } + + unpost_form(form); + free_form(form); + touchwin(stdscr); + refresh(); + + endwin(); + /* TODO: reboot */ + halt(); +} + diff --git a/payloads/nvramcui/payload.sh b/payloads/nvramcui/payload.sh new file mode 100755 index 0000000..57ed38b --- /dev/null +++ b/payloads/nvramcui/payload.sh @@ -0,0 +1,7 @@ +#!/bin/sh +# +# This is a trivial payload compile & find script for abuild +# +DIR=`dirname $0` +lpgcc -o $DIR/nvramcui.elf $DIR/nvramcui.c 2>&1 >/dev/null || exit 1 +echo "$DIR/nvramcui.elf"

1 0

Patch set updated for coreboot: 7ccf524 roda/rk9: New mainboard
by Patrick Georgi 16 Nov '12

16 Nov '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1691 -gerrit commit 7ccf524f3d0679674bf2e2673a4e27a2ec0b5b7d Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 6 11:05:38 2012 +0100 roda/rk9: New mainboard Roda RK9 is a notebook based on the GM45/ICH9 platform using DDR3 memory. http://roda-computer.com/products/notebooks/rk9/ Tested with various Linux versions, known to work: - 2x4GB RAM - IGD - HD Audio - UHCI, EHCI - AHCI - NIC - PCI - PS/2 keyboard - serial console - ACPI lid switch - ACPI battery/AC events - power off, reboot Change-Id: I7299dccbff2eea3544363fdd4f49f05aa3dae7bc Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/mainboard/roda/Kconfig | 4 + src/mainboard/roda/rk9/Kconfig | 46 ++++ src/mainboard/roda/rk9/Makefile.inc | 21 ++ src/mainboard/roda/rk9/acpi/battery.asl | 232 ++++++++++++++++ src/mainboard/roda/rk9/acpi/ec.asl | 197 ++++++++++++++ src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl | 86 ++++++ src/mainboard/roda/rk9/acpi/gpe.asl | 120 +++++++++ src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl | 110 ++++++++ src/mainboard/roda/rk9/acpi/mainboard.asl | 44 +++ src/mainboard/roda/rk9/acpi/platform.asl | 209 +++++++++++++++ src/mainboard/roda/rk9/acpi/superio.asl | 368 ++++++++++++++++++++++++++ src/mainboard/roda/rk9/acpi/thermal.asl | 115 ++++++++ src/mainboard/roda/rk9/acpi/video.asl | 45 ++++ src/mainboard/roda/rk9/acpi_tables.c | 313 ++++++++++++++++++++++ src/mainboard/roda/rk9/cmos.layout | 141 ++++++++++ src/mainboard/roda/rk9/cstates.c | 41 +++ src/mainboard/roda/rk9/devicetree.cb | 152 +++++++++++ src/mainboard/roda/rk9/dsdt.asl | 56 ++++ src/mainboard/roda/rk9/fadt.c | 158 +++++++++++ src/mainboard/roda/rk9/hda_verb.h | 74 ++++++ src/mainboard/roda/rk9/mainboard.c | 147 ++++++++++ src/mainboard/roda/rk9/mainboard_smi.c | 76 ++++++ src/mainboard/roda/rk9/mptable.c | 1 + src/mainboard/roda/rk9/romstage.c | 211 +++++++++++++++ src/mainboard/roda/rk9/ti_pci7xx1.c | 71 +++++ 25 files changed, 3038 insertions(+) diff --git a/src/mainboard/roda/Kconfig b/src/mainboard/roda/Kconfig index ba4b6ec..b70ce33 100644 --- a/src/mainboard/roda/Kconfig +++ b/src/mainboard/roda/Kconfig @@ -6,9 +6,13 @@ choice config BOARD_RODA_RK886EX bool "RK886EX" +config BOARD_RODA_RK9 + bool "RK9" + endchoice source "src/mainboard/roda/rk886ex/Kconfig" +source "src/mainboard/roda/rk9/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig new file mode 100644 index 0000000..dd9e940 --- /dev/null +++ b/src/mainboard/roda/rk9/Kconfig @@ -0,0 +1,46 @@ +if BOARD_RODA_RK9 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_BGA956 + select NORTHBRIDGE_INTEL_GM45 + select SOUTHBRIDGE_INTEL_I82801IX + select SUPERIO_SMSC_LPC47N227 + select MMCONF_SUPPORT + select BOARD_ROMSIZE_KB_4096 + select RTL8168_ROM_DISABLE + select DRIVERS_GENERIC_IOAPIC + select HAVE_MP_TABLE + select CARDBUS_PLUGIN_SUPPORT + select BOARD_HAS_FADT + select HAVE_ACPI_TABLES + #select HAVE_ACPI_RESUME + select EC_ACPI + select HAVE_OPTION_TABLE + +config MAINBOARD_DIR + string + default roda/rk9 + +config MAINBOARD_PART_NUMBER + string + default "RK9" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +endif # BOARD_RODA_RK9 diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc new file mode 100644 index 0000000..27feaab --- /dev/null +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 secunet Security Networks AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/roda/rk9/acpi/battery.asl b/src/mainboard/roda/rk9/acpi/battery.asl new file mode 100644 index 0000000..3eb9b14 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/battery.asl @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Name(\CBA1, 0x60) +Name(\CBA2, 0x60) + +/* ACPI doesn't care if capacity is given in mWh or mAh, + but it has to be consistent */ + +Device (BAT1) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 1) + + Name(_PCL, Package(){ _SB }) + Name(PSTA, 0x1f) + + /* battery information */ + Name(PBIF, Package() { + 0x01, // power unit + 0x01, // design capacity (mWh/mAh), updated by UPBI + 0x01, // last full charge capacity (mWh/mAh), updated by UPBI + 0x01, // battery technology: "rechargeable" + 0x01, // design voltage (mV), updated by UPBI + 0x0294, // design capacity of warning (mWh/mAh) + 0x014a, // design capacity of low (mWh/mAh) + 0x42, // battery capacity granularity between low and warning + 0x42, // battery capacity granularity between warning and full + "BAT1", // Name + "001 ", // Number + "LION", // Type + "JSE" // Vendor + }) + /* battery status */ + /* dummy values, filled in by UPBS */ + Name(PBST, Package() { + 0x00, // battery state + // bit0: discharging + // bit1: charging + // bit2: critical energy state + 0x01, // battery present rate (mW/mA) + 0x01, // remaining capacity (mW/mA) + 0x01 // battery present voltage (mV) + }) + + /* Status */ + Method(_STA, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + If(\_SB.PCI0.LPCB.EC0.B1PR) { + If(\_SB.PCI0.LPCB.EC0.B1CH) { + Return(0x1f) + } + } + } + Return(0x0f) + } + + /* Battery Info */ + Method(_BIF, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B1DW, Index(PBIF, 1)) + Store (\_SB.PCI0.LPCB.EC0.B1FW, Index(PBIF, 2)) + Store (\_SB.PCI0.LPCB.EC0.B1DV, Index(PBIF, 4)) + } + + Return(PBIF) + } + + /* Battery Status */ + Method(_BST, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B1PW, Local0) + If (LGreaterEqual (Local0, 0x8000)) { + Subtract (0x10000, Local0, Local0) + } + Store (Local0, Index(PBST, 1)) + Store (\_SB.PCI0.LPCB.EC0.B1PV, Index(PBST, 3)) + + Store (\_SB.PCI0.LPCB.EC0.B1RW, Index(PBST, 2)) + + If (\_SB.PCI0.LPCB.EC0.ACCH) { + If (\_SB.PCI0.LPCB.EC0.B1CH) { + If (\_SB.PCI0.LPCB.EC0.B1CG) { + Store (2, Index(PBST, 0)) + } + } + } Else { + If (\_SB.PCI0.LPCB.EC0.B1LO) { + Store (5, Index(PBST, 0)) + } Else { + Store (1, Index(PBST, 0)) + } + } + } + + Return(PBST) + } + +} + +Device (BAT2) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 2) + + Name(_PCL, Package(){ _SB }) + Name(PSTA, 0x1f) + + /* battery information */ + Name(PBIF, Package() { + 0x01, // power unit + 0x01, // design capacity (mWh/mAh), updated by UPBI + 0x01, // last full charge capacity (mWh/mAh), updated by UPBI + 0x01, // battery technology: "rechargeable" + 0x01, // design voltage (mV), updated by UPBI + 0x0294, // design capacity of warning (mWh/mAh) + 0x014a, // design capacity of low (mWh/mAh) + 0x42, // battery capacity granularity between low and warning + 0x42, // battery capacity granularity between warning and full + "BAT1", // Name + "002 ", // Number + "LION", // Type + "JSE" // Vendor + }) + /* battery status */ + /* dummy values, filled in by UPBS */ + Name(PBST, Package() { + 0x00, // battery state + // bit0: discharging + // bit1: charging + // bit2: critical energy state + 0x01, // battery present rate (mW/mA) + 0x01, // remaining capacity (mW/mA) + 0x01 // battery present voltage (mV) + }) + + /* Status */ + Method(_STA, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + If(\_SB.PCI0.LPCB.EC0.B2PR) { + If(\_SB.PCI0.LPCB.EC0.B2CH) { + Return(0x1f) + } + } + } + Return(0x0f) + } + + /* Battery Info */ + Method(_BIF, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B2DW, Index(PBIF, 1)) + Store (\_SB.PCI0.LPCB.EC0.B2FW, Index(PBIF, 2)) + Store (\_SB.PCI0.LPCB.EC0.B2DV, Index(PBIF, 4)) + } + + Return(PBIF) + } + + /* Battery Status */ + Method(_BST, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B2PW, Local0) + If (LGreaterEqual (Local0, 0x8000)) { + Subtract (0x10000, Local0, Local0) + } + Store (Local0, Index(PBST, 1)) + Store (\_SB.PCI0.LPCB.EC0.B2PV, Index(PBST, 3)) + + Store (\_SB.PCI0.LPCB.EC0.B2RW, Index(PBST, 2)) + + If (\_SB.PCI0.LPCB.EC0.ACCH) { + If (\_SB.PCI0.LPCB.EC0.B2CH) { + If (\_SB.PCI0.LPCB.EC0.B2CG) { + Store (2, Index(PBST, 0)) + } + } + } Else { + If (\_SB.PCI0.LPCB.EC0.B2LO) { + Store (5, Index(PBST, 0)) + } Else { + Store (1, Index(PBST, 0)) + } + } + } + + Return(PBST) + } + +} + +Device (ADP1) +{ + Name (_HID, "ACPI0003") + Method (_PSR, 0) + { + Store (\_SB.PCI0.LPCB.EC0.ACCH, PWRS) + Stall (0x02) + Return (PWRS) + } + + Method (_PCL, 0) + { + Return (_SB) + } +} + diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl new file mode 100644 index 0000000..3e6cb98 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + Name (ECON, 0) + Name (QEVT, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0xb1), + CPWR, 1, + ACCH, 1, // AC connected (charger present) + B1PR, 1, // battery 1 present + B2PR, 1, // battery 2 present + B1CH, 1, // battery 1 charged + B2CH, 1, // battery 2 charged + Offset(0xb2), + B1CG, 1, // battery 1 charging + B2CG, 1, // battery 2 charging + B1LO, 1, // battery 1 low + B2LO, 1, // battery 2 low + Offset(0xb3), + B1DW, 16, // battery 1 design capacity + B1FW, 16, // battery 1 last full charge capacity + B1DV, 16, // battery 1 design voltage + B1PW, 16, // battery 1 present capacity + Offset(0xbd), + B1PV, 16, // battery 1 present voltage + Offset(0xc1), + B2DW, 16, // battery 2 design capacity + B2FW, 16, // battery 2 last full charge capacity + B2DV, 16, // battery 2 design voltage + B2PW, 16, // battery 2 present capacity + Offset(0xcb), + B2PV, 16, // battery 2 present voltage + Offset(0xcf), + FDDI, 1, // floppy on lpt indicator? + LIDC, 1, // LID switch + Offset(0xd0), + TCPU, 8, // T_CPU in deg Celcius + Offset(0xd6), + /* exact purpose of these three is guessed, + but it's something about cooling */ + ALRL, 1, // active cooling low limit + ALRH, 1, // active cooling high limit + ALRC, 1, // active cooling clear + Offset(0xe8), + B1RW, 16, // battery 1 remaining capacity + B2RW, 16, // battery 2 remaining capacity + } + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 for + // EC initialization before a driver is loaded + + If (LEqual(Arg0, 0x03)) { + Store (Arg1, ECON) + } + } + + // EC Query methods + + Method (_Q11, 0) + { + Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug) + Notify(SLPB, 0x80) + } + + Method (_Q30, 0) + { + Store("_Q30: AC In", Debug) + Notify(ADP1, 0x80) // Tell the Power Adapter + PNOT() // and the CPU and Battery + } + + Method (_Q31, 0) + { + Store("_Q31: AC Out", Debug) + Notify(ADP1, 0x80) // Tell the Power Adapter + PNOT() // and the CPU and Battery + } + + Method (_Q32, 0) + { + Store("_Q32: Bat1 In", Debug) + Notify(BAT1, 0x81) + } + + Method (_Q33, 0) + { + Store("_Q33: Bat1 Out", Debug) + Notify(BAT1, 0x81) + } + + Method (_Q34, 0) + { + Store("_Q34: Bat2 In", Debug) + Notify(BAT2, 0x81) + } + + Method (_Q35, 0) + { + Store("_Q35: Bat2 Out", Debug) + Notify(BAT2, 0x81) + } + + Method (_Q36, 0) + { + Store("_Q36: Bat1 Low Power", Debug) + Notify(BAT1, 0x80) + } + + Method (_Q37, 0) + { + Store("_Q37: Bat1 Full Charge", Debug) + Notify(BAT1, 0x80) + } + + Method (_Q38, 0) + { + Store("_Q38: Bat2 Low Power", Debug) + Notify(BAT2, 0x80) + } + + Method (_Q39, 0) + { + Store("_Q39: Bat2 Full Charge", Debug) + Notify(BAT2, 0x80) + } + + Method (_Q40, 0) + { + Store("_Q40: LID Open/Close", Debug) + Notify(LID0, 0x80) + } + + Method (_Q41, 0) + { + Store("_Q41: Floppy on Parallel Port: Call the Museum!", Debug) + } + + Method (_Q50, 0) + { + Store("_Q50: Processor is hot", Debug) + Notify(\_TZ.THRM, 0x80) + } + + Method (_Q51, 0) + { + Store("_Q51: Processor is boiling", Debug) + Notify(\_TZ.THRM, 0x80) + } + + Method (_Q52, 0) + { + Store("_Q52: Processor is burning", Debug) + Notify(\_TZ.THRM, 0x80) + } + +} diff --git a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl new file mode 100644 index 0000000..83c7762 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * gm45 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // USB and EHCI 0:1a.x + Package() { 0x001affff, 0, 0, 16 }, + Package() { 0x001affff, 1, 0, 17 }, + Package() { 0x001affff, 2, 0, 18 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 16 }, + Package() { 0x001dffff, 1, 0, 17 }, + Package() { 0x001dffff, 2, 0, 18 }, + // FIXME + // CardBus/IEEE1394 0:1e.2, 0:1e.3 + // Package() { 0x001effff, 0, 0, 22 }, + // Package() { 0x001effff, 1, 0, 20 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 16 }, + Package() { 0x001fffff, 1, 0, 17 }, + Package() { 0x001fffff, 2, 0, 18 } + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // USB and EHCI 0:1a.x + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + // FIXME + // CardBus/IEEE1394 0:1e.2, 0:1e.3 + // Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 } + }) + } +} + diff --git a/src/mainboard/roda/rk9/acpi/gpe.asl b/src/mainboard/roda/rk9/acpi/gpe.asl new file mode 100644 index 0000000..5854006 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/gpe.asl @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (_GPE) +{ + /* The event numbers correspond to the bit numbers in the + * GPE0_EN register PMBASE + 0x28. + */ + /* IMO we don't need empty Methods here. If we don't specify + one and don't set the GPE0_EN bit Linux won't neither enable + it. - Nico */ + + // Thermal Event - original BIOS doesn't have it + Method (_L00, 0) + { + /* FIXME: We should enable throttling here. */ + } + + // Hot Plug + Method (_L01, 0) + { + + } + + // USB1 + Method (_L03, 0) + { + + } + + // USB2 + Method (_L04, 0) + { + + } + + // USB5 + Method (_L05, 0) + { + + } + + // _L06 TCOSCI + + // SMBus Wake Status + Method (_L07, 0) + { + + } + + // COM1/COM2 (RI) + Method (_L08, 0) + { + + } + + // PCIe + Method (_L09, 0) + { + + } + + // _L0A BatLow / Quick Resume + + // PME + Method (_L0B, 0) + { + + } + + // USB3 + Method (_L0C, 0) + { + + } + + // PME B0 + Method (_L0D, 0) + { + + } + + // USB4 + Method (_L0E, 0) + { + + } + + // _L10 - _L1f: GPIn + + // GPI8 + Method (_L18, 0) + { + + } + + // USB6 + Method (_L20, 0) + { + + } +} diff --git a/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl new file mode 100644 index 0000000..325f13c --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH9 + */ + +/* TODO: which slots are actually relevant? */ +If (PICM) { + Return (Package() { + // PCI Slot 1 routes ABCD + Package() { 0x0000ffff, 0, 0, 16}, + Package() { 0x0000ffff, 1, 0, 17}, + Package() { 0x0000ffff, 2, 0, 18}, + Package() { 0x0000ffff, 3, 0, 19}, + + // PCI Slot 2 routes BCDA + Package() { 0x0001ffff, 0, 0, 17}, + Package() { 0x0001ffff, 1, 0, 18}, + Package() { 0x0001ffff, 2, 0, 19}, + Package() { 0x0001ffff, 3, 0, 16}, + + // PCI Slot 3 routes CDAB + Package() { 0x0002ffff, 0, 0, 18}, + Package() { 0x0002ffff, 1, 0, 19}, + Package() { 0x0002ffff, 2, 0, 16}, + Package() { 0x0002ffff, 3, 0, 17}, + + // PCI Slot 4 routes ABCD + Package() { 0x0003ffff, 0, 0, 16}, + Package() { 0x0003ffff, 1, 0, 17}, + Package() { 0x0003ffff, 2, 0, 18}, + Package() { 0x0003ffff, 3, 0, 19}, + + // PCI Slot 5 routes ABCD + Package() { 0x0004ffff, 0, 0, 16}, + Package() { 0x0004ffff, 1, 0, 17}, + Package() { 0x0004ffff, 2, 0, 18}, + Package() { 0x0004ffff, 3, 0, 19}, + + // PCI Slot 6 routes BCDA + Package() { 0x0005ffff, 0, 0, 17}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 19}, + Package() { 0x0005ffff, 3, 0, 16}, + + // FIXME: what's this supposed to mean? (adopted from ich7) + //Package() { 0x0008ffff, 0, 0, 20}, + }) +} Else { + Return (Package() { + // PCI Slot 1 routes ABCD + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 2 routes BCDA + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + // PCI Slot 3 routes CDAB + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0}, + + // PCI Slot 4 routes ABCD + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 5 routes ABCD + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 6 routes BCDA + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + // FIXME + // Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} + diff --git a/src/mainboard/roda/rk9/acpi/mainboard.asl b/src/mainboard/roda/rk9/acpi/mainboard.asl new file mode 100644 index 0000000..0837ed3 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/mainboard.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LID0) +{ + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Return (\_SB.PCI0.LPCB.EC0.LIDC) + } +} + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x18, 0x04}) +} + +#include "acpi/battery.asl" diff --git a/src/mainboard/roda/rk9/acpi/platform.asl b/src/mainboard/roda/rk9/acpi/platform.asl new file mode 100644 index 0000000..b85433f --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/platform.asl @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* These come from the dynamically created CPU SSDT */ +External(PDC0) +External(PDC1) + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + // TODO: Return Arg0 as second value if S-Arg0 was entered + // before. + + Return(Package(){0,0}) +} + +// Power notification + +External (\_PR_.CPU0, DeviceObj) +External (\_PR_.CPU1, DeviceObj) + +Method (PNOT) +{ + If (MPEN) { + If(And(PDC0, 0x08)) { + Notify (\_PR_.CPU0, 0x80) // _PPC + + If (And(PDC0, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU0, 0x81) // _CST + } + } + + If(And(PDC1, 0x08)) { + Notify (\_PR_.CPU1, 0x80) // _PPC + If (And(PDC1, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU1, 0x81) // _CST + } + } + + } Else { // UP + Notify (\_PR_.CPU0, 0x80) + Sleep(0x64) + Notify(\_PR_.CPU0, 0x81) + } + + // Notify the Batteries + Notify(BAT1, 0x80) // Execute BAT1 _BST + Notify(BAT2, 0x80) // Execute BAT2 _BST +} + +/* System Bus */ + +Scope(\_SB) +{ + /* This method is placed on the top level, so we can make sure it's the + * first executed _INI method. + */ + Method(_INI, 0) + { + /* The DTS data in NVS is probably not up to date. + * Update temperature values and make sure AP thermal + * interrupts can happen + */ + + // TRAP(71) // TODO + + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI, Local0)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + } + + /* And the OS workarounds start right after we know what we're + * running: Windows XP SP1 needs to have C-State coordination + * enabled in SMM. + */ + If (LAnd(LEqual(OSYS, 2001), MPEN)) { + // TRAP(61) // TODO + } + + /* SMM power state and C4-on-C3 settings need to be updated */ + // TRAP(43) // TODO + } +} + diff --git a/src/mainboard/roda/rk9/acpi/superio.asl b/src/mainboard/roda/rk9/acpi/superio.asl new file mode 100644 index 0000000..174f2f1 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/superio.asl @@ -0,0 +1,368 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* SMSC LPC47N227 */ + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + OperationRegion(SIOR, SystemIO, 0x2e, 0x02) + Field (SIOR, ByteAcc, Nolock, Preserve) + { + INDX, 8, + DATA, 8 + } + + Mutex (SIOM, 0x00) + + Method (READ, 3) + { + Acquire (SIOM, 0xffff) + If (LEqual(Arg0, 0)) { + Store (0x55, INDX) + Store (Arg1, INDX) + Store (DATA, Local1) + Store (0xaa, INDX) + } + And (Local1, Arg2, Local1) + Release(SIOM) + Return(Local1) + } + + Method (WRIT, 3) + { + Acquire (SIOM, 0xffff) + If (LEqual(Arg0, 0)) { + Store (0x55, INDX) + Store (Arg1, INDX) + Store (Arg2, DATA) + Store (0xaa, INDX) + } + Release(SIOM) + } + + Device (COMA) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + Name(_PRW, Package() { 0x08, 0x03 }) + + /* Device Status */ + Method (_STA, 0) + { + // Device disabled by coreboot? + If (LEqual(CMAP, 0)) { + Return (0) + } + + // Is the hardware enabled? + Store (READ(0, 0x24, 0xff), Local0) + If (LEqual(Local0, 0)) { + Return (0xd) + } Else { + // Power Enabled? + Store (READ(0, 0x02, 0x08), Local0) + If (LEqual(Local0, 0)) { + Return (0x0d) + } Else { + Return (0x0f) + } + } + } + + /* Device Disable */ + Method (_DIS, 0) + { + WRIT(0, 0x24, 0x00) + + Store(READ(0, 0x28, 0x0f), Local0) + WRIT(0, 0x28, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Not(0x08, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + + /* Possible Resource Settings */ + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + /* Current Resource Settings */ + Method(_CRS, 0) + { + Name(NONE, ResourceTemplate() { + IO(Decode16, 0x000, 0x000, 0x0, 0x1) + IRQNoFlags() { } + }) + + Name(RSRC, ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8, _IOA) + IRQNoFlags(_IRA) { 4 } + }) + + And (_STA(), 0x02, Local0) + If (LEqual(Local0, 0)) { + Return(NONE) + } + + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MIN, IOMN) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MAX, IOMX) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ) + + /* I/O Base */ + Store (READ(0, 0x24, 0xfe), Local0) + ShiftLeft(Local0, 0x02, Local0) + Store(Local0, IOMN) + Store(Local0, IOMX) + + /* Interrupt */ + Store(READ(0, 0x28, 0xf0), Local0) + ShiftRight(Local0, 4, Local0) + ShiftLeft(1, Local0, IRQ) + Return(RSRC) + } + + /* Set Resource Settings */ + Method(_SRS, 1) + { + CreateByteField(Arg0, 0x02, IOLO) + CreateByteField(Arg0, 0x03, IOHI) + CreateByteField(Arg0, 0x09, IRQL) + + WRIT(0, 0x24, 0) + FindSetRightBit(IRQL, Local0) + Decrement(Local0) + ShiftLeft(Local0, 4, Local0) + + Store(READ(0, 0x28, 0x0f), Local1) + Or(Local0, Local1, Local0) + WRIT(0, 0x28, Local0) + + Store(IOLO, Local0) + ShiftRight(Local0, 2, Local0) + And(Local0, 0xfe, Local0) + + Store(IOHI, Local1) + ShiftLeft(Local1, 6, Local1) + Or (Local0, Local1, Local0) + WRIT(0, 0x24, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x08, Local0) + WRIT(0, 0x02, Local0) + + Store(READ(0, 0x07, 0xff), Local0) + Not(0x40, Local1) + And (Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + + /* D0 state - Line drivers are on */ + Method (_PS0, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x08, Local0) + WRIT(0, 0x02, Local0) + + Store (READ(0, 0x07, 0xff), Local0) + Not(0x40, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D3 State - Line drivers are off */ + Method(_PS3, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Not(0x08, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + } + + Device (COMB) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + Name(_PRW, Package() { 0x08, 0x03 }) + + /* Device Status */ + Method (_STA, 0) + { + // Device disabled by coreboot? + If (LEqual(CMBP, 0)) { + Return (0) + } + + /* IRDA? */ + Store(READ(0, 0x0c, 0x38), Local0) + If (LNotEqual(Local0, Zero)) { + Return (0) + } + + // Is the hardware enabled? + Store (READ(0, 0x25, 0xff), Local0) + If (LEqual(Local0, 0)) { + Return (0xd) + } Else { + // Power Enabled? + Store (READ(0, 0x02, 0x80), Local0) + If (LEqual(Local0, 0)) { + Return (0x0d) + } Else { + Return (0x0f) + } + } + } + + /* Device Disable */ + Method (_DIS, 0) + { + WRIT(0, 0x25, 0x00) + + Store(READ(0, 0x28, 0xf0), Local0) + WRIT(0, 0x28, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Not(0x80, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + + /* Possible Resource Settings */ + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + + /* Current Resource Settings */ + Method(_CRS, 0) + { + Name(NONE, ResourceTemplate() { + IO(Decode16, 0x000, 0x000, 0x0, 0x1) + IRQNoFlags() { } + }) + + Name(RSRC, ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8, _IOB) + IRQNoFlags(_IRB) { 3 } + }) + + And (_STA(), 0x02, Local0) + If (LEqual(Local0, 0)) { + Return(NONE) + } + + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MIN, IOMN) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MAX, IOMX) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ) + + /* I/O Base */ + Store (READ(0, 0x25, 0xfe), Local0) + ShiftLeft(Local0, 0x02, Local0) + Store(Local0, IOMN) + Store(Local0, IOMX) + + /* Interrupt */ + Store(READ(0, 0x28, 0x0f), Local0) + ShiftLeft(1, Local0, IRQ) + Return(RSRC) + } + + /* Set Resource Settings */ + Method(_SRS, 1) + { + CreateByteField(Arg0, 0x02, IOLO) + CreateByteField(Arg0, 0x03, IOHI) + CreateByteField(Arg0, 0x09, IRQL) + + WRIT(0, 0x25, 0) + FindSetRightBit(IRQL, Local0) + Decrement(Local0) + + Store(READ(0, 0x28, 0xf0), Local1) + Or(Local0, Local1, Local0) + WRIT(0, 0x28, Local0) + + Store(IOLO, Local0) + ShiftRight(Local0, 2, Local0) + And(Local0, 0xfe, Local0) + + Store(IOHI, Local1) + ShiftLeft(Local1, 6, Local1) + Or (Local0, Local1, Local0) + WRIT(0, 0x25, Local0) + + Store(READ(0, 0x0c, 0xff), Local0) + Not(0x38, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x0c, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x80, Local0) + WRIT(0, 0x02, Local0) + + Store(READ(0, 0x07, 0xff), Local0) + Not(0x20, Local1) + And (Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D0 state - Line drivers are on */ + Method (_PS0, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x80, Local0) + WRIT(0, 0x02, Local0) + + Store (READ(0, 0x07, 0xff), Local0) + Not(0x20, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D3 State - Line drivers are off */ + Method(_PS3, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Not(0x80, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + } +} + diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl new file mode 100644 index 0000000..4cd8882 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + /* degree Celcius to deci-Kelvin (ACPI temperature unit) */ + Method(C2dK, 1) { + Add (2732, Multiply (Arg0, 10), Local0) + Return (Local0) + } + + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x96) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (C2dK(120)) // Value for Rocky + } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (C2dK(155)) // Value for Rocky + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (C2dK(105)) // Value for Rocky + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + If (\_SB.PCI0.LPCB.EC0.ALRC) { + Store(0, \_SB.PCI0.LPCB.EC0.ALRC) + Return(_AC0()) + } + + If (\_SB.PCI0.LPCB.EC0.ALRL) { + Store(0, THRO) + Store(0, \_SB.PCI0.LPCB.EC0.ALRL) + } + + If (\_SB.PCI0.LPCB.EC0.ALRH) { + Store(1, THRO) + Store(0, \_SB.PCI0.LPCB.EC0.ALRH) + } + + /* vendor BIOS reports 0K if TCPU >= 128 deg C ?!? */ + Return (C2dK(\_SB.PCI0.LPCB.EC0.TCPU)) + } + + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU0, \_PR.CPU1}) + } + Return (Package() {\_PR.CPU0}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} + diff --git a/src/mainboard/roda/rk9/acpi/video.asl b/src/mainboard/roda/rk9/acpi/video.asl new file mode 100644 index 0000000..507a390 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/video.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c new file mode 100644 index 0000000..6e6cd72 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -0,0 +1,313 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include "southbridge/intel/i82801ix/nvs.h" +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 0; /* Will use default of 0x00000400. */ + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +static void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ +#define HPET_ADDR 0xfed00000ULL + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = HPET_ADDR & 0xffffffff; + addr->addrh = HPET_ADDR >> 32; + + hpet->id = 0x8086a201; /* Intel */ + hpet->number = 0x00; + hpet->min_tick = 0x0080; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_IOMMU + acpi_dmar_t *dmar; +#endif +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + void *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + +#if CONFIG_IOMMU + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + dmar = (acpi_dmar_t *) current; + acpi_create_dmar(dmar); + current += dmar->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, dmar); +#endif + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + /* Fix up global NVS region for SMI handler. The GNVS region lives + * in the (high) table area. The low memory map looks like this: + * + * 0x00000000 - 0x000003ff Real Mode IVT + * 0x00000020 - 0x0000019c Low MP Table (XXX conflict?) + * 0x00000400 - 0x000004ff BDA (somewhat unused) + * 0x00000500 - 0x0000052f Moved GDT + * 0x00000530 - 0x00000b64 coreboot table + * 0x0007c000 - 0x0007dfff OS boot sector (unused?) + * 0x0007e000 - 0x0007ffff free to use (so no good for acpi+smi) + * 0x00080000 - 0x0009fbff usable ram + * 0x0009fc00 - 0x0009ffff EBDA (unused?) + * 0x000a0000 - 0x000bffff VGA memory + * 0x000c0000 - 0x000cffff VGA option rom + * 0x000d0000 - 0x000dffff free for other option roms? + * 0x000e0000 - 0x000fffff SeaBIOS? (conflict with low tables:) + * 0x000f0000 - 0x000f03ff PIRQ table + * 0x000f0400 - 0x000f66?? ACPI tables + * 0x000f66?? - 0x000f???? DMI tables + */ + + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* Keep pointer around */ + gnvs = (void *)current; + + current += 0x100; + ALIGN_CURRENT; + +#if CONFIG_HAVE_SMI_HANDLER + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); +#endif + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + + return current; +} diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout new file mode 100644 index 0000000..5c82567 --- /dev/null +++ b/src/mainboard/roda/rk9/cmos.layout @@ -0,0 +1,141 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# 2012 secunet Security Networks AG +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#400 8 r 0 unused + +# coreboot config options: southbridge +#408 8 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +#937 7 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 unused + +# ram initialization internal data +1024 128 r 0 read_training_results + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + diff --git a/src/mainboard/roda/rk9/cstates.c b/src/mainboard/roda/rk9/cstates.c new file mode 100644 index 0000000..ab0de76 --- /dev/null +++ b/src/mainboard/roda/rk9/cstates.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpigen.h> +#include <device/device.h> /* fix for i82801ix.h */ +#include <southbridge/intel/i82801ix/i82801ix.h> + +static acpi_cstate_t cst_entries[] = { + { + /* acpi C1 / cpu C1 */ + 1, 0x01, 1000, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } + }, + { + /* acpi C2 / cpu C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } + }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb new file mode 100644 index 0000000..002f595 --- /dev/null +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -0,0 +1,152 @@ +chip northbridge/intel/gm45 + device lapic_cluster 0 on + chip cpu/intel/socket_BGA956 + device lapic 0 on end + end + chip cpu/intel/model_1067x + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Enable Super LFM + register "slfm" = "1" + + # Enable C5, C6 + register "c5" = "1" + register "c6" = "1" + end + end + + device pci_domain 0 on + subsystemid 0x4352 0x8986 + device pci 00.0 on end # host bridge + device pci 02.0 on # VGA + ioapic_irq 2 INTA 0x10 + end + device pci 02.1 on end # Display + device pci 03.0 off end # ME + device pci 03.1 off end # ME + device pci 03.2 off end # ME + device pci 03.3 off end # ME + chip southbridge/intel/i82801ix + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + register "gpi8_routing" = "2" + register "gpi7_routing" = "2" + register "gpe0_en" = "0x01800042" + register "gpi1_routing" = "1" + register "alt_gp_smi_en" = "0x0002" + + # Set AHCI mode, enable ports 1 and 2. + register "sata_ahci" = "1" + register "sata_port_map" = "0x03" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Set c-state support + register "c4onc3_enable" = "0" + register "c5_enable" = "1" + register "c6_enable" = "1" + + # Set thermal throttling to 75%. + register "throttle_duty" = "THTL_75_0" + + # Enable PCIe ports 1 and 5 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0x11" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }" + + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "0xfec00000" + device ioapic 2 on end + end + + device pci 19.0 off end # LAN + device pci 1a.0 on # UHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1a.1 on # UHCI + ioapic_irq 2 INTB 0x11 + end + device pci 1a.2 on # UHCI + ioapic_irq 2 INTC 0x12 + end + device pci 1a.7 on # EHCI + ioapic_irq 2 INTC 0x12 + end + device pci 1b.0 on # HD Audio + ioapic_irq 2 INTA 0x10 + end + device pci 1c.0 on # PCIe Port #1 + ioapic_irq 2 INTA 0x10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + ioapic_irq 2 INTA 0x10 + device pci 00.0 on end # Realtek 8168B + end + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on # UHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1d.1 on # UHCI + ioapic_irq 2 INTB 0x11 + end + device pci 1d.2 on # UHCI + ioapic_irq 2 INTC 0x12 + end + device pci 1d.7 on # EHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1e.0 on # PCI + device pci 03.0 on # TI Cardbus + ioapic_irq 2 INTA 0x10 + end + device pci 03.1 on # TI Cardbus + ioapic_irq 2 INTB 0x11 + end + device pci 03.2 off end # TI FireWire OHC + device pci 03.3 off end # unconnected FlashMedia + device pci 03.4 off end # unconnected SD-Card + end + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47n227 + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # Keyboard+Mouse + end + end + end + device pci 1f.2 on # SATA/IDE 1 + ioapic_irq 2 INTB 0x11 + end + device pci 1f.3 on # SMBus + ioapic_irq 2 INTC 0x12 + end + device pci 1f.5 off end # SATA/IDE 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl new file mode 100644 index 0000000..a240b17 --- /dev/null +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801ix/acpi/globalnvs.asl> + + // General Purpose Events + #include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + // Thermal Zone + #include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/gm45/acpi/gm45.asl> + #include <southbridge/intel/i82801ix/acpi/ich9.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801ix/acpi/sleepstates.asl> +} diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c new file mode 100644 index 0000000..fef9721 --- /dev/null +++ b/src/mainboard/roda/rk9/fadt.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 0x39; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0x00; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 0x06; + + fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */ + fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */ + /* then FIRMWARE_CTRL must be zero. */ + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 0; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 0; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 0; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/roda/rk9/hda_verb.h b/src/mainboard/roda/rk9/hda_verb.h new file mode 100644 index 0000000..f99d097 --- /dev/null +++ b/src/mainboard/roda/rk9/hda_verb.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define PIN_CFG(pin, val) \ + (pin << 20) | ( 0x71c << 8) | (val & 0xff), \ + (pin << 20) | ( 0x71d << 8) | ((val >> 8) & 0xff), \ + (pin << 20) | ( 0x71e << 8) | ((val >> 16) & 0xff), \ + (pin << 20) | ( 0x71f << 8) | ((val >> 24) & 0xff), \ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x43528986, // Subsystem ID + 0x0000000c, // Number of entries + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x11), S/PDIF-OUT2: not connected */ + PIN_CFG(0x11, 0x411111f0) + /* Pin Complex (NID 0x14), LINE_OUT (port D): Speakers */ + PIN_CFG(0x14, 0x99130110) + /* Pin Complex (NID 0x15), HP_OUT (port A): Head phones */ + PIN_CFG(0x15, 0x0121411f) + /* Pin Complex (NID 0x16), MONO-OUT: not connected */ + PIN_CFG(0x16, 0x411111f0) + /* Pin Complex (NID 0x18), MIC1 (port B): Microphone */ + PIN_CFG(0x18, 0x01a19920) + /* Pin Complex (NID 0x19), MIC2 (port F): not connected */ + PIN_CFG(0x19, 0x411111f0) + /* Pin Complex (NID 0x1a), LINE1 (port C): Line-In */ + PIN_CFG(0x1a, 0x01813121) + /* Pin Complex (NID 0x1b), LINE2 (port E): MDC */ + PIN_CFG(0x1b, 0x9983012f) + /* Pin Complex (NID 0x1c), CD_IN */ + PIN_CFG(0x1c, 0x593301f0) + /* Pin Complex (NID 0x1d), PCBEEP */ + PIN_CFG(0x1d, 0x4014022d) + /* Pin Complex (NID 0x1e), S/PDIF-OUT: not connected */ + PIN_CFG(0x1e, 0x411111f0) + /* Pin Complex (NID 0x1f), S/PDIF-IN: not connected */ + PIN_CFG(0x1f, 0x411111f0) +}; +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; + +static const u32 mainboard_pc_beep_verbs[] = { + 0x00170500, /* power up codec */ + 0x01470500, /* power up speakers */ + 0x01470100, /* select lout1 (input 0x0) for speakers */ + 0x01470740, /* enable speakers output */ + 0x00b37517, /* unmute beep (mixer's input 0x5), set amp 0dB */ + 0x00c37100, /* unmute mixer in lout1 (lout1 input 0x1) */ + 0x00c3b015, /* set lout1 output volume -15dB */ + 0x0143b000, /* unmute speakers */ +}; +extern const u32 * pc_beep_verbs; +extern u32 pc_beep_verbs_size; diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c new file mode 100644 index 0000000..5b4285c --- /dev/null +++ b/src/mainboard/roda/rk9/mainboard.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <arch/io.h> +//#include <pc80/mc146818rtc.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include <x86emu/x86emu.h> +#endif +#include <pc80/keyboard.h> +#include <ec/acpi/ec.h> +#include "hda_verb.h" + +#if CONFIG_GENERATE_ACPI_TABLES +#include "cstates.c" /* Include it, as the linker won't find + the overloaded weak function in there. */ +#endif + + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +static int int15_handler(void) +{ + enum { + BOOT_DISPLAY_DEFAULT = 0, + BOOT_DISPLAY_CRT = (1 << 0), + BOOT_DISPLAY_TV = (1 << 1), + BOOT_DISPLAY_EFP = (1 << 2), + BOOT_DISPLAY_LFP = (1 << 3), + BOOT_DISPLAY_CRT2 = (1 << 4), + BOOT_DISPLAY_TV2 = (1 << 5), + BOOT_DISPLAY_EFP2 = (1 << 6), + BOOT_DISPLAY_LFP2 = (1 << 7), + }; + enum { + PANEL_FIT_DEFAULT = 0, + PANEL_FIT_CENTERING = (1 << 0), + PANEL_FIT_TXT_STRETCH = (1 << 1), + PANEL_FIT_GFX_STRETCH = (1 << 2), + }; + + switch (M.x86.R_AX) { + case 0x5f34: + /* Set Panel Fitting Hook */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = PANEL_FIT_CENTERING; + break; + case 0x5f35: + /* Boot Display Device Hook */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = BOOT_DISPLAY_DEFAULT; /* Select automatically. */ + break; + case 0x5f40: + /* Boot Panel Type Hook */ + /* Contrary to what EMGD's user's guide says, + this _alters_ the behavior of the Video BIOS. */ + /* LCD panel type is SIO GPIO40-43. + It's controlled by a DIP switch but was always + set to 4 while only values of 5 and 6 worked. */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = (inb(0x60f) & 0x0f) + 1; + break; + case 0x5f70: + /* Sandybridge boards return 0 here. */ + case 0x5f14: + case 0x5f21: + case 0x5f22: + case 0x5f49: + /* No documentation found. */ + default: + /* Interrupt was not handled. */ + printk(BIOS_DEBUG, + "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", __func__, + M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + return 0; + } + + /* Interrupt handled. */ + return 1; +} + +static void int15_install(void) +{ + typedef int (* yabel_handleIntFunc)(void); + extern yabel_handleIntFunc yabel_intFuncArray[256]; + yabel_intFuncArray[0x15] = int15_handler; +} +#endif + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); +} + +static void ec_setup(void) +{ + /* Thermal limits? Values are from ectool's ram dump. */ + ec_write(0xd1, 0x57); /* CPUH */ + ec_write(0xd2, 0xc9); /* CPUL */ + ec_write(0xd4, 0x64); /* SYSH */ + ec_write(0xd5, 0xc9); /* SYSL */ + + send_ec_command(0x04); /* Set_SMI_Enable */ + send_ec_command(0xab); /* Set_ACPI_Disable */ + send_ec_command(0xac); /* Clr_SYS_Flag? well, why not? */ + send_ec_command(0xad); /* Set_Thml_Value */ +} + +static void mainboard_enable(device_t dev) +{ + ec_setup(); + verb_setup(); +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL// || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + /* Install custom int15 handler for VGA OPROM */ + int15_install(); +#endif + + /* We have no driver for the embedded controller since the firmware + does most of the job. Hence, initialize keyboards here. */ + pc_keyboard_init(NULL); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/roda/rk9/mainboard_smi.c b/src/mainboard/roda/rk9/mainboard_smi.c new file mode 100644 index 0000000..8a87cd9 --- /dev/null +++ b/src/mainboard/roda/rk9/mainboard_smi.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801ix/nvs.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <ec/acpi/ec.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + gnvs->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +void mainboard_smi_gpi(u16 gpi_sts) +{ + if (gpi_sts & (1 << 1)) { + printk(BIOS_DEBUG, "EC/SMI\n"); + /* TODO */ + } +} + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + send_ec_command(0x05); /* Set_SMI_Disable */ + send_ec_command(0xaa); /* Set_ACPI_Enable */ + break; + + case APM_CNT_ACPI_DISABLE: + send_ec_command(0x04); /* Set_SMI_Enable */ + send_ec_command(0xab); /* Set_ACPI_Disable */ + break; + } + return 0; +} diff --git a/src/mainboard/roda/rk9/mptable.c b/src/mainboard/roda/rk9/mptable.c new file mode 100644 index 0000000..f1839f0 --- /dev/null +++ b/src/mainboard/roda/rk9/mptable.c @@ -0,0 +1 @@ +/* dummy file */ diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c new file mode 100644 index 0000000..c6ca078 --- /dev/null +++ b/src/mainboard/roda/rk9/romstage.c @@ -0,0 +1,211 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cbmem.h> +#include <lib.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <northbridge/intel/gm45/gm45.h> +#include <superio/smsc/lpc47n227/early_serial.c> + +#define LPC_DEV PCI_DEV(0, 0x1f, 0) +#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1) + +static void default_southbridge_gpio_setup(void) +{ + /* Enable GPIOs [31:0]. */ + outl(0x197e7dfe, DEFAULT_GPIOBASE + 0x00); + /* Set input/output mode [31:0] (0 == out, 1 == in). */ + outl(0xe0ea43fe, DEFAULT_GPIOBASE + 0x04); + /* Set gpio levels [31:0]. orig: 0x01140800 (~SATA0, ~SATA1, GSM, BT, + WLAN, ~ANTMUX, ~GPIO12, + ~SUSPWR, SMBALERT) */ + outl(0x00000800, DEFAULT_GPIOBASE + 0x0c); + + /* Disable blink [31:0]. */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); + /* Set input inversion [31:0]. */ + outl(0x00000182, DEFAULT_GPIOBASE + 0x2c); + + /* Enable GPIOs [60:32]. */ + outl(0x130300fe, DEFAULT_GPIOBASE + 0x30); + /* Set input/output mode [60:32] (0 == out, 1 == in). */ + outl(0x0e55ffb0, DEFAULT_GPIOBASE + 0x34); + /* Set gpio levels [60:32]. orig: 0x10020046 (LNKALERT, ~ATAIO, + DMITERM, TXT, ~CLKSATA, + GPS, AUDIO) */ + outl(0x10020042, DEFAULT_GPIOBASE + 0x38); +} + +static void early_lpc_setup(void) +{ + /* Set up SuperIO LPC forwards */ + + /* Configure serial IRQs.*/ + pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0); + /* Map COMa on 0x3f8, COMb on 0x2f8. */ + pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); + /* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */ + pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03); +} + +static void default_superio_gpio_setup(void) +{ + /* Original settings: + idx 30 31 32 33 34 35 36 37 38 39 + val 60 00 00 40 00 ff 00 e0 00 80 + def 00 00 00 00 00 00 00 00 00 80 + + Values: + GP1 GP2 GP3 GP4 + fd 17 88 14 + */ + const device_t sio = PNP_DEV(0x2e, 0); + + /* Enter super-io's configuration state. */ + pnp_enter_conf_state(sio); + + /* Set lpc47n227's runtime register block's base address. */ + pnp_write_config(sio, 0x30, 0x600 >> 4); + + /* Set GP23 to alternate function. */ + pnp_write_config(sio, 0x33, 0x40); + + /* Set GP30 - GP37 to output mode: COM control */ + pnp_write_config(sio, 0x35, 0xff); + + /* Set GP45 - GP47 to output mode. */ + pnp_write_config(sio, 0x37, 0xe0); + + /* Set nIO_PME to open drain. */ + pnp_write_config(sio, 0x39, 0x80); + + /* Exit configuration state. */ + pnp_exit_conf_state(sio); + + + /* Enable decoding of 0x600-0x60f through lpc. */ + pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601); + + /* Set GPIO output values: */ + outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */ + outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ +} + +void main(unsigned long bist) +{ + sysinfo_t sysinfo; + int s3resume = 0; + u16 reg16; + + /* basic northbridge setup, including MMCONF BAR */ + gm45_early_init(); + + if (bist == 0) + enable_lapic(); + + /* First, run everything needed for console output. */ + i82801ix_early_init(); + early_lpc_setup(); + default_superio_gpio_setup(); + lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist); + + reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); + pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); + if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + gm45_early_reset(); + } + + default_southbridge_gpio_setup(); + + /* ASPM related setting, set early by original BIOS. */ + DMIBAR16(0x204) &= ~(3 << 10); + + /* Check for S3 resume. */ + const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); + if (((pm1_cnt >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + /* RAM initialization */ + enter_raminit_or_reset(); + get_gmch_info(&sysinfo); + raminit(&sysinfo, s3resume); + + raminit_thermal(&sysinfo); + init_igd(&sysinfo, 0, 1); /* Enable IGD, disable PEG. */ + init_pm(&sysinfo); + + i82801ix_dmi_setup(); + gm45_late_init(sysinfo.stepping); + i82801ix_dmi_poll_vc1(); + + MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; + + init_iommu(); + +#if CONFIG_HAVE_ACPI_RESUME + /* Start address of high memory tables */ + unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if (s3resume && cbmem_reinit((u64)high_ram_base)) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); + } +#endif + printk(BIOS_SPEW, "exit main()\n"); +} + diff --git a/src/mainboard/roda/rk9/ti_pci7xx1.c b/src/mainboard/roda/rk9/ti_pci7xx1.c new file mode 100644 index 0000000..8acc90f --- /dev/null +++ b/src/mainboard/roda/rk9/ti_pci7xx1.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/cardbus.h> + +static void pci7xx1_enable(struct device *const dev) +{ + printk(BIOS_DEBUG, "%s: TI PCI7xx1 media controller\n", __func__); + if (PCI_FUNC(dev->path.pci.devfn) == 0) { + const uint16_t secondary = dev->bus->secondary; + const unsigned slot = PCI_SLOT(dev->path.pci.devfn); + + int fn; + + /* Hide functions based on devicetree info. */ + u16 gcr = pci_read_config16(dev, 0x86); + for (fn = 5; fn > 0; --fn) { + const struct device *const d = + dev_find_slot(secondary, PCI_DEVFN(slot, fn)); + if (!d || d->enabled) continue; + printk(BIOS_DEBUG, + "%s: Hiding function #%d.\n", __func__, fn); + switch (fn) { + case 1: gcr |= 1 << 4; break; /* CardBus B */ + case 2: gcr |= 1 << 3; break; /* OHCI 1394 */ + case 3: gcr |= 1 << 5; break; /* Flash media */ + case 4: gcr |= 1 << 6; break; /* SD card */ + case 5: gcr |= 1 << 7; break; /* Smart Card */ + } + } + pci_write_config16(dev, 0x86, gcr); + } +} + +static struct device_operations device_ops = { + .read_resources = cardbus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = cardbus_enable_resources, + .init = 0, + .scan_bus = pci_scan_bridge, + .enable = pci7xx1_enable, + .reset_bus = pci_bus_reset, +}; + +static const struct pci_driver ti_pci7xx1 __pci_driver = { + .ops = &device_ops, + .vendor = 0x104c, + .device = 0x8031, +}; +

1 0

Patch set updated for coreboot: 857b67a roda/rk9: New mainboard
by Nico Huber 16 Nov '12

16 Nov '12

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1691 -gerrit commit 857b67a4ba8fd2acaa2313ea67c6edb1ce0588ba Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 6 11:05:38 2012 +0100 roda/rk9: New mainboard Roda RK9 is a notebook based on the GM45/ICH9 platform using DDR3 memory. Change-Id: I7299dccbff2eea3544363fdd4f49f05aa3dae7bc Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/mainboard/roda/Kconfig | 4 + src/mainboard/roda/rk9/Kconfig | 46 ++++ src/mainboard/roda/rk9/Makefile.inc | 21 ++ src/mainboard/roda/rk9/acpi/battery.asl | 232 ++++++++++++++++ src/mainboard/roda/rk9/acpi/ec.asl | 197 ++++++++++++++ src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl | 86 ++++++ src/mainboard/roda/rk9/acpi/gpe.asl | 120 +++++++++ src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl | 110 ++++++++ src/mainboard/roda/rk9/acpi/mainboard.asl | 44 +++ src/mainboard/roda/rk9/acpi/platform.asl | 209 +++++++++++++++ src/mainboard/roda/rk9/acpi/superio.asl | 368 ++++++++++++++++++++++++++ src/mainboard/roda/rk9/acpi/thermal.asl | 115 ++++++++ src/mainboard/roda/rk9/acpi/video.asl | 45 ++++ src/mainboard/roda/rk9/acpi_tables.c | 313 ++++++++++++++++++++++ src/mainboard/roda/rk9/cmos.layout | 141 ++++++++++ src/mainboard/roda/rk9/cstates.c | 41 +++ src/mainboard/roda/rk9/devicetree.cb | 152 +++++++++++ src/mainboard/roda/rk9/dsdt.asl | 56 ++++ src/mainboard/roda/rk9/fadt.c | 158 +++++++++++ src/mainboard/roda/rk9/hda_verb.h | 74 ++++++ src/mainboard/roda/rk9/mainboard.c | 147 ++++++++++ src/mainboard/roda/rk9/mainboard_smi.c | 76 ++++++ src/mainboard/roda/rk9/mptable.c | 1 + src/mainboard/roda/rk9/romstage.c | 211 +++++++++++++++ src/mainboard/roda/rk9/ti_pci7xx1.c | 71 +++++ 25 files changed, 3038 insertions(+) diff --git a/src/mainboard/roda/Kconfig b/src/mainboard/roda/Kconfig index ba4b6ec..b70ce33 100644 --- a/src/mainboard/roda/Kconfig +++ b/src/mainboard/roda/Kconfig @@ -6,9 +6,13 @@ choice config BOARD_RODA_RK886EX bool "RK886EX" +config BOARD_RODA_RK9 + bool "RK9" + endchoice source "src/mainboard/roda/rk886ex/Kconfig" +source "src/mainboard/roda/rk9/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig new file mode 100644 index 0000000..dd9e940 --- /dev/null +++ b/src/mainboard/roda/rk9/Kconfig @@ -0,0 +1,46 @@ +if BOARD_RODA_RK9 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_BGA956 + select NORTHBRIDGE_INTEL_GM45 + select SOUTHBRIDGE_INTEL_I82801IX + select SUPERIO_SMSC_LPC47N227 + select MMCONF_SUPPORT + select BOARD_ROMSIZE_KB_4096 + select RTL8168_ROM_DISABLE + select DRIVERS_GENERIC_IOAPIC + select HAVE_MP_TABLE + select CARDBUS_PLUGIN_SUPPORT + select BOARD_HAS_FADT + select HAVE_ACPI_TABLES + #select HAVE_ACPI_RESUME + select EC_ACPI + select HAVE_OPTION_TABLE + +config MAINBOARD_DIR + string + default roda/rk9 + +config MAINBOARD_PART_NUMBER + string + default "RK9" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +endif # BOARD_RODA_RK9 diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc new file mode 100644 index 0000000..27feaab --- /dev/null +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 secunet Security Networks AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/roda/rk9/acpi/battery.asl b/src/mainboard/roda/rk9/acpi/battery.asl new file mode 100644 index 0000000..3eb9b14 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/battery.asl @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Name(\CBA1, 0x60) +Name(\CBA2, 0x60) + +/* ACPI doesn't care if capacity is given in mWh or mAh, + but it has to be consistent */ + +Device (BAT1) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 1) + + Name(_PCL, Package(){ _SB }) + Name(PSTA, 0x1f) + + /* battery information */ + Name(PBIF, Package() { + 0x01, // power unit + 0x01, // design capacity (mWh/mAh), updated by UPBI + 0x01, // last full charge capacity (mWh/mAh), updated by UPBI + 0x01, // battery technology: "rechargeable" + 0x01, // design voltage (mV), updated by UPBI + 0x0294, // design capacity of warning (mWh/mAh) + 0x014a, // design capacity of low (mWh/mAh) + 0x42, // battery capacity granularity between low and warning + 0x42, // battery capacity granularity between warning and full + "BAT1", // Name + "001 ", // Number + "LION", // Type + "JSE" // Vendor + }) + /* battery status */ + /* dummy values, filled in by UPBS */ + Name(PBST, Package() { + 0x00, // battery state + // bit0: discharging + // bit1: charging + // bit2: critical energy state + 0x01, // battery present rate (mW/mA) + 0x01, // remaining capacity (mW/mA) + 0x01 // battery present voltage (mV) + }) + + /* Status */ + Method(_STA, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + If(\_SB.PCI0.LPCB.EC0.B1PR) { + If(\_SB.PCI0.LPCB.EC0.B1CH) { + Return(0x1f) + } + } + } + Return(0x0f) + } + + /* Battery Info */ + Method(_BIF, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B1DW, Index(PBIF, 1)) + Store (\_SB.PCI0.LPCB.EC0.B1FW, Index(PBIF, 2)) + Store (\_SB.PCI0.LPCB.EC0.B1DV, Index(PBIF, 4)) + } + + Return(PBIF) + } + + /* Battery Status */ + Method(_BST, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B1PW, Local0) + If (LGreaterEqual (Local0, 0x8000)) { + Subtract (0x10000, Local0, Local0) + } + Store (Local0, Index(PBST, 1)) + Store (\_SB.PCI0.LPCB.EC0.B1PV, Index(PBST, 3)) + + Store (\_SB.PCI0.LPCB.EC0.B1RW, Index(PBST, 2)) + + If (\_SB.PCI0.LPCB.EC0.ACCH) { + If (\_SB.PCI0.LPCB.EC0.B1CH) { + If (\_SB.PCI0.LPCB.EC0.B1CG) { + Store (2, Index(PBST, 0)) + } + } + } Else { + If (\_SB.PCI0.LPCB.EC0.B1LO) { + Store (5, Index(PBST, 0)) + } Else { + Store (1, Index(PBST, 0)) + } + } + } + + Return(PBST) + } + +} + +Device (BAT2) +{ + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 2) + + Name(_PCL, Package(){ _SB }) + Name(PSTA, 0x1f) + + /* battery information */ + Name(PBIF, Package() { + 0x01, // power unit + 0x01, // design capacity (mWh/mAh), updated by UPBI + 0x01, // last full charge capacity (mWh/mAh), updated by UPBI + 0x01, // battery technology: "rechargeable" + 0x01, // design voltage (mV), updated by UPBI + 0x0294, // design capacity of warning (mWh/mAh) + 0x014a, // design capacity of low (mWh/mAh) + 0x42, // battery capacity granularity between low and warning + 0x42, // battery capacity granularity between warning and full + "BAT1", // Name + "002 ", // Number + "LION", // Type + "JSE" // Vendor + }) + /* battery status */ + /* dummy values, filled in by UPBS */ + Name(PBST, Package() { + 0x00, // battery state + // bit0: discharging + // bit1: charging + // bit2: critical energy state + 0x01, // battery present rate (mW/mA) + 0x01, // remaining capacity (mW/mA) + 0x01 // battery present voltage (mV) + }) + + /* Status */ + Method(_STA, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + If(\_SB.PCI0.LPCB.EC0.B2PR) { + If(\_SB.PCI0.LPCB.EC0.B2CH) { + Return(0x1f) + } + } + } + Return(0x0f) + } + + /* Battery Info */ + Method(_BIF, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B2DW, Index(PBIF, 1)) + Store (\_SB.PCI0.LPCB.EC0.B2FW, Index(PBIF, 2)) + Store (\_SB.PCI0.LPCB.EC0.B2DV, Index(PBIF, 4)) + } + + Return(PBIF) + } + + /* Battery Status */ + Method(_BST, 0) + { + If(\_SB.PCI0.LPCB.EC0.ECON) { + Store (\_SB.PCI0.LPCB.EC0.B2PW, Local0) + If (LGreaterEqual (Local0, 0x8000)) { + Subtract (0x10000, Local0, Local0) + } + Store (Local0, Index(PBST, 1)) + Store (\_SB.PCI0.LPCB.EC0.B2PV, Index(PBST, 3)) + + Store (\_SB.PCI0.LPCB.EC0.B2RW, Index(PBST, 2)) + + If (\_SB.PCI0.LPCB.EC0.ACCH) { + If (\_SB.PCI0.LPCB.EC0.B2CH) { + If (\_SB.PCI0.LPCB.EC0.B2CG) { + Store (2, Index(PBST, 0)) + } + } + } Else { + If (\_SB.PCI0.LPCB.EC0.B2LO) { + Store (5, Index(PBST, 0)) + } Else { + Store (1, Index(PBST, 0)) + } + } + } + + Return(PBST) + } + +} + +Device (ADP1) +{ + Name (_HID, "ACPI0003") + Method (_PSR, 0) + { + Store (\_SB.PCI0.LPCB.EC0.ACCH, PWRS) + Stall (0x02) + Return (PWRS) + } + + Method (_PCL, 0) + { + Return (_SB) + } +} + diff --git a/src/mainboard/roda/rk9/acpi/ec.asl b/src/mainboard/roda/rk9/acpi/ec.asl new file mode 100644 index 0000000..3e6cb98 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/ec.asl @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device(EC0) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 1) + + Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI + Name (ECON, 0) + Name (QEVT, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0xb1), + CPWR, 1, + ACCH, 1, // AC connected (charger present) + B1PR, 1, // battery 1 present + B2PR, 1, // battery 2 present + B1CH, 1, // battery 1 charged + B2CH, 1, // battery 2 charged + Offset(0xb2), + B1CG, 1, // battery 1 charging + B2CG, 1, // battery 2 charging + B1LO, 1, // battery 1 low + B2LO, 1, // battery 2 low + Offset(0xb3), + B1DW, 16, // battery 1 design capacity + B1FW, 16, // battery 1 last full charge capacity + B1DV, 16, // battery 1 design voltage + B1PW, 16, // battery 1 present capacity + Offset(0xbd), + B1PV, 16, // battery 1 present voltage + Offset(0xc1), + B2DW, 16, // battery 2 design capacity + B2FW, 16, // battery 2 last full charge capacity + B2DV, 16, // battery 2 design voltage + B2PW, 16, // battery 2 present capacity + Offset(0xcb), + B2PV, 16, // battery 2 present voltage + Offset(0xcf), + FDDI, 1, // floppy on lpt indicator? + LIDC, 1, // LID switch + Offset(0xd0), + TCPU, 8, // T_CPU in deg Celcius + Offset(0xd6), + /* exact purpose of these three is guessed, + but it's something about cooling */ + ALRL, 1, // active cooling low limit + ALRH, 1, // active cooling high limit + ALRC, 1, // active cooling clear + Offset(0xe8), + B1RW, 16, // battery 1 remaining capacity + B2RW, 16, // battery 2 remaining capacity + } + + Method (_CRS, 0) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 1, 1) + IO (Decode16, 0x66, 0x66, 1, 1) + }) + + Return (ECMD) + } + + Method (_REG, 2) + { + // This method is needed by Windows XP/2000 for + // EC initialization before a driver is loaded + + If (LEqual(Arg0, 0x03)) { + Store (Arg1, ECON) + } + } + + // EC Query methods + + Method (_Q11, 0) + { + Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug) + Notify(SLPB, 0x80) + } + + Method (_Q30, 0) + { + Store("_Q30: AC In", Debug) + Notify(ADP1, 0x80) // Tell the Power Adapter + PNOT() // and the CPU and Battery + } + + Method (_Q31, 0) + { + Store("_Q31: AC Out", Debug) + Notify(ADP1, 0x80) // Tell the Power Adapter + PNOT() // and the CPU and Battery + } + + Method (_Q32, 0) + { + Store("_Q32: Bat1 In", Debug) + Notify(BAT1, 0x81) + } + + Method (_Q33, 0) + { + Store("_Q33: Bat1 Out", Debug) + Notify(BAT1, 0x81) + } + + Method (_Q34, 0) + { + Store("_Q34: Bat2 In", Debug) + Notify(BAT2, 0x81) + } + + Method (_Q35, 0) + { + Store("_Q35: Bat2 Out", Debug) + Notify(BAT2, 0x81) + } + + Method (_Q36, 0) + { + Store("_Q36: Bat1 Low Power", Debug) + Notify(BAT1, 0x80) + } + + Method (_Q37, 0) + { + Store("_Q37: Bat1 Full Charge", Debug) + Notify(BAT1, 0x80) + } + + Method (_Q38, 0) + { + Store("_Q38: Bat2 Low Power", Debug) + Notify(BAT2, 0x80) + } + + Method (_Q39, 0) + { + Store("_Q39: Bat2 Full Charge", Debug) + Notify(BAT2, 0x80) + } + + Method (_Q40, 0) + { + Store("_Q40: LID Open/Close", Debug) + Notify(LID0, 0x80) + } + + Method (_Q41, 0) + { + Store("_Q41: Floppy on Parallel Port: Call the Museum!", Debug) + } + + Method (_Q50, 0) + { + Store("_Q50: Processor is hot", Debug) + Notify(\_TZ.THRM, 0x80) + } + + Method (_Q51, 0) + { + Store("_Q51: Processor is boiling", Debug) + Notify(\_TZ.THRM, 0x80) + } + + Method (_Q52, 0) + { + Store("_Q52: Processor is burning", Debug) + Notify(\_TZ.THRM, 0x80) + } + +} diff --git a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl new file mode 100644 index 0000000..83c7762 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * gm45 + */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 16 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // USB and EHCI 0:1a.x + Package() { 0x001affff, 0, 0, 16 }, + Package() { 0x001affff, 1, 0, 17 }, + Package() { 0x001affff, 2, 0, 18 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 16 }, + Package() { 0x001dffff, 1, 0, 17 }, + Package() { 0x001dffff, 2, 0, 18 }, + // FIXME + // CardBus/IEEE1394 0:1e.2, 0:1e.3 + // Package() { 0x001effff, 0, 0, 22 }, + // Package() { 0x001effff, 1, 0, 20 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 16 }, + Package() { 0x001fffff, 1, 0, 17 }, + Package() { 0x001fffff, 2, 0, 18 } + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // USB and EHCI 0:1a.x + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + // FIXME + // CardBus/IEEE1394 0:1e.2, 0:1e.3 + // Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 } + }) + } +} + diff --git a/src/mainboard/roda/rk9/acpi/gpe.asl b/src/mainboard/roda/rk9/acpi/gpe.asl new file mode 100644 index 0000000..5854006 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/gpe.asl @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (_GPE) +{ + /* The event numbers correspond to the bit numbers in the + * GPE0_EN register PMBASE + 0x28. + */ + /* IMO we don't need empty Methods here. If we don't specify + one and don't set the GPE0_EN bit Linux won't neither enable + it. - Nico */ + + // Thermal Event - original BIOS doesn't have it + Method (_L00, 0) + { + /* FIXME: We should enable throttling here. */ + } + + // Hot Plug + Method (_L01, 0) + { + + } + + // USB1 + Method (_L03, 0) + { + + } + + // USB2 + Method (_L04, 0) + { + + } + + // USB5 + Method (_L05, 0) + { + + } + + // _L06 TCOSCI + + // SMBus Wake Status + Method (_L07, 0) + { + + } + + // COM1/COM2 (RI) + Method (_L08, 0) + { + + } + + // PCIe + Method (_L09, 0) + { + + } + + // _L0A BatLow / Quick Resume + + // PME + Method (_L0B, 0) + { + + } + + // USB3 + Method (_L0C, 0) + { + + } + + // PME B0 + Method (_L0D, 0) + { + + } + + // USB4 + Method (_L0E, 0) + { + + } + + // _L10 - _L1f: GPIn + + // GPI8 + Method (_L18, 0) + { + + } + + // USB6 + Method (_L20, 0) + { + + } +} diff --git a/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl new file mode 100644 index 0000000..325f13c --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/ich9_pci_irqs.asl @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH9 + */ + +/* TODO: which slots are actually relevant? */ +If (PICM) { + Return (Package() { + // PCI Slot 1 routes ABCD + Package() { 0x0000ffff, 0, 0, 16}, + Package() { 0x0000ffff, 1, 0, 17}, + Package() { 0x0000ffff, 2, 0, 18}, + Package() { 0x0000ffff, 3, 0, 19}, + + // PCI Slot 2 routes BCDA + Package() { 0x0001ffff, 0, 0, 17}, + Package() { 0x0001ffff, 1, 0, 18}, + Package() { 0x0001ffff, 2, 0, 19}, + Package() { 0x0001ffff, 3, 0, 16}, + + // PCI Slot 3 routes CDAB + Package() { 0x0002ffff, 0, 0, 18}, + Package() { 0x0002ffff, 1, 0, 19}, + Package() { 0x0002ffff, 2, 0, 16}, + Package() { 0x0002ffff, 3, 0, 17}, + + // PCI Slot 4 routes ABCD + Package() { 0x0003ffff, 0, 0, 16}, + Package() { 0x0003ffff, 1, 0, 17}, + Package() { 0x0003ffff, 2, 0, 18}, + Package() { 0x0003ffff, 3, 0, 19}, + + // PCI Slot 5 routes ABCD + Package() { 0x0004ffff, 0, 0, 16}, + Package() { 0x0004ffff, 1, 0, 17}, + Package() { 0x0004ffff, 2, 0, 18}, + Package() { 0x0004ffff, 3, 0, 19}, + + // PCI Slot 6 routes BCDA + Package() { 0x0005ffff, 0, 0, 17}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 19}, + Package() { 0x0005ffff, 3, 0, 16}, + + // FIXME: what's this supposed to mean? (adopted from ich7) + //Package() { 0x0008ffff, 0, 0, 20}, + }) +} Else { + Return (Package() { + // PCI Slot 1 routes ABCD + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 2 routes BCDA + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + // PCI Slot 3 routes CDAB + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0}, + + // PCI Slot 4 routes ABCD + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 5 routes ABCD + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + // PCI Slot 6 routes BCDA + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + // FIXME + // Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} + diff --git a/src/mainboard/roda/rk9/acpi/mainboard.asl b/src/mainboard/roda/rk9/acpi/mainboard.asl new file mode 100644 index 0000000..0837ed3 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/mainboard.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LID0) +{ + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Return (\_SB.PCI0.LPCB.EC0.LIDC) + } +} + +Device (SLPB) +{ + Name(_HID, EisaId("PNP0C0E")) +} + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x18, 0x04}) +} + +#include "acpi/battery.asl" diff --git a/src/mainboard/roda/rk9/acpi/platform.asl b/src/mainboard/roda/rk9/acpi/platform.asl new file mode 100644 index 0000000..b85433f --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/platform.asl @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* These come from the dynamically created CPU SSDT */ +External(PDC0) +External(PDC1) + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + // TODO: Return Arg0 as second value if S-Arg0 was entered + // before. + + Return(Package(){0,0}) +} + +// Power notification + +External (\_PR_.CPU0, DeviceObj) +External (\_PR_.CPU1, DeviceObj) + +Method (PNOT) +{ + If (MPEN) { + If(And(PDC0, 0x08)) { + Notify (\_PR_.CPU0, 0x80) // _PPC + + If (And(PDC0, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU0, 0x81) // _CST + } + } + + If(And(PDC1, 0x08)) { + Notify (\_PR_.CPU1, 0x80) // _PPC + If (And(PDC1, 0x10)) { + Sleep(100) + Notify(\_PR_.CPU1, 0x81) // _CST + } + } + + } Else { // UP + Notify (\_PR_.CPU0, 0x80) + Sleep(0x64) + Notify(\_PR_.CPU0, 0x81) + } + + // Notify the Batteries + Notify(BAT1, 0x80) // Execute BAT1 _BST + Notify(BAT2, 0x80) // Execute BAT2 _BST +} + +/* System Bus */ + +Scope(\_SB) +{ + /* This method is placed on the top level, so we can make sure it's the + * first executed _INI method. + */ + Method(_INI, 0) + { + /* The DTS data in NVS is probably not up to date. + * Update temperature values and make sure AP thermal + * interrupts can happen + */ + + // TRAP(71) // TODO + + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI, Local0)) { + /* Linux answers _OSI with "True" for a couple of + * Windows version queries. But unlike Windows it + * needs a Video repost, so let's determine whether + * we're running Linux. + */ + + If (_OSI("Linux")) { + Store (1, LINX) + } + + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + } + + /* And the OS workarounds start right after we know what we're + * running: Windows XP SP1 needs to have C-State coordination + * enabled in SMM. + */ + If (LAnd(LEqual(OSYS, 2001), MPEN)) { + // TRAP(61) // TODO + } + + /* SMM power state and C4-on-C3 settings need to be updated */ + // TRAP(43) // TODO + } +} + diff --git a/src/mainboard/roda/rk9/acpi/superio.asl b/src/mainboard/roda/rk9/acpi/superio.asl new file mode 100644 index 0000000..174f2f1 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/superio.asl @@ -0,0 +1,368 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* SMSC LPC47N227 */ + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + OperationRegion(SIOR, SystemIO, 0x2e, 0x02) + Field (SIOR, ByteAcc, Nolock, Preserve) + { + INDX, 8, + DATA, 8 + } + + Mutex (SIOM, 0x00) + + Method (READ, 3) + { + Acquire (SIOM, 0xffff) + If (LEqual(Arg0, 0)) { + Store (0x55, INDX) + Store (Arg1, INDX) + Store (DATA, Local1) + Store (0xaa, INDX) + } + And (Local1, Arg2, Local1) + Release(SIOM) + Return(Local1) + } + + Method (WRIT, 3) + { + Acquire (SIOM, 0xffff) + If (LEqual(Arg0, 0)) { + Store (0x55, INDX) + Store (Arg1, INDX) + Store (Arg2, DATA) + Store (0xaa, INDX) + } + Release(SIOM) + } + + Device (COMA) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + Name(_PRW, Package() { 0x08, 0x03 }) + + /* Device Status */ + Method (_STA, 0) + { + // Device disabled by coreboot? + If (LEqual(CMAP, 0)) { + Return (0) + } + + // Is the hardware enabled? + Store (READ(0, 0x24, 0xff), Local0) + If (LEqual(Local0, 0)) { + Return (0xd) + } Else { + // Power Enabled? + Store (READ(0, 0x02, 0x08), Local0) + If (LEqual(Local0, 0)) { + Return (0x0d) + } Else { + Return (0x0f) + } + } + } + + /* Device Disable */ + Method (_DIS, 0) + { + WRIT(0, 0x24, 0x00) + + Store(READ(0, 0x28, 0x0f), Local0) + WRIT(0, 0x28, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Not(0x08, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + + /* Possible Resource Settings */ + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + /* Current Resource Settings */ + Method(_CRS, 0) + { + Name(NONE, ResourceTemplate() { + IO(Decode16, 0x000, 0x000, 0x0, 0x1) + IRQNoFlags() { } + }) + + Name(RSRC, ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8, _IOA) + IRQNoFlags(_IRA) { 4 } + }) + + And (_STA(), 0x02, Local0) + If (LEqual(Local0, 0)) { + Return(NONE) + } + + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MIN, IOMN) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MAX, IOMX) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ) + + /* I/O Base */ + Store (READ(0, 0x24, 0xfe), Local0) + ShiftLeft(Local0, 0x02, Local0) + Store(Local0, IOMN) + Store(Local0, IOMX) + + /* Interrupt */ + Store(READ(0, 0x28, 0xf0), Local0) + ShiftRight(Local0, 4, Local0) + ShiftLeft(1, Local0, IRQ) + Return(RSRC) + } + + /* Set Resource Settings */ + Method(_SRS, 1) + { + CreateByteField(Arg0, 0x02, IOLO) + CreateByteField(Arg0, 0x03, IOHI) + CreateByteField(Arg0, 0x09, IRQL) + + WRIT(0, 0x24, 0) + FindSetRightBit(IRQL, Local0) + Decrement(Local0) + ShiftLeft(Local0, 4, Local0) + + Store(READ(0, 0x28, 0x0f), Local1) + Or(Local0, Local1, Local0) + WRIT(0, 0x28, Local0) + + Store(IOLO, Local0) + ShiftRight(Local0, 2, Local0) + And(Local0, 0xfe, Local0) + + Store(IOHI, Local1) + ShiftLeft(Local1, 6, Local1) + Or (Local0, Local1, Local0) + WRIT(0, 0x24, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x08, Local0) + WRIT(0, 0x02, Local0) + + Store(READ(0, 0x07, 0xff), Local0) + Not(0x40, Local1) + And (Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + + /* D0 state - Line drivers are on */ + Method (_PS0, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x08, Local0) + WRIT(0, 0x02, Local0) + + Store (READ(0, 0x07, 0xff), Local0) + Not(0x40, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D3 State - Line drivers are off */ + Method(_PS3, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Not(0x08, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + } + + Device (COMB) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + Name(_PRW, Package() { 0x08, 0x03 }) + + /* Device Status */ + Method (_STA, 0) + { + // Device disabled by coreboot? + If (LEqual(CMBP, 0)) { + Return (0) + } + + /* IRDA? */ + Store(READ(0, 0x0c, 0x38), Local0) + If (LNotEqual(Local0, Zero)) { + Return (0) + } + + // Is the hardware enabled? + Store (READ(0, 0x25, 0xff), Local0) + If (LEqual(Local0, 0)) { + Return (0xd) + } Else { + // Power Enabled? + Store (READ(0, 0x02, 0x80), Local0) + If (LEqual(Local0, 0)) { + Return (0x0d) + } Else { + Return (0x0f) + } + } + } + + /* Device Disable */ + Method (_DIS, 0) + { + WRIT(0, 0x25, 0x00) + + Store(READ(0, 0x28, 0xf0), Local0) + WRIT(0, 0x28, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Not(0x80, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + + /* Possible Resource Settings */ + Name(_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + + /* Current Resource Settings */ + Method(_CRS, 0) + { + Name(NONE, ResourceTemplate() { + IO(Decode16, 0x000, 0x000, 0x0, 0x1) + IRQNoFlags() { } + }) + + Name(RSRC, ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8, _IOB) + IRQNoFlags(_IRB) { 3 } + }) + + And (_STA(), 0x02, Local0) + If (LEqual(Local0, 0)) { + Return(NONE) + } + + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MIN, IOMN) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IOA._MAX, IOMX) + CreateWordField(RSRC, + \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ) + + /* I/O Base */ + Store (READ(0, 0x25, 0xfe), Local0) + ShiftLeft(Local0, 0x02, Local0) + Store(Local0, IOMN) + Store(Local0, IOMX) + + /* Interrupt */ + Store(READ(0, 0x28, 0x0f), Local0) + ShiftLeft(1, Local0, IRQ) + Return(RSRC) + } + + /* Set Resource Settings */ + Method(_SRS, 1) + { + CreateByteField(Arg0, 0x02, IOLO) + CreateByteField(Arg0, 0x03, IOHI) + CreateByteField(Arg0, 0x09, IRQL) + + WRIT(0, 0x25, 0) + FindSetRightBit(IRQL, Local0) + Decrement(Local0) + + Store(READ(0, 0x28, 0xf0), Local1) + Or(Local0, Local1, Local0) + WRIT(0, 0x28, Local0) + + Store(IOLO, Local0) + ShiftRight(Local0, 2, Local0) + And(Local0, 0xfe, Local0) + + Store(IOHI, Local1) + ShiftLeft(Local1, 6, Local1) + Or (Local0, Local1, Local0) + WRIT(0, 0x25, Local0) + + Store(READ(0, 0x0c, 0xff), Local0) + Not(0x38, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x0c, Local0) + + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x80, Local0) + WRIT(0, 0x02, Local0) + + Store(READ(0, 0x07, 0xff), Local0) + Not(0x20, Local1) + And (Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D0 state - Line drivers are on */ + Method (_PS0, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Or(Local0, 0x80, Local0) + WRIT(0, 0x02, Local0) + + Store (READ(0, 0x07, 0xff), Local0) + Not(0x20, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x07, Local0) + } + + /* D3 State - Line drivers are off */ + Method(_PS3, 0) + { + Store(READ(0, 0x02, 0xff), Local0) + Not(0x80, Local1) + And(Local0, Local1, Local0) + WRIT(0, 0x02, Local0) + } + } +} + diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl new file mode 100644 index 0000000..4cd8882 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/thermal.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + /* degree Celcius to deci-Kelvin (ACPI temperature unit) */ + Method(C2dK, 1) { + Add (2732, Multiply (Arg0, 10), Local0) + Return (Local0) + } + + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x96) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (C2dK(120)) // Value for Rocky + } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (C2dK(155)) // Value for Rocky + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (C2dK(105)) // Value for Rocky + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + If (\_SB.PCI0.LPCB.EC0.ALRC) { + Store(0, \_SB.PCI0.LPCB.EC0.ALRC) + Return(_AC0()) + } + + If (\_SB.PCI0.LPCB.EC0.ALRL) { + Store(0, THRO) + Store(0, \_SB.PCI0.LPCB.EC0.ALRL) + } + + If (\_SB.PCI0.LPCB.EC0.ALRH) { + Store(1, THRO) + Store(0, \_SB.PCI0.LPCB.EC0.ALRH) + } + + /* vendor BIOS reports 0K if TCPU >= 128 deg C ?!? */ + Return (C2dK(\_SB.PCI0.LPCB.EC0.TCPU)) + } + + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU0, \_PR.CPU1}) + } + Return (Package() {\_PR.CPU0}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} + diff --git a/src/mainboard/roda/rk9/acpi/video.asl b/src/mainboard/roda/rk9/acpi/video.asl new file mode 100644 index 0000000..507a390 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi/video.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c new file mode 100644 index 0000000..6e6cd72 --- /dev/null +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -0,0 +1,313 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include "southbridge/intel/i82801ix/nvs.h" +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 0; /* Will use default of 0x00000400. */ + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +static void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ +#define HPET_ADDR 0xfed00000ULL + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = HPET_ADDR & 0xffffffff; + addr->addrh = HPET_ADDR >> 32; + + hpet->id = 0x8086a201; /* Intel */ + hpet->number = 0x00; + hpet->min_tick = 0x0080; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* LAPIC_NMI */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 0, + MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) + current, 1, MP_IRQ_POLARITY_HIGH | + MP_IRQ_TRIGGER_EDGE, 0x01); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1); + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_IOMMU + acpi_dmar_t *dmar; +#endif +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + void *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + +#if CONFIG_IOMMU + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + dmar = (acpi_dmar_t *) current; + acpi_create_dmar(dmar); + current += dmar->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, dmar); +#endif + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + /* Fix up global NVS region for SMI handler. The GNVS region lives + * in the (high) table area. The low memory map looks like this: + * + * 0x00000000 - 0x000003ff Real Mode IVT + * 0x00000020 - 0x0000019c Low MP Table (XXX conflict?) + * 0x00000400 - 0x000004ff BDA (somewhat unused) + * 0x00000500 - 0x0000052f Moved GDT + * 0x00000530 - 0x00000b64 coreboot table + * 0x0007c000 - 0x0007dfff OS boot sector (unused?) + * 0x0007e000 - 0x0007ffff free to use (so no good for acpi+smi) + * 0x00080000 - 0x0009fbff usable ram + * 0x0009fc00 - 0x0009ffff EBDA (unused?) + * 0x000a0000 - 0x000bffff VGA memory + * 0x000c0000 - 0x000cffff VGA option rom + * 0x000d0000 - 0x000dffff free for other option roms? + * 0x000e0000 - 0x000fffff SeaBIOS? (conflict with low tables:) + * 0x000f0000 - 0x000f03ff PIRQ table + * 0x000f0400 - 0x000f66?? ACPI tables + * 0x000f66?? - 0x000f???? DMI tables + */ + + ALIGN_CURRENT; + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* Keep pointer around */ + gnvs = (void *)current; + + current += 0x100; + ALIGN_CURRENT; + +#if CONFIG_HAVE_SMI_HANDLER + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); +#endif + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + + return current; +} diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout new file mode 100644 index 0000000..5c82567 --- /dev/null +++ b/src/mainboard/roda/rk9/cmos.layout @@ -0,0 +1,141 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2007-2008 coresystems GmbH +# 2012 secunet Security Networks AG +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; version 2 of +# the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#400 8 r 0 unused + +# coreboot config options: southbridge +#408 8 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +#937 7 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 unused + +# ram initialization internal data +1024 128 r 0 read_training_results + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + diff --git a/src/mainboard/roda/rk9/cstates.c b/src/mainboard/roda/rk9/cstates.c new file mode 100644 index 0000000..ab0de76 --- /dev/null +++ b/src/mainboard/roda/rk9/cstates.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpigen.h> +#include <device/device.h> /* fix for i82801ix.h */ +#include <southbridge/intel/i82801ix/i82801ix.h> + +static acpi_cstate_t cst_entries[] = { + { + /* acpi C1 / cpu C1 */ + 1, 0x01, 1000, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } + }, + { + /* acpi C2 / cpu C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } + }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb new file mode 100644 index 0000000..002f595 --- /dev/null +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -0,0 +1,152 @@ +chip northbridge/intel/gm45 + device lapic_cluster 0 on + chip cpu/intel/socket_BGA956 + device lapic 0 on end + end + chip cpu/intel/model_1067x + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Enable Super LFM + register "slfm" = "1" + + # Enable C5, C6 + register "c5" = "1" + register "c6" = "1" + end + end + + device pci_domain 0 on + subsystemid 0x4352 0x8986 + device pci 00.0 on end # host bridge + device pci 02.0 on # VGA + ioapic_irq 2 INTA 0x10 + end + device pci 02.1 on end # Display + device pci 03.0 off end # ME + device pci 03.1 off end # ME + device pci 03.2 off end # ME + device pci 03.3 off end # ME + chip southbridge/intel/i82801ix + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + register "gpi8_routing" = "2" + register "gpi7_routing" = "2" + register "gpe0_en" = "0x01800042" + register "gpi1_routing" = "1" + register "alt_gp_smi_en" = "0x0002" + + # Set AHCI mode, enable ports 1 and 2. + register "sata_ahci" = "1" + register "sata_port_map" = "0x03" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Set c-state support + register "c4onc3_enable" = "0" + register "c5_enable" = "1" + register "c6_enable" = "1" + + # Set thermal throttling to 75%. + register "throttle_duty" = "THTL_75_0" + + # Enable PCIe ports 1 and 5 as slots (Mini * PCIe). + register "pcie_slot_implemented" = "0x11" + # Set power limits to 10 * 10^0 watts. + # Maybe we should set less for Mini PCIe. + register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }" + + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "0xfec00000" + device ioapic 2 on end + end + + device pci 19.0 off end # LAN + device pci 1a.0 on # UHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1a.1 on # UHCI + ioapic_irq 2 INTB 0x11 + end + device pci 1a.2 on # UHCI + ioapic_irq 2 INTC 0x12 + end + device pci 1a.7 on # EHCI + ioapic_irq 2 INTC 0x12 + end + device pci 1b.0 on # HD Audio + ioapic_irq 2 INTA 0x10 + end + device pci 1c.0 on # PCIe Port #1 + ioapic_irq 2 INTA 0x10 + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + ioapic_irq 2 INTA 0x10 + device pci 00.0 on end # Realtek 8168B + end + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on # UHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1d.1 on # UHCI + ioapic_irq 2 INTB 0x11 + end + device pci 1d.2 on # UHCI + ioapic_irq 2 INTC 0x12 + end + device pci 1d.7 on # EHCI + ioapic_irq 2 INTA 0x10 + end + device pci 1e.0 on # PCI + device pci 03.0 on # TI Cardbus + ioapic_irq 2 INTA 0x10 + end + device pci 03.1 on # TI Cardbus + ioapic_irq 2 INTB 0x11 + end + device pci 03.2 off end # TI FireWire OHC + device pci 03.3 off end # unconnected FlashMedia + device pci 03.4 off end # unconnected SD-Card + end + device pci 1f.0 on # LPC bridge + chip superio/smsc/lpc47n227 + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # Keyboard+Mouse + end + end + end + device pci 1f.2 on # SATA/IDE 1 + ioapic_irq 2 INTB 0x11 + end + device pci 1f.3 on # SMBus + ioapic_irq 2 INTC 0x12 + end + device pci 1f.5 off end # SATA/IDE 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/roda/rk9/dsdt.asl b/src/mainboard/roda/rk9/dsdt.asl new file mode 100644 index 0000000..a240b17 --- /dev/null +++ b/src/mainboard/roda/rk9/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801ix/acpi/globalnvs.asl> + + // General Purpose Events + #include "acpi/gpe.asl" + + // mainboard specific devices + #include "acpi/mainboard.asl" + + // Thermal Zone + #include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/gm45/acpi/gm45.asl> + #include <southbridge/intel/i82801ix/acpi/ich9.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801ix/acpi/sleepstates.asl> +} diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c new file mode 100644 index 0000000..fef9721 --- /dev/null +++ b/src/mainboard/roda/rk9/fadt.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 0x00; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 0x39; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0x00; + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_DOCKING_SUPPORTED | ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 0x06; + + fadt->x_firmware_ctl_l = 0; /* Set X_FIRMWARE_CTRL only if FACS is */ + fadt->x_firmware_ctl_h = 0; /* above 4GB. If X_FIRMWARE_CTRL is set, */ + /* then FIRMWARE_CTRL must be zero. */ + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 0; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; /* Upper word is reserved and + Linux complains about 32 bit. */ + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 0; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 0; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/roda/rk9/hda_verb.h b/src/mainboard/roda/rk9/hda_verb.h new file mode 100644 index 0000000..f99d097 --- /dev/null +++ b/src/mainboard/roda/rk9/hda_verb.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define PIN_CFG(pin, val) \ + (pin << 20) | ( 0x71c << 8) | (val & 0xff), \ + (pin << 20) | ( 0x71d << 8) | ((val >> 8) & 0xff), \ + (pin << 20) | ( 0x71e << 8) | ((val >> 16) & 0xff), \ + (pin << 20) | ( 0x71f << 8) | ((val >> 24) & 0xff), \ + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x43528986, // Subsystem ID + 0x0000000c, // Number of entries + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x11), S/PDIF-OUT2: not connected */ + PIN_CFG(0x11, 0x411111f0) + /* Pin Complex (NID 0x14), LINE_OUT (port D): Speakers */ + PIN_CFG(0x14, 0x99130110) + /* Pin Complex (NID 0x15), HP_OUT (port A): Head phones */ + PIN_CFG(0x15, 0x0121411f) + /* Pin Complex (NID 0x16), MONO-OUT: not connected */ + PIN_CFG(0x16, 0x411111f0) + /* Pin Complex (NID 0x18), MIC1 (port B): Microphone */ + PIN_CFG(0x18, 0x01a19920) + /* Pin Complex (NID 0x19), MIC2 (port F): not connected */ + PIN_CFG(0x19, 0x411111f0) + /* Pin Complex (NID 0x1a), LINE1 (port C): Line-In */ + PIN_CFG(0x1a, 0x01813121) + /* Pin Complex (NID 0x1b), LINE2 (port E): MDC */ + PIN_CFG(0x1b, 0x9983012f) + /* Pin Complex (NID 0x1c), CD_IN */ + PIN_CFG(0x1c, 0x593301f0) + /* Pin Complex (NID 0x1d), PCBEEP */ + PIN_CFG(0x1d, 0x4014022d) + /* Pin Complex (NID 0x1e), S/PDIF-OUT: not connected */ + PIN_CFG(0x1e, 0x411111f0) + /* Pin Complex (NID 0x1f), S/PDIF-IN: not connected */ + PIN_CFG(0x1f, 0x411111f0) +}; +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; + +static const u32 mainboard_pc_beep_verbs[] = { + 0x00170500, /* power up codec */ + 0x01470500, /* power up speakers */ + 0x01470100, /* select lout1 (input 0x0) for speakers */ + 0x01470740, /* enable speakers output */ + 0x00b37517, /* unmute beep (mixer's input 0x5), set amp 0dB */ + 0x00c37100, /* unmute mixer in lout1 (lout1 input 0x1) */ + 0x00c3b015, /* set lout1 output volume -15dB */ + 0x0143b000, /* unmute speakers */ +}; +extern const u32 * pc_beep_verbs; +extern u32 pc_beep_verbs_size; diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c new file mode 100644 index 0000000..5b4285c --- /dev/null +++ b/src/mainboard/roda/rk9/mainboard.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <arch/io.h> +//#include <pc80/mc146818rtc.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include <x86emu/x86emu.h> +#endif +#include <pc80/keyboard.h> +#include <ec/acpi/ec.h> +#include "hda_verb.h" + +#if CONFIG_GENERATE_ACPI_TABLES +#include "cstates.c" /* Include it, as the linker won't find + the overloaded weak function in there. */ +#endif + + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +static int int15_handler(void) +{ + enum { + BOOT_DISPLAY_DEFAULT = 0, + BOOT_DISPLAY_CRT = (1 << 0), + BOOT_DISPLAY_TV = (1 << 1), + BOOT_DISPLAY_EFP = (1 << 2), + BOOT_DISPLAY_LFP = (1 << 3), + BOOT_DISPLAY_CRT2 = (1 << 4), + BOOT_DISPLAY_TV2 = (1 << 5), + BOOT_DISPLAY_EFP2 = (1 << 6), + BOOT_DISPLAY_LFP2 = (1 << 7), + }; + enum { + PANEL_FIT_DEFAULT = 0, + PANEL_FIT_CENTERING = (1 << 0), + PANEL_FIT_TXT_STRETCH = (1 << 1), + PANEL_FIT_GFX_STRETCH = (1 << 2), + }; + + switch (M.x86.R_AX) { + case 0x5f34: + /* Set Panel Fitting Hook */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = PANEL_FIT_CENTERING; + break; + case 0x5f35: + /* Boot Display Device Hook */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = BOOT_DISPLAY_DEFAULT; /* Select automatically. */ + break; + case 0x5f40: + /* Boot Panel Type Hook */ + /* Contrary to what EMGD's user's guide says, + this _alters_ the behavior of the Video BIOS. */ + /* LCD panel type is SIO GPIO40-43. + It's controlled by a DIP switch but was always + set to 4 while only values of 5 and 6 worked. */ + M.x86.R_AX = 0x005f; + M.x86.R_CX = (inb(0x60f) & 0x0f) + 1; + break; + case 0x5f70: + /* Sandybridge boards return 0 here. */ + case 0x5f14: + case 0x5f21: + case 0x5f22: + case 0x5f49: + /* No documentation found. */ + default: + /* Interrupt was not handled. */ + printk(BIOS_DEBUG, + "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", __func__, + M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + return 0; + } + + /* Interrupt handled. */ + return 1; +} + +static void int15_install(void) +{ + typedef int (* yabel_handleIntFunc)(void); + extern yabel_handleIntFunc yabel_intFuncArray[256]; + yabel_intFuncArray[0x15] = int15_handler; +} +#endif + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = ARRAY_SIZE(mainboard_pc_beep_verbs); +} + +static void ec_setup(void) +{ + /* Thermal limits? Values are from ectool's ram dump. */ + ec_write(0xd1, 0x57); /* CPUH */ + ec_write(0xd2, 0xc9); /* CPUL */ + ec_write(0xd4, 0x64); /* SYSH */ + ec_write(0xd5, 0xc9); /* SYSL */ + + send_ec_command(0x04); /* Set_SMI_Enable */ + send_ec_command(0xab); /* Set_ACPI_Disable */ + send_ec_command(0xac); /* Clr_SYS_Flag? well, why not? */ + send_ec_command(0xad); /* Set_Thml_Value */ +} + +static void mainboard_enable(device_t dev) +{ + ec_setup(); + verb_setup(); +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL// || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + /* Install custom int15 handler for VGA OPROM */ + int15_install(); +#endif + + /* We have no driver for the embedded controller since the firmware + does most of the job. Hence, initialize keyboards here. */ + pc_keyboard_init(NULL); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/roda/rk9/mainboard_smi.c b/src/mainboard/roda/rk9/mainboard_smi.c new file mode 100644 index 0000000..8a87cd9 --- /dev/null +++ b/src/mainboard/roda/rk9/mainboard_smi.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801ix/nvs.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <ec/acpi/ec.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + gnvs->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +void mainboard_smi_gpi(u16 gpi_sts) +{ + if (gpi_sts & (1 << 1)) { + printk(BIOS_DEBUG, "EC/SMI\n"); + /* TODO */ + } +} + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + send_ec_command(0x05); /* Set_SMI_Disable */ + send_ec_command(0xaa); /* Set_ACPI_Enable */ + break; + + case APM_CNT_ACPI_DISABLE: + send_ec_command(0x04); /* Set_SMI_Enable */ + send_ec_command(0xab); /* Set_ACPI_Disable */ + break; + } + return 0; +} diff --git a/src/mainboard/roda/rk9/mptable.c b/src/mainboard/roda/rk9/mptable.c new file mode 100644 index 0000000..f1839f0 --- /dev/null +++ b/src/mainboard/roda/rk9/mptable.c @@ -0,0 +1 @@ +/* dummy file */ diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c new file mode 100644 index 0000000..c6ca078 --- /dev/null +++ b/src/mainboard/roda/rk9/romstage.c @@ -0,0 +1,211 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cbmem.h> +#include <lib.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <northbridge/intel/gm45/gm45.h> +#include <superio/smsc/lpc47n227/early_serial.c> + +#define LPC_DEV PCI_DEV(0, 0x1f, 0) +#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1) + +static void default_southbridge_gpio_setup(void) +{ + /* Enable GPIOs [31:0]. */ + outl(0x197e7dfe, DEFAULT_GPIOBASE + 0x00); + /* Set input/output mode [31:0] (0 == out, 1 == in). */ + outl(0xe0ea43fe, DEFAULT_GPIOBASE + 0x04); + /* Set gpio levels [31:0]. orig: 0x01140800 (~SATA0, ~SATA1, GSM, BT, + WLAN, ~ANTMUX, ~GPIO12, + ~SUSPWR, SMBALERT) */ + outl(0x00000800, DEFAULT_GPIOBASE + 0x0c); + + /* Disable blink [31:0]. */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); + /* Set input inversion [31:0]. */ + outl(0x00000182, DEFAULT_GPIOBASE + 0x2c); + + /* Enable GPIOs [60:32]. */ + outl(0x130300fe, DEFAULT_GPIOBASE + 0x30); + /* Set input/output mode [60:32] (0 == out, 1 == in). */ + outl(0x0e55ffb0, DEFAULT_GPIOBASE + 0x34); + /* Set gpio levels [60:32]. orig: 0x10020046 (LNKALERT, ~ATAIO, + DMITERM, TXT, ~CLKSATA, + GPS, AUDIO) */ + outl(0x10020042, DEFAULT_GPIOBASE + 0x38); +} + +static void early_lpc_setup(void) +{ + /* Set up SuperIO LPC forwards */ + + /* Configure serial IRQs.*/ + pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0); + /* Map COMa on 0x3f8, COMb on 0x2f8. */ + pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); + /* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */ + pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03); +} + +static void default_superio_gpio_setup(void) +{ + /* Original settings: + idx 30 31 32 33 34 35 36 37 38 39 + val 60 00 00 40 00 ff 00 e0 00 80 + def 00 00 00 00 00 00 00 00 00 80 + + Values: + GP1 GP2 GP3 GP4 + fd 17 88 14 + */ + const device_t sio = PNP_DEV(0x2e, 0); + + /* Enter super-io's configuration state. */ + pnp_enter_conf_state(sio); + + /* Set lpc47n227's runtime register block's base address. */ + pnp_write_config(sio, 0x30, 0x600 >> 4); + + /* Set GP23 to alternate function. */ + pnp_write_config(sio, 0x33, 0x40); + + /* Set GP30 - GP37 to output mode: COM control */ + pnp_write_config(sio, 0x35, 0xff); + + /* Set GP45 - GP47 to output mode. */ + pnp_write_config(sio, 0x37, 0xe0); + + /* Set nIO_PME to open drain. */ + pnp_write_config(sio, 0x39, 0x80); + + /* Exit configuration state. */ + pnp_exit_conf_state(sio); + + + /* Enable decoding of 0x600-0x60f through lpc. */ + pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601); + + /* Set GPIO output values: */ + outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */ + outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ +} + +void main(unsigned long bist) +{ + sysinfo_t sysinfo; + int s3resume = 0; + u16 reg16; + + /* basic northbridge setup, including MMCONF BAR */ + gm45_early_init(); + + if (bist == 0) + enable_lapic(); + + /* First, run everything needed for console output. */ + i82801ix_early_init(); + early_lpc_setup(); + default_superio_gpio_setup(); + lpc47n227_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist); + + reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3); + pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16); + if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + gm45_early_reset(); + } + + default_southbridge_gpio_setup(); + + /* ASPM related setting, set early by original BIOS. */ + DMIBAR16(0x204) &= ~(3 << 10); + + /* Check for S3 resume. */ + const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); + if (((pm1_cnt >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + /* RAM initialization */ + enter_raminit_or_reset(); + get_gmch_info(&sysinfo); + raminit(&sysinfo, s3resume); + + raminit_thermal(&sysinfo); + init_igd(&sysinfo, 0, 1); /* Enable IGD, disable PEG. */ + init_pm(&sysinfo); + + i82801ix_dmi_setup(); + gm45_late_init(sysinfo.stepping); + i82801ix_dmi_poll_vc1(); + + MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; + + init_iommu(); + +#if CONFIG_HAVE_ACPI_RESUME + /* Start address of high memory tables */ + unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if (s3resume && cbmem_reinit((u64)high_ram_base)) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); + } +#endif + printk(BIOS_SPEW, "exit main()\n"); +} + diff --git a/src/mainboard/roda/rk9/ti_pci7xx1.c b/src/mainboard/roda/rk9/ti_pci7xx1.c new file mode 100644 index 0000000..8acc90f --- /dev/null +++ b/src/mainboard/roda/rk9/ti_pci7xx1.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/cardbus.h> + +static void pci7xx1_enable(struct device *const dev) +{ + printk(BIOS_DEBUG, "%s: TI PCI7xx1 media controller\n", __func__); + if (PCI_FUNC(dev->path.pci.devfn) == 0) { + const uint16_t secondary = dev->bus->secondary; + const unsigned slot = PCI_SLOT(dev->path.pci.devfn); + + int fn; + + /* Hide functions based on devicetree info. */ + u16 gcr = pci_read_config16(dev, 0x86); + for (fn = 5; fn > 0; --fn) { + const struct device *const d = + dev_find_slot(secondary, PCI_DEVFN(slot, fn)); + if (!d || d->enabled) continue; + printk(BIOS_DEBUG, + "%s: Hiding function #%d.\n", __func__, fn); + switch (fn) { + case 1: gcr |= 1 << 4; break; /* CardBus B */ + case 2: gcr |= 1 << 3; break; /* OHCI 1394 */ + case 3: gcr |= 1 << 5; break; /* Flash media */ + case 4: gcr |= 1 << 6; break; /* SD card */ + case 5: gcr |= 1 << 7; break; /* Smart Card */ + } + } + pci_write_config16(dev, 0x86, gcr); + } +} + +static struct device_operations device_ops = { + .read_resources = cardbus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = cardbus_enable_resources, + .init = 0, + .scan_bus = pci_scan_bridge, + .enable = pci7xx1_enable, + .reset_bus = pci_bus_reset, +}; + +static const struct pci_driver ti_pci7xx1 __pci_driver = { + .ops = &device_ops, + .vendor = 0x104c, + .device = 0x8031, +}; +

1 0

Patch set updated for coreboot: 57326bb intel/i82801ix: new southbridge, ICH9
by Nico Huber 16 Nov '12

16 Nov '12

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1690 -gerrit commit 57326bb612264e208b3db8ee57de5aa997d7855c Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 6 11:05:09 2012 +0100 intel/i82801ix: new southbridge, ICH9 Add support for ICH9 southbridge Change-Id: I70612431101bf48d9dcc96ee1b37d257c9ad2ee2 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/cpu/x86/smm/smmrelocate.S | 2 + src/southbridge/intel/Kconfig | 1 + src/southbridge/intel/Makefile.inc | 1 + src/southbridge/intel/i82801ix/Kconfig | 48 ++ src/southbridge/intel/i82801ix/Makefile.inc | 42 ++ src/southbridge/intel/i82801ix/acpi/audio.asl | 36 ++ src/southbridge/intel/i82801ix/acpi/globalnvs.asl | 171 +++++++ src/southbridge/intel/i82801ix/acpi/ich9.asl | 208 ++++++++ src/southbridge/intel/i82801ix/acpi/irqlinks.asl | 493 ++++++++++++++++++ src/southbridge/intel/i82801ix/acpi/lpc.asl | 290 +++++++++++ src/southbridge/intel/i82801ix/acpi/pci.asl | 77 +++ src/southbridge/intel/i82801ix/acpi/pcie.asl | 186 +++++++ src/southbridge/intel/i82801ix/acpi/sata.asl | 142 ++++++ .../intel/i82801ix/acpi/sleepstates.asl | 30 ++ src/southbridge/intel/i82801ix/acpi/smbus.asl | 242 +++++++++ src/southbridge/intel/i82801ix/acpi/usb.asl | 331 ++++++++++++ src/southbridge/intel/i82801ix/bootblock.c | 40 ++ src/southbridge/intel/i82801ix/chip.h | 95 ++++ src/southbridge/intel/i82801ix/dmi_setup.c | 147 ++++++ src/southbridge/intel/i82801ix/early_init.c | 65 +++ src/southbridge/intel/i82801ix/early_smbus.c | 64 +++ src/southbridge/intel/i82801ix/hdaudio.c | 332 ++++++++++++ src/southbridge/intel/i82801ix/i82801ix.c | 264 ++++++++++ src/southbridge/intel/i82801ix/i82801ix.h | 222 ++++++++ src/southbridge/intel/i82801ix/lpc.c | 566 +++++++++++++++++++++ src/southbridge/intel/i82801ix/nvs.h | 138 +++++ src/southbridge/intel/i82801ix/pci.c | 86 ++++ src/southbridge/intel/i82801ix/pcie.c | 134 +++++ src/southbridge/intel/i82801ix/sata.c | 285 +++++++++++ src/southbridge/intel/i82801ix/smbus.h | 100 ++++ src/southbridge/intel/i82801ix/smi.c | 392 ++++++++++++++ src/southbridge/intel/i82801ix/smihandler.c | 532 +++++++++++++++++++ src/southbridge/intel/i82801ix/thermal.c | 85 ++++ src/southbridge/intel/i82801ix/usb_ehci.c | 107 ++++ 34 files changed, 5954 insertions(+) diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index b752531..16d4b9f 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -37,6 +37,8 @@ #include "../../../southbridge/intel/sch/sch.h" #elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216 #include "../../../southbridge/intel/bd82x6x/pch.h" +#elif CONFIG_SOUTHBRIDGE_INTEL_I82801IX +#include "../../../southbridge/intel/i82801ix/i82801ix.h" #else #error "Southbridge needs SMM handler support." #endif diff --git a/src/southbridge/intel/Kconfig b/src/southbridge/intel/Kconfig index cb0ac83..bb539ad 100644 --- a/src/southbridge/intel/Kconfig +++ b/src/southbridge/intel/Kconfig @@ -7,6 +7,7 @@ source src/southbridge/intel/i82801cx/Kconfig source src/southbridge/intel/i82801dx/Kconfig source src/southbridge/intel/i82801ex/Kconfig source src/southbridge/intel/i82801gx/Kconfig +source src/southbridge/intel/i82801ix/Kconfig source src/southbridge/intel/i82870/Kconfig source src/southbridge/intel/pxhd/Kconfig source src/southbridge/intel/sch/Kconfig diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc index 6869e5b..75f4322 100644 --- a/src/southbridge/intel/Makefile.inc +++ b/src/southbridge/intel/Makefile.inc @@ -7,6 +7,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx +subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) += i82801ix subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_PXHD) += pxhd subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig new file mode 100644 index 0000000..ec30af8 --- /dev/null +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -0,0 +1,48 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## 2012 secunet security Networks AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_INTEL_I82801IX + bool + select IOAPIC + select HAVE_USBDEBUG + select HAVE_HARD_RESET + select USE_WATCHDOG_ON_BOOT + select HAVE_SMI_HANDLER + +if SOUTHBRIDGE_INTEL_I82801IX + +config EHCI_BAR + hex + default 0xfef00000 + +config EHCI_DEBUG_OFFSET + hex + default 0xa0 + +config USBDEBUG_DEFAULT_PORT + int + default 1 + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/intel/i82801ix/bootblock.c" + +endif + diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc new file mode 100644 index 0000000..2fd1967 --- /dev/null +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## 2012 secunet Security Networks AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +driver-y += i82801ix.c +driver-y += pci.c +driver-y += lpc.c +driver-y += pcie.c +driver-y += usb_ehci.c +driver-y += sata.c +driver-y += hdaudio.c +driver-y += thermal.c + +ramstage-y += ../i82801gx/usb_debug.c +ramstage-y += ../i82801gx/reset.c +ramstage-y += ../i82801gx/watchdog.c + +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +romstage-y += early_init.c +romstage-y += early_smbus.c +romstage-y += dmi_setup.c +romstage-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c +smm-$(CONFIG_USBDEBUG) += ../i82801gx/usb_debug.c + diff --git a/src/southbridge/intel/i82801ix/acpi/audio.asl b/src/southbridge/intel/i82801ix/acpi/audio.asl new file mode 100644 index 0000000..e7f5019 --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/audio.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Intel i82801I HDA */ + +// Intel High Definition Audio (Azalia) 0:1b.0 + +Device (HDEF) +{ + Name (_ADR, 0x001b0000) + + // Power Resources for Wake + Name (_PRW, Package(){ + 5, // Bit 5 of GPE + 4 // Can wake from S4 state. + }) +} + diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl new file mode 100644 index 0000000..0384376 --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Global Variables */ + +Name(\PICM, 0) // IOAPIC/8259 +Name(\DSEN, 1) // Display Output Switching Enable + +/* Global ACPI memory region. This region is used for passing information + * between coreboot (aka "the system bios"), ACPI, and the SMI handler. + * Since we don't know where this will end up in memory at ACPI compile time, + * we have to fix it up in coreboot's ACPI creation phase. + */ + + +OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x100) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + Offset (0x00), + OSYS, 16, // 0x00 - Operating System + SMIF, 8, // 0x02 - SMI function + PRM0, 8, // 0x03 - SMI function parameter + PRM1, 8, // 0x04 - SMI function parameter + SCIF, 8, // 0x05 - SCI function + PRM2, 8, // 0x06 - SCI function parameter + PRM3, 8, // 0x07 - SCI function parameter + LCKF, 8, // 0x08 - Global Lock function for EC + PRM4, 8, // 0x09 - Lock function parameter + PRM5, 8, // 0x0a - Lock function parameter + P80D, 32, // 0x0b - Debug port (IO 0x80) value + LIDS, 8, // 0x0f - LID state (open = 1) + PWRS, 8, // 0x10 - Power State (AC = 1) + DBGS, 8, // 0x11 - Debug State + LINX, 8, // 0x12 - Linux OS + DCKN, 8, // 0x13 - PCIe docking state + /* Thermal policy */ + Offset (0x14), + ACTT, 8, // 0x14 - active trip point + PSVT, 8, // 0x15 - passive trip point + TC1V, 8, // 0x16 - passive trip point TC1 + TC2V, 8, // 0x17 - passive trip point TC2 + TSPV, 8, // 0x18 - passive trip point TSP + CRTT, 8, // 0x19 - critical trip point + DTSE, 8, // 0x1a - Digital Thermal Sensor enable + DTS1, 8, // 0x1b - DT sensor 1 + DTS2, 8, // 0x1c - DT sensor 2 + /* Battery Support */ + Offset (0x1e), + BNUM, 8, // 0x1e - number of batteries + B0SC, 8, // 0x1f - BAT0 stored capacity + B1SC, 8, // 0x20 - BAT1 stored capacity + B2SC, 8, // 0x21 - BAT2 stored capacity + B0SS, 8, // 0x22 - BAT0 stored status + B1SS, 8, // 0x23 - BAT1 stored status + B2SS, 8, // 0x24 - BAT2 stored status + /* Processor Identification */ + Offset (0x28), + APIC, 8, // 0x28 - APIC Enabled by coreboot + MPEN, 8, // 0x29 - Multi Processor Enable + PCP0, 8, // 0x2a - PDC CPU/CORE 0 + PCP1, 8, // 0x2b - PDC CPU/CORE 1 + PPCM, 8, // 0x2c - Max. PPC state + /* Super I/O & CMOS config */ + Offset (0x32), + NATP, 8, // 0x32 - + CMAP, 8, // 0x33 - + CMBP, 8, // 0x34 - + LPTP, 8, // 0x35 - LPT Port + FDCP, 8, // 0x36 - Floppy Disk Controller + RFDV, 8, // 0x37 - + HOTK, 8, // 0x38 - + RTCF, 8, // 0x39 - + UTIL, 8, // 0x3a - + ACIN, 8, // 0x3b - + /* Integrated Graphics Device */ + Offset (0x3c), + IGDS, 8, // 0x3c - IGD state (primary = 1) + TLST, 8, // 0x3d - Display Toggle List pointer + CADL, 8, // 0x3e - Currently Attached Devices List + PADL, 8, // 0x3f - Previously Attached Devices List + CSTE, 16, // 0x40 - Current display state + NSTE, 16, // 0x42 - Next display state + SSTE, 16, // 0x44 - Set display state + Offset (0x46), + NDID, 8, // 0x46 - Number of Device IDs + DID1, 32, // 0x47 - Device ID 1 + DID2, 32, // 0x4b - Device ID 2 + DID3, 32, // 0x4f - Device ID 3 + DID4, 32, // 0x53 - Device ID 4 + DID5, 32, // 0x57 - Device ID 5 + /* Backlight Control */ + Offset (0x64), + BLCS, 8, // 0x64 - Backlight control possible? + BRTL, 8, // 0x65 - Brightness Level + ODDS, 8, // 0x66 + /* Ambient Light Sensors */ + Offset (0x6e), + ALSE, 8, // 0x6e - ALS enable + ALAF, 8, // 0x6f - Ambient light adjustment factor + LLOW, 8, // 0x70 - LUX Low + LHIH, 8, // 0x71 - LUX High + /* EMA */ + Offset (0x78), + EMAE, 8, // 0x78 - EMA enable + EMAP, 16, // 0x79 - EMA pointer + EMAL, 16, // 0x7b - EMA length + /* MEF */ + Offset (0x82), + MEFE, 8, // 0x82 - MEF enable + /* TPM support */ + Offset (0x8c), + TPMP, 8, // 0x8c - TPM + TPME, 8, // 0x8d - TPM enable + /* SATA */ + Offset (0x96), + GTF0, 56, // 0x96 - GTF task file buffer for port 0 + GTF1, 56, // 0x9d - GTF task file buffer for port 1 + GTF2, 56, // 0xa4 - GTF task file buffer for port 2 + IDEM, 8, // 0xab - IDE mode (compatible / enhanced) + IDET, 8, // 0xac - IDE + /* IGD OpRegion */ + Offset (0xb4), + ASLB, 32, // 0xb4 - IGD OpRegion Base Address + IBTT, 8, // 0xb8 - IGD boot panel device + IPAT, 8, // 0xb9 - IGD panel type cmos option + ITVF, 8, // 0xba - IGD TV format cmos option + ITVM, 8, // 0xbb - IGD TV minor format option + IPSC, 8, // 0xbc - IGD panel scaling + IBLC, 8, // 0xbd - IGD BLC config + IBIA, 8, // 0xbe - IGD BIA config + ISSC, 8, // 0xbf - IGD SSC config + I409, 8, // 0xc0 - IGD 0409 modified settings + I509, 8, // 0xc1 - IGD 0509 modified settings + I609, 8, // 0xc2 - IGD 0609 modified settings + I709, 8, // 0xc3 - IGD 0709 modified settings + IDMM, 8, // 0xc4 - IGD DVMT Mode + IDMS, 8, // 0xc5 - IGD DVMT memory size + IF1E, 8, // 0xc6 - IGD function 1 enable + HVCO, 8, // 0xc7 - IGD HPLL VCO + NXD1, 32, // 0xc8 - IGD _DGS next DID1 + NXD2, 32, // 0xcc - IGD _DGS next DID2 + NXD3, 32, // 0xd0 - IGD _DGS next DID3 + NXD4, 32, // 0xd4 - IGD _DGS next DID4 + NXD5, 32, // 0xd8 - IGD _DGS next DID5 + NXD6, 32, // 0xdc - IGD _DGS next DID6 + NXD7, 32, // 0xe0 - IGD _DGS next DID7 + NXD8, 32, // 0xe4 - IGD _DGS next DID8 + /* Mainboard Specific (TODO move elsewhere) */ + Offset (0xf0), + DOCK, 8, // 0xf0 - Docking Status + BTEN, 8, // 0xf1 - Bluetooth Enable +} diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl new file mode 100644 index 0000000..8ded413 --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Intel 82801Ix support */ + +Scope(\) +{ + // IO-Trap at 0x800. This is the ACPI->SMI communication interface. + + OperationRegion(IO_T, SystemIO, 0x800, 0x10) + Field(IO_T, ByteAcc, NoLock, Preserve) + { + Offset(0x8), + TRP0, 8 // IO-Trap at 0x808 + } + + // ICH9 Power Management Registers, located at PMBASE (0x1f.0 0x40.l) + OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80) + Field(PMIO, ByteAcc, NoLock, Preserve) + { + Offset(0x11), + THRO, 1, // force thermal throttling + Offset(0x42), // General Purpose Control + , 1, // skip 1 bit + GPEC, 1, // TCO status + Offset(0x64), + , 9, // skip 9 more bits + SCIS, 1 // TCO DMI status + } + + // FIXME: purposes of the GPIOs (comments) are probably wrong + // ICH9 GPIO IO mapped registers (0x1f.0 reg 0x48.l) + OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c) + Field(GPIO, ByteAcc, NoLock, Preserve) + { + Offset(0x00), // GPIO Use Select + GU00, 8, + GU01, 8, + GU02, 8, + GU03, 8, + Offset(0x04), // GPIO IO Select + GIO0, 8, + GIO1, 8, + GIO2, 8, + GIO3, 8, + Offset(0x0c), // GPIO Level + GP00, 1, + GP01, 1, + GP02, 1, + GP03, 1, + GP04, 1, + GP05, 1, + GP06, 1, // GDET + GP07, 1, + GP08, 1, + GP09, 1, // HPMU + GP10, 1, // GPSE + GP11, 1, + GP12, 1, // WLED + GP13, 1, // BLED + GP14, 1, // GLED + GP15, 1, // GDIS + GP16, 1, + GP17, 1, + GP18, 1, // SPCI + GP19, 1, // TSDT + GP20, 1, // SCPU + GP21, 1, + GP22, 1, + GP23, 1, // LANP + GP24, 1, // DKLR + GP25, 1, // WLAN + GP26, 1, // SATA_PWR_EN #0 / SPOF + GP27, 1, // SATA_PWR_EN #1 / SPMU + GP28, 1, + GP29, 1, + GP30, 1, + GP31, 1, + Offset(0x18), // GPIO Blink + GB00, 8, + GB01, 8, + GB02, 8, + GB03, 8, + Offset(0x2c), // GPIO Invert + GIV0, 8, + GIV1, 8, + GIV2, 8, + GIV3, 8, + Offset(0x30), // GPIO Use Select 2 + GU04, 8, + GU05, 8, + GU06, 8, + GU07, 8, + Offset(0x34), // GPIO IO Select 2 + GIO4, 8, + GIO5, 8, + GIO6, 8, + GIO7, 8, + Offset(0x38), // GPIO Level 2 + GP32, 1, + GP33, 1, // CREN + GP34, 1, // CRRS + GP35, 1, + GP36, 1, // STAD + GP37, 1, // PATA_PWR_EN / HDDE + GP38, 1, // Battery / Power (?) / MB00 + GP39, 1, // ?? / MB01 + GL05, 8, + GL06, 8, + GL07, 8 + } + + + // ICH9 Root Complex Register Block. Memory Mapped through RCBA) + OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) + Field(RCRB, DWordAcc, Lock, Preserve) + { + Offset(0x0000), // Backbone + Offset(0x1000), // Chipset + Offset(0x3000), // Legacy Configuration Registers + Offset(0x3404), // High Performance Timer Configuration + HPAS, 2, // Address Select + , 5, + HPTE, 1, // Address Enable + Offset(0x3418), // FD (Function Disable) + , 2, // Reserved + SA1D, 1, // SATA disable + SMBD, 1, // SMBUS disable + HDAD, 1, // Azalia disable + , 2, // Reserved + US6D, 1, // UHCI #6 disable + US1D, 1, // UHCI #1 disable + US2D, 1, // UHCI #2 disable + US3D, 1, // UHCI #3 disable + US4D, 1, // UHCI #4 disable + US5D, 1, // UHCI #5 disable + EH2D, 1, // EHCI disable + LPBD, 1, // LPC bridge disable + EH1D, 1, // EHCI disable + Offset(0x341a), // FD Root Ports + RP1D, 1, // Root Port 1 disable + RP2D, 1, // Root Port 2 disable + RP3D, 1, // Root Port 3 disable + RP4D, 1, // Root Port 4 disable + RP5D, 1, // Root Port 5 disable + RP6D, 1, // Root Port 6 disable + , 2, // Reserved + THRD, 1, // Thermal Throttle disable + SA2D, 1, // SATA disable + } + +} + +// 0:1b.0 High Definition Audio (Azalia) +#include "audio.asl" + +// PCI Express Ports +#include "pcie.asl" + +// USB +#include "usb.asl" + +// PCI Bridge +#include "pci.asl" + +// LPC Bridge +#include "lpc.asl" + +// SATA +#include "sata.asl" + +// SMBus +#include "smbus.asl" + +Method (_OSC, 4) +{ + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +} diff --git a/src/southbridge/intel/i82801ix/acpi/irqlinks.asl b/src/southbridge/intel/i82801ix/acpi/irqlinks.asl new file mode 100644 index 0000000..5fcee45 --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/irqlinks.asl @@ -0,0 +1,493 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LNKA) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 1) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTA) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLA, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTA + ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + + Return (RTLA) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTA) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTA, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKB) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 2) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTB) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLB, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLB, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTB + ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + + Return (RTLB) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTB) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTB, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKC) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 3) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTC) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLC, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLC, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTC + ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + + Return (RTLC) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTC) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTC, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKD) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 4) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTD) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLD, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLD, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTD + ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + + Return (RTLD) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTD) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTD, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKE) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 5) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTE) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLE, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLE, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTE + ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + + Return (RTLE) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTE) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTE, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKF) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 6) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTF) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLF, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLF, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTF + ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + + Return (RTLF) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTF) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTF, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKG) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 7) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTG) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLG, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLG, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTG + ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + + Return (RTLG) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTG) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTG, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKH) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 8) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTH) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLH, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLH, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTH + ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + + Return (RTLH) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTH) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTH, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + diff --git a/src/southbridge/intel/i82801ix/acpi/lpc.asl b/src/southbridge/intel/i82801ix/acpi/lpc.asl new file mode 100644 index 0000000..0d1e68a --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/lpc.asl @@ -0,0 +1,290 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Intel LPC Bus Device - 0:1f.0 + +Device (LPCB) +{ + Name(_ADR, 0x001f0000) + + OperationRegion(LPC0, PCI_Config, 0x00, 0x100) + Field (LPC0, AnyAcc, NoLock, Preserve) + { + Offset (0x40), + PMBS, 16, // PMBASE + Offset (0x60), // Interrupt Routing Registers + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + Offset (0x68), + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + + Offset (0x80), // IO Decode Ranges + IOD0, 8, + IOD1, 8, + + Offset (0xf0), // RCBA + RCEN, 1, + , 13, + RCBA, 18, + } + + #include "irqlinks.asl" + + #include "acpi/ec.asl" + + Device (DMAC) // DMA Controller + { + Name(_HID, EISAID("PNP0200")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + Device (FWH) // Firmware Hub + { + Name (_HID, EISAID("INT0800")) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + Device (HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_CID, 0x010CD041) + + Name(BUF0, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0) + }) + + Method (_STA, 0) // Device Status + { + If (HPTE) { + // Note: Ancient versions of Windows don't want + // to see the HPET in order to work right + If (LGreaterEqual(OSYS, 2001)) { + Return (0xf) // Enable and show device + } Else { + Return (0xb) // Enable and don't show device + } + } + + Return (0x0) // Not enabled, don't show. + } + + Method (_CRS, 0, Serialized) // Current resources + { + If (HPTE) { + CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) + If (Lequal(HPAS, 1)) { + Store(0xfed01000, HPT0) + } + + If (Lequal(HPAS, 2)) { + Store(0xfed02000, HPT0) + } + + If (Lequal(HPAS, 3)) { + Store(0xfed03000, HPT0) + } + } + + Return (BUF0) + } + } + + Device(PIC) // 8259 Interrupt Controller + { + Name(_HID,EISAID("PNP0000")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x20, 0x20, 0x01, 0x02) + IO (Decode16, 0x24, 0x24, 0x01, 0x02) + IO (Decode16, 0x28, 0x28, 0x01, 0x02) + IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO (Decode16, 0x30, 0x30, 0x01, 0x02) + IO (Decode16, 0x34, 0x34, 0x01, 0x02) + IO (Decode16, 0x38, 0x38, 0x01, 0x02) + IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO (Decode16, 0xac, 0xac, 0x01, 0x02) + IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + Device(MATH) // FPU + { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) + IRQNoFlags() { 13 } + }) + } + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 2) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO + IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap + IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH9 ACPI + IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH9 GPIO + }) + } + + Device (RTC) // Real Time Clock + { + Name (_HID, EISAID("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x70, 0x70, 1, 8) +// Disable as Windows doesn't like it, and systems don't seem to use it. +// IRQNoFlags() { 8 } + }) + } + + Device (TIMR) // Intel 8254 timer + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() {0} + }) + } + + #include "acpi/superio.asl" + +#ifdef ENABLE_TPM + Device (TPM) // Trusted Platform Module + { + Name(_HID, EISAID("IFX0102")) + Name(_CID, 0x310cd041) + Name(_UID, 1) + + Method(_STA, 0) + { + If (TPMP) { + Return (0xf) + } + Return (0x0) + } + + Name(_CRS, ResourceTemplate() { + IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) + IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) + Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) + IRQ (Edge, Activehigh, Exclusive) { 6 } + }) + } +#endif + + Device (PS2K) // Keyboard + { + Name(_HID, EISAID("PNP0303")) + Name(_CID, EISAID("PNP030B")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + + Device (PS2M) // Mouse + { + Name(_HID, EISAID("PNP0F13")) + Name(_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 + }) + + Method(_STA, 0) + { + Return (0xf) + } + } + +#ifdef ENABLE_FDC + Device (FDC0) // Floppy controller + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) // FIXME + } + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + + Name(_PRS, ResourceTemplate() + { + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06) + IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + + } +#endif +} diff --git a/src/southbridge/intel/i82801ix/acpi/pci.asl b/src/southbridge/intel/i82801ix/acpi/pci.asl new file mode 100644 index 0000000..8699c48 --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/pci.asl @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Intel PCI to PCI bridge 0:1e.0 + +Device (PCIB) +{ + Name (_ADR, 0x001e0000) + + Device (SLT1) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package(){ 11, 4 }) + } + + Device (SLT2) + { + Name (_ADR, 0x00010000) + Name (_PRW, Package(){ 11, 4 }) + } + + Device (SLT3) + { + Name (_ADR, 0x00020000) + Name (_PRW, Package(){ 11, 4 }) + } + + Device (SLT6) + { + Name (_ADR, 0x00050000) + Name (_PRW, Package(){ 11, 4 }) + } + + Device (LANC) + { + Name (_ADR, 0x00080000) + Name (_PRW, Package(){ 11, 3 }) + } + + Device (LANR) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package(){ 11, 3 }) + } + + // TODO: How many slots, where? + + // PCI Interrupt Routing. + // If PICM is set, interrupts are routed over the i8259, otherwise + // over the IOAPIC. (Really? If they're above 15 they need to be routed + // fixed over the IOAPIC?) + + Method (_PRT) + { + #include "acpi/ich9_pci_irqs.asl" + } + +} + diff --git a/src/southbridge/intel/i82801ix/acpi/pcie.asl b/src/southbridge/intel/i82801ix/acpi/pcie.asl new file mode 100644 index 0000000..a76c7fb --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/pcie.asl @@ -0,0 +1,186 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Intel i82801G PCIe support */ + +// PCI Express Ports + +Device (RP01) +{ + NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } + }) + + } + + } +} + +Device (RP02) +{ + NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 18 }, + Package() { 0x0000ffff, 2, 0, 19 }, + Package() { 0x0000ffff, 3, 0, 16 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } + }) + + } + + } +} + + +Device (RP03) +{ + NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 18 }, + Package() { 0x0000ffff, 1, 0, 19 }, + Package() { 0x0000ffff, 2, 0, 16 }, + Package() { 0x0000ffff, 3, 0, 17 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } + }) + + } + + } +} + + +Device (RP04) +{ + NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 19 }, + Package() { 0x0000ffff, 1, 0, 16 }, + Package() { 0x0000ffff, 2, 0, 17 }, + Package() { 0x0000ffff, 3, 0, 18 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } + }) + + } + + } +} + + +Device (RP05) +{ + NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } + }) + + } + + } +} + + +Device (RP06) +{ + NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation? + //#include "pcie_port.asl" + Method(_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 18 }, + Package() { 0x0000ffff, 2, 0, 19 }, + Package() { 0x0000ffff, 3, 0, 16 } + }) + } Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } + }) + + } + + } +} + + diff --git a/src/southbridge/intel/i82801ix/acpi/sata.asl b/src/southbridge/intel/i82801ix/acpi/sata.asl new file mode 100644 index 0000000..dbf6b9e --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/sata.asl @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily +// pluggable + +// Intel SATA Controller 0:1f.2 + +Device (AHC1) +{ + Name (_ADR, 0x001f0002) + + Device (PRID) + { + Name (_ADR, 0) + + // Get Timing Mode + Method (_GTM) + { + Name(PBUF, Buffer(20) { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }) + + CreateDwordField (PBUF, 0, PIO0) + CreateDwordField (PBUF, 4, DMA0) + CreateDwordField (PBUF, 8, PIO1) + CreateDwordField (PBUF, 12, DMA1) + CreateDwordField (PBUF, 16, FLAG) + + // TODO fill return structure + + Return (PBUF) + } + + // Set Timing Mode + Method (_STM, 3) + { + CreateDwordField (Arg0, 0, PIO0) + CreateDwordField (Arg0, 4, DMA0) + CreateDwordField (Arg0, 8, PIO1) + CreateDwordField (Arg0, 12, DMA1) + CreateDwordField (Arg0, 16, FLAG) + + // TODO: Do the deed + } + + Device (DSK0) + { + Name (_ADR, 0) + // TODO: _RMV ? + // TODO: _GTF ? + } + + Device (DSK1) + { + Name (_ADR, 1) + + // TODO: _RMV ? + // TODO: _GTF ? + } + + } +} + +// Intel SATA Controller 0:1f.5 + +Device (AHC2) +{ + Name (_ADR, 0x001f0005) + + Device (PRID) + { + Name (_ADR, 0) + + // Get Timing Mode + Method (_GTM) + { + Name(PBUF, Buffer(20) { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }) + + CreateDwordField (PBUF, 0, PIO0) + CreateDwordField (PBUF, 4, DMA0) + CreateDwordField (PBUF, 8, PIO1) + CreateDwordField (PBUF, 12, DMA1) + CreateDwordField (PBUF, 16, FLAG) + + // TODO fill return structure + + Return (PBUF) + } + + // Set Timing Mode + Method (_STM, 3) + { + CreateDwordField (Arg0, 0, PIO0) + CreateDwordField (Arg0, 4, DMA0) + CreateDwordField (Arg0, 8, PIO1) + CreateDwordField (Arg0, 12, DMA1) + CreateDwordField (Arg0, 16, FLAG) + + // TODO: Do the deed + } + + Device (DSK0) + { + Name (_ADR, 0) + // TODO: _RMV ? + // TODO: _GTF ? + } + + Device (DSK1) + { + Name (_ADR, 1) + + // TODO: _RMV ? + // TODO: _GTF ? + } + + } +} + diff --git a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl new file mode 100644 index 0000000..e8dadc2 --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +#if !CONFIG_HAVE_ACPI_RESUME +Name(\_S1, Package(){0x1,0x0,0x0,0x0}) +#else +Name(\_S3, Package(){0x5,0x0,0x0,0x0}) +#endif +Name(\_S4, Package(){0x6,0x0,0x0,0x0}) +Name(\_S5, Package(){0x7,0x0,0x0,0x0}) + diff --git a/src/southbridge/intel/i82801ix/acpi/smbus.asl b/src/southbridge/intel/i82801ix/acpi/smbus.asl new file mode 100644 index 0000000..b6d2d6a --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/smbus.asl @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Intel SMBus Controller 0:1f.3 + +Device (SBUS) +{ + Name (_ADR, 0x001f0003) + + OperationRegion (SMBP, PCI_Config, 0x00, 0x100) + Field(SMBP, DWordAcc, NoLock, Preserve) + { + Offset(0x40), + , 2, + I2CE, 1 + } + + OperationRegion (SMBI, SystemIO, 0x400, 0x20) + Field (SMBI, ByteAcc, NoLock, Preserve) + { + HSTS, 8, // Host Status + , 8, + HCNT, 8, // Host Control + HCMD, 8, // Host Command + TXSA, 8, // Transmit Slave Address + DAT0, 8, // Host Data 0 + DAT1, 8, // Host Data 1 + HBDB, 8, // Host Block Data Byte + PECK, 8, // Packet Error Check + RXSA, 8, // Receive Slave Address + RXDA, 16, // Receive Slave Data + AUXS, 8, // Auxiliary Status + AUXC, 8, // Auxiliary Control + SLPC, 8, // SMLink Pin Control + SBPC, 8, // SMBus Pin Control + SSTS, 8, // Slave Status + SCMD, 8, // Slave Command + NADR, 8, // Notify Device Address + NDLB, 8, // Notify Data Low Byte + NDLH, 8, // Notify Data High Byte + } + +#ifdef ENABLE_SMBUS_METHODS + // Kill all SMBus communication + Method (KILL, 0, Serialized) + { + Or (HCNT, 0x02, HCNT) // Send Kill + Or (HSTS, 0xff, HSTS) // Clean Status + } + + // Check if last operation completed + // return Failure = 0, Success = 1 + Method (CMPL, 0, Serialized) + { + Store (4000, Local0) // Timeout 200ms in 50us steps + While (Local0) { + If (And(HSTS, 0x02)) { // Completion Status? + Return (1) // Operation Completed + } Else { + Stall (50) + Decrement (Local0) + If (LEqual(Local0, 0)) { + KILL() + } + } + } + + Return (0) // Failure + } + + + // Wait for SMBus to become ready + Method (SRDY, 0, Serialized) + { + Store (200, Local0) // Timeout 200ms + While (Local0) { + If (And(HSTS, 0x40)) { // IN_USE? + Sleep(1) // Wait 1ms + Decrement(Local0) // timeout-- + If (LEqual(Local0, 0)) { + Return (1) + } + } Else { + Store (0, Local0) // We're ready + } + } + + Store (4000, Local0) // Timeout 200ms (50us * 4000) + While (Local0) { + If (And (HSTS, 0x01)) { // Host Busy? + Stall(50) // Wait 50us + Decrement(Local0) // timeout-- + If (LEqual(Local0, 0)) { + KILL() + } + } Else { + Return (0) // Success + } + } + + Return (1) // Failure + } + + // SMBus Send Byte + // Arg0: Address + // Arg1: Data + // Return: 1 = Success, 0=Failure + + Method (SSXB, 2, Serialized) + { + + // Is the SMBus Controller Ready? + If (SRDY()) { + Return (0) + } + + // Send Byte + Store (0, I2CE) // SMBus Enable + Store (0xbf, HSTS) + Store (Arg0, TXSA) // Write Address + Store (Arg1, HCMD) // Write Data + + Store (0x48, HCNT) // Start + Byte Data Protocol + + If (CMPL()) { + Or (HSTS, 0xff, HSTS) // Clean up + Return (1) // Success + } + + Return (0) + } + + + // SMBus Receive Byte + // Arg0: Address + // Return: 0xffff = Failure, Data (8bit) = Success + + Method (SRXB, 2, Serialized) + { + + // Is the SMBus Controller Ready? + If (SRDY()) { + Return (0xffff) + } + + // Receive Byte + Store (0, I2CE) // SMBus Enable + Store (0xbf, HSTS) + Store (Or (Arg0, 1), TXSA) // Write Address + + Store (0x44, HCNT) // Start + + If (CMPL()) { + Or (HSTS, 0xff, HSTS) // Clean up + Return (DAT0) // Success + } + + Return (0xffff) + } + + + // SMBus Write Byte + // Arg0: Address + // Arg1: Command + // Arg2: Data + // Return: 1 = Success, 0=Failure + + Method (SWRB, 3, Serialized) + { + + // Is the SMBus Controller Ready? + If (SRDY()) { + Return (0) + } + + // Send Byte + Store (0, I2CE) // SMBus Enable + Store (0xbf, HSTS) + Store (Arg0, TXSA) // Write Address + Store (Arg1, HCMD) // Write Command + Store (Arg2, DAT0) // Write Data + + Store (0x48, HCNT) // Start + Byte Protocol + + If (CMPL()) { + Or (HSTS, 0xff, HSTS) // Clean up + Return (1) // Success + } + + Return (0) + } + + + // SMBus Read Byte + // Arg0: Address + // Arg1: Command + // Return: 0xffff = Failure, Data (8bit) = Success + + Method (SRDB, 2, Serialized) + { + + // Is the SMBus Controller Ready? + If (SRDY()) { + Return (0xffff) + } + + // Receive Byte + Store (0, I2CE) // SMBus Enable + Store (0xbf, HSTS) + Store (Or (Arg0, 1), TXSA) // Write Address + Store (Arg1, HCMD) // Command + + Store (0x48, HCNT) // Start + + If (CMPL()) { + Or (HSTS, 0xff, HSTS) // Clean up + Return (DAT0) // Success + } + + Return (0xffff) + } +#endif +} + diff --git a/src/southbridge/intel/i82801ix/acpi/usb.asl b/src/southbridge/intel/i82801ix/acpi/usb.asl new file mode 100644 index 0000000..8699c3f --- /dev/null +++ b/src/southbridge/intel/i82801ix/acpi/usb.asl @@ -0,0 +1,331 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Intel i82801I USB support */ + +// USB Controller 0:1d.0 + +Device (USB1) +{ + Name(_ADR, 0x001d0000) + + OperationRegion(U01P, PCI_Config, 0, 256) + Field(U01P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U1WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + Store (3, U1WE) + } Else { + Store (0, U1WE) + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } +} + + +// USB Controller 0:1d.1 + +Device (USB2) +{ + Name(_ADR, 0x001d0001) + + OperationRegion(U02P, PCI_Config, 0, 256) + Field(U02P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U2WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + Store (3, U2WE) + } Else { + Store (0, U2WE) + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + +} + + +// USB Controller 0:1d.2 + +Device (USB3) +{ + Name(_ADR, 0x001d0002) + + OperationRegion(U03P, PCI_Config, 0, 256) + Field(U03P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U3WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + Store (3, U3WE) + } Else { + Store (0, U3WE) + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + +} + + +// EHCI Controller 0:1d.7 + +Device (EHC1) +{ + Name(_ADR, 0x001d0007) + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0x00000000) + + // How many are there? + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} + + +// USB Controller 0:1a.0 + +Device (USB4) +{ + Name(_ADR, 0x001a0000) + + OperationRegion(U01P, PCI_Config, 0, 256) + Field(U01P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U1WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + Store (3, U1WE) + } Else { + Store (0, U1WE) + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } +} + + +// USB Controller 0:1a.1 + +Device (USB5) +{ + Name(_ADR, 0x001a0001) + + OperationRegion(U02P, PCI_Config, 0, 256) + Field(U02P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U2WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + Store (3, U2WE) + } Else { + Store (0, U2WE) + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + +} + + +// USB Controller 0:1a.2 + +Device (USB6) +{ + Name(_ADR, 0x001a0002) + + OperationRegion(U03P, PCI_Config, 0, 256) + Field(U03P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U3WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + Store (3, U3WE) + } Else { + Store (0, U3WE) + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + +} + + +// EHCI Controller 0:1a.7 + +Device (EHC2) +{ + Name(_ADR, 0x001a0007) + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0x00000000) + + // How many are there? + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} + + diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c new file mode 100644 index 0000000..39b0bd4 --- /dev/null +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> + +static void enable_spi_prefetch(void) +{ + u8 reg8; + device_t dev; + + dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); +} + +static void bootblock_southbridge_init(void) +{ + enable_spi_prefetch(); +} + diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h new file mode 100644 index 0000000..16c7f23 --- /dev/null +++ b/src/southbridge/intel/i82801ix/chip.h @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H +#define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H + +enum { + THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, + THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 +}; + +struct southbridge_intel_i82801ix_config { + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; + + /** + * GPI Routing configuration + * + * Only the lower two bits have a meaning: + * 00: No effect + * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + * 10: SCI (if corresponding GPIO_EN bit is also set) + * 11: reserved + */ + uint8_t gpi0_routing; + uint8_t gpi1_routing; + uint8_t gpi2_routing; + uint8_t gpi3_routing; + uint8_t gpi4_routing; + uint8_t gpi5_routing; + uint8_t gpi6_routing; + uint8_t gpi7_routing; + uint8_t gpi8_routing; + uint8_t gpi9_routing; + uint8_t gpi10_routing; + uint8_t gpi11_routing; + uint8_t gpi12_routing; + uint8_t gpi13_routing; + uint8_t gpi14_routing; + uint8_t gpi15_routing; + + uint32_t gpe0_en; + uint16_t alt_gp_smi_en; + + /* IDE configuration */ + uint32_t ide_legacy_combined; + uint32_t sata_ahci; /* If enabled, keep bit 2 of sata_enabled unset. */ + uint8_t sata_port_map : 6; + int sata_clock_request : 1; + int sata_traffic_monitor : 1; + + int c4onc3_enable:1; + int c5_enable : 1; + int c6_enable : 1; + + int throttle_duty : 3; + + /* Bit mask to tell whether a PCIe slot is implemented as slot. */ + int pcie_slot_implemented : 6; + + /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */ + struct { + uint8_t value : 8; + uint8_t scale : 2; + } pcie_power_limits[6]; +}; + +#endif /* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */ diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c new file mode 100644 index 0000000..73703b4 --- /dev/null +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include <northbridge/intel/gm45/gm45.h> +#include "i82801ix.h" + +/* VC1 Port Arbitration Table */ +static const u8 vc1_pat[] = { + 0x0f, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0f, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xf0, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0f, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0xf0, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x0f, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x0f, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0xf0, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0f, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0xf0, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, +}; +void i82801ix_dmi_setup(void) +{ + int i; + u32 reg32; + + RCBA32(RCBA_V1CAP) = (RCBA32(RCBA_V1CAP) & ~(0x7f<<16)) | (0x12<<16); + + RCBA32(0x0088) = 0x00109000; + RCBA16(0x01fc) = 0x060b; + RCBA32(0x01f4) = 0x86000040; + RCBA8 (0x0220) = 0x45; + RCBA32(0x2024) &= ~(1 << 7); + + + /* VC1 setup for isochronous transfers: */ + + /* Set VC1 virtual channel id to 1. */ + RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 24)) | (0x1 << 24); + /* Enable TC7 traffic on VC1. */ + RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7f << 1)) | (1 << 7); + /* Disable TC7-TC1 traffic on VC0. */ + RCBA32(RCBA_V0CTL) &= ~(0x7f << 1); + /* TC7-TC1 traffic on PCIe root ports will be disabled in pci driver. */ + + /* Set table type to time-based WRR. */ + RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 17)) | (0x4 << 17); + /* Program port arbitration table. */ + for (i = 0; i < sizeof(vc1_pat); ++i) + RCBA8(RCBA_PAT + i) = vc1_pat[i]; + /* Load port arbitration table. */ + RCBA32(RCBA_V1CTL) |= (1 << 16); + + /* Enable VC1. */ + RCBA32(RCBA_V1CTL) |= (1 << 31); + + + /* Setup RCRB: */ + + /* Set component id to 2 for southbridge, northbridge has id 1. */ + RCBA8(RCBA_ESD + 2) = 2; + /* Set target port number and target component id of the northbridge. */ + RCBA8(RCBA_ULD + 3) = 1; + RCBA8(RCBA_ULD + 2) = 1; + /* Set target rcrb base address, i.e. DMIBAR. */ + RCBA32(RCBA_ULBA) = DEFAULT_DMIBAR; + + /* Enable ASPM. */ + if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) { + reg32 = RCBA32(RCBA_DMC); + /* Enable mobile specific power saving (set this first). */ + reg32 = (reg32 & ~(3 << 10)) | (1 << 10); + RCBA32(RCBA_DMC) = reg32; + /* Enable DMI power savings. */ + reg32 |= (1 << 19); + RCBA32(RCBA_DMC) = reg32; + /* Advertise L0s and L1. */ + RCBA32(RCBA_LCAP) |= (3 << 10); + /* Enable L0s and L1. */ + RCBA32(RCBA_LCTL) |= (3 << 0); + } else { + /* Enable DMI power savings. */ + RCBA32(RCBA_DMC) |= (1 << 19); + /* Advertise L0s only. */ + RCBA32(RCBA_LCAP) = (RCBA32(RCBA_LCAP) & ~(3<<10)) | (1<<10); + /* Enable L0s only. */ + RCBA32(RCBA_LCTL) = (RCBA32(RCBA_LCTL) & ~(3<< 0)) | (1<< 0); + } +} + +/* Should be called after VC1 has been enabled on both sides. */ +void i82801ix_dmi_poll_vc1(void) +{ + int timeout; + + timeout = 0x7ffff; + printk(BIOS_DEBUG, "ICH9 waits for VC1 negotiation... "); + while ((RCBA32(RCBA_V1STS) & (1 << 1)) && --timeout) {} + if (!timeout) + printk(BIOS_DEBUG, "timeout!\n"); + else + printk(BIOS_DEBUG, "done.\n"); + + /* Check for x2 DMI link. */ + if (((RCBA16(RCBA_LSTS) >> 4) & 0x3f) == 2) { + printk(BIOS_DEBUG, "x2 DMI link detected.\n"); + RCBA32(0x2024) = (RCBA32(0x2024) & ~(7 << 21)) | (3 << 21); + RCBA16(0x20c4) |= (1 << 15); + RCBA16(0x20e4) |= (1 << 15); + /* TODO: Maybe we have to save and + restore these settings across S3. */ + } + + timeout = 0x7ffff; + printk(BIOS_DEBUG, "ICH9 waits for port arbitration table update... "); + while ((RCBA32(RCBA_V1STS) & (1 << 0)) && --timeout) {} + if (!timeout) + printk(BIOS_DEBUG, "timeout!\n"); + else + printk(BIOS_DEBUG, "done.\n"); +} + diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c new file mode 100644 index 0000000..66cdf03 --- /dev/null +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include "i82801ix.h" + +void i82801ix_early_init(void) +{ + const device_t d31f0 = PCI_DEV(0, 0x1f, 0); + + /* Set up RCBA. */ + pci_write_config32(d31f0, D31F0_RCBA, DEFAULT_RCBA | 1); + + /* Set up PMBASE. */ + pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1); + /* Enable PMBASE. */ + pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80); + + /* Set up GPIOBASE. */ + pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); + /* Enable GPIO. */ + pci_write_config8(d31f0, D31F0_GPIO_CNTL, + pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10); + + /* Reset watchdog. */ + outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */ + outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */ + + /* Enable upper 128bytes of CMOS. */ + RCBA32(0x3400) = (1 << 2); + + /* Initialize power manangement initialization + register early as it affects reboot behavior. */ + /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6 + and 0xe (required if ME is disabled but present), bit 31 locks it. + The other bits are 'must write'. */ + u8 reg8 = pci_read_config8(d31f0, 0xac); + reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); + pci_write_config8(d31f0, 0xac, reg8); + + /* TODO: If RTC power failed, reset RTC state machine + (set, then reset RTC 0x0b bit7) */ + + /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2) + before they get cleared. */ +} + diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c new file mode 100644 index 0000000..a2d8544 --- /dev/null +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include "i82801ix.h" +#include "smbus.h" + +void enable_smbus(void) +{ + device_t dev; + + /* Set the SMBus device statically. */ + dev = PCI_DEV(0x0, 0x1f, 0x3); + + /* Check to make sure we've got the right device. */ + if (pci_read_config16(dev, 0x2) != 0x2930) { + die("SMBus controller not found!"); + } + + /* Set SMBus I/O base. */ + pci_write_config32(dev, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + + /* Set SMBus enable. */ + pci_write_config8(dev, HOSTC, HST_EN); + + /* Set SMBus I/O space enable. */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + + /* Disable interrupt generation. */ + outb(0, SMBUS_IO_BASE + SMBHSTCTL); + + /* Clear any lingering errors, so transactions can run. */ + outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + print_debug("SMBus controller enabled.\n"); +} + +int smbus_read_byte(unsigned device, unsigned address) +{ + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); +} + diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c new file mode 100644 index 0000000..3f87915 --- /dev/null +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -0,0 +1,332 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <delay.h> +#include "i82801ix.h" + +#define HDA_ICII_REG 0x68 +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) + +typedef struct southbridge_intel_i82801ix_config config_t; + +static int set_bits(u32 port, u32 mask, u32 val) +{ + u32 reg32; + int count; + + /* Write (val & mask) to port */ + val &= mask; + reg32 = read32(port); + reg32 &= ~mask; + reg32 |= val; + write32(port, reg32); + + /* Wait for readback of register to + * match what was just written to it + */ + count = 50; + do { + /* Wait 1ms based on BKDG wait time */ + mdelay(1); + reg32 = read32(port); + reg32 &= mask; + } while ((reg32 != val) && --count); + + /* Timeout occurred */ + if (!count) + return -1; + return 0; +} + +static int codec_detect(u32 base) +{ + u32 reg32; + + /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 0) == -1) + goto no_codec; + + /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ + if (set_bits(base + 0x08, 1, 1) == -1) + goto no_codec; + + /* Read in Codec location (BAR + 0xe)[2..0]*/ + reg32 = read32(base + 0xe); + reg32 &= 0x0f; + if (!reg32) + goto no_codec; + + return reg32; + +no_codec: + /* Codec Not found */ + /* Put HDA back in reset (BAR + 0x8) [0] */ + set_bits(base + 0x08, 1, 0); + printk(BIOS_DEBUG, "Azalia: No codec!\n"); + return 0; +} + +const u32 * cim_verb_data = NULL; +u32 cim_verb_data_size = 0; +const u32 * pc_beep_verbs = NULL; +u32 pc_beep_verbs_size = 0; + +static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) +{ + int idx=0; + + while (idx < (cim_verb_data_size / sizeof(u32))) { + u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + if (cim_verb_data[idx] != viddid) { + idx += verb_size + 3; // skip verb + header + continue; + } + *verb = &cim_verb_data[idx+3]; + return verb_size; + } + + /* Not all codecs need to load another verb */ + return 0; +} + +/** + * Wait 50usec for the codec to indicate it is ready + * no response would imply that the codec is non-operative + */ + +static int wait_for_ready(u32 base) +{ + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + + while(timeout--) { + u32 reg32 = read32(base + HDA_ICII_REG); + if (!(reg32 & HDA_ICII_BUSY)) + return 0; + udelay(1); + } + + return -1; +} + +/** + * Wait 50usec for the codec to indicate that it accepted + * the previous command. No response would imply that the code + * is non-operative + */ + +static int wait_for_valid(u32 base) +{ + u32 reg32; + + /* Send the verb to the codec */ + reg32 = read32(base + 0x68); + reg32 |= (1 << 0) | (1 << 1); + write32(base + 0x68, reg32); + + /* Use a 50 usec timeout - the Linux kernel uses the + * same duration */ + + int timeout = 50; + while(timeout--) { + reg32 = read32(base + HDA_ICII_REG); + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == + HDA_ICII_VALID) + return 0; + udelay(1); + } + + return -1; +} + +static void codec_init(struct device *dev, u32 base, int addr) +{ + u32 reg32; + const u32 *verb; + u32 verb_size; + int i; + + printk(BIOS_DEBUG, "HD Audio: Initializing codec #%d\n", addr); + + /* 1 */ + if (wait_for_ready(base) == -1) + return; + + reg32 = (addr << 28) | 0x000f0000; + write32(base + 0x60, reg32); + + if (wait_for_valid(base) == -1) + return; + + reg32 = read32(base + 0x64); + + /* 2 */ + printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); + verb_size = find_verb(dev, reg32, &verb); + + if (!verb_size) { + printk(BIOS_DEBUG, "Azalia: No verb!\n"); + return; + } + printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); + + /* 3 */ + for (i = 0; i < verb_size; i++) { + if (wait_for_ready(base) == -1) + return; + + write32(base + 0x60, verb[i]); + + if (wait_for_valid(base) == -1) + return; + } + printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); +} + +static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +{ + int i; + for (i = 2; i >= 0; i--) { + if (codec_mask & (1 << i)) + codec_init(dev, base, i); + } + + for (i = 0; i < pc_beep_verbs_size; i++) { + if (wait_for_ready(base) == -1) + return; + + write32(base + 0x60, pc_beep_verbs[i]); + + if (wait_for_valid(base) == -1) + return; + } +} + +static void azalia_init(struct device *dev) +{ + u32 base; + struct resource *res; + u32 codec_mask; + u8 reg8; + u32 reg32; + +#if CONFIG_MMCONF_SUPPORT + // ESD + reg32 = pci_mmio_read_config32(dev, 0x134); + reg32 &= 0xff00ffff; + reg32 |= (2 << 16); + pci_mmio_write_config32(dev, 0x134, reg32); + + // Link1 description + reg32 = pci_mmio_read_config32(dev, 0x140); + reg32 &= 0xff00ffff; + reg32 |= (2 << 16); + pci_mmio_write_config32(dev, 0x140, reg32); + + // Port VC0 Resource Control Register + reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 &= 0xffffff00; + reg32 |= 1; + pci_mmio_write_config32(dev, 0x114, reg32); + + // VCi traffic class + reg8 = pci_mmio_read_config8(dev, 0x44); + reg8 |= (7 << 0); // TC7 + pci_mmio_write_config8(dev, 0x44, reg8); + + // VCi Resource Control + reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 |= (1 << 31); + reg32 |= (1 << 24); // VCi ID + reg32 |= (0x80 << 0); // VCi map + pci_mmio_write_config32(dev, 0x120, reg32); +#else +#error ICH9 Azalia required CONFIG_MMCONF_SUPPORT +#endif + + /* Set Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + + reg8 = pci_read_config8(dev, 0x4d); // Docking Status + reg8 &= ~(1 << 7); // Docking not supported + pci_write_config8(dev, 0x4d, reg8); + + /* Lock some R/WO bits by writing their current value. */ + reg32 = pci_read_config32(dev, 0x74); + pci_write_config32(dev, 0x74, reg32); + + res = find_resource(dev, 0x10); + if (!res) + return; + + // NOTE this will break as soon as the Azalia get's a bar above + // 4G. Is there anything we can do about it? + base = (u32)res->base; + printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + codec_mask = codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); + codecs_init(dev, base, codec_mask); + } +} + +static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations azalia_pci_ops = { + .set_subsystem = azalia_set_subsystem, +}; + +static struct device_operations azalia_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = azalia_init, + .scan_bus = 0, + .ops_pci = &azalia_pci_ops, +}; + +/* ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M */ +static const struct pci_driver i82801ix_azalia __pci_driver = { + .ops = &azalia_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x293e, +}; + diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c new file mode 100644 index 0000000..99e7ca1 --- /dev/null +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -0,0 +1,264 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * (Written by Nico Huber <nico.huber(a)secunet.com> for secunet) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include "i82801ix.h" + +typedef struct southbridge_intel_i82801ix_config config_t; + +static void i82801ix_enable_device(device_t dev) +{ + u32 reg32; + + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); +} + +static void i82801ix_early_settings(const config_t *const info) +{ + /* Program FERR# as processor break event indicator. */ + RCBA32(0x3410) |= (1 << 6); + /* BIOS must program... */ + RCBA32(0x3430) = (RCBA32(0x3430) & ~(0x3 << 0)) | (0x2 << 0); + RCBA32(0x3418) |= (1 << 0); + RCBA32(0x350c) = (RCBA32(0x350c) & ~(0x3 << 26)) | (0x2 << 26); + RCBA32(0x2034) = (RCBA32(0x2034) & ~(0xf << 16)) | (0x5 << 16); + RCBA32(0x0f20) = (RCBA32(0x0f20) & ~(0xf << 16)) | (0x5 << 16); + RCBA32(0x1d40) |= (1 << 0); + RCBA32(0x352c) |= (3 << 16); +} + +static void i82801ix_pcie_init(const config_t *const info) +{ + device_t pciePort[6]; + int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */ + u32 reg32; + + /* PCIe - BIOS must program... */ + for (i = 0; i < 6; ++i) { + pciePort[i] = dev_find_slot(0, PCI_DEVFN(0x1c, i)); + if (!pciePort[i]) { + printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); + die(" is not listed in devicetree.\n"); + } +#if CONFIG_MMCONF_SUPPORT + reg32 = pci_mmio_read_config32(pciePort[i], 0x300); + pci_mmio_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); + pci_mmio_write_config8(pciePort[i], 0x324, 0x40); +#else +#error "MMIO needed for ICH9 PCIe" +#endif + } + + if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) { + for (i = 0; i < 6; ++i) { + if (pciePort[i]->enabled) { + reg32 = pci_read_config32(pciePort[i], 0xe8); + reg32 |= 1; + pci_write_config32(pciePort[i], 0xe8, reg32); + } + } + } + + for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { + /* Only for the top disabled ports. */ +#if CONFIG_MMCONF_SUPPORT + reg32 = pci_mmio_read_config32(pciePort[i], 0x300); + reg32 |= 0x3 << 16; + pci_mmio_write_config32(pciePort[i], 0x300, reg32); +#else +#error "MMIO needed for ICH9 PCIe" +#endif + } + + /* Set slot implemented, slot number and slot power limits. */ + for (i = 0; i < 6; ++i) { + const device_t dev = pciePort[i]; + u32 xcap = pci_read_config32(dev, D28Fx_XCAP); + if (info->pcie_slot_implemented & (1 << i)) + xcap |= PCI_EXP_FLAGS_SLOT; + else + xcap &= ~PCI_EXP_FLAGS_SLOT; + pci_write_config32(dev, D28Fx_XCAP, xcap); + + if (info->pcie_slot_implemented & (1 << i)) { + u32 slcap = pci_read_config32(dev, D28Fx_SLCAP); + slcap &= ~(0x1fff << 19); + slcap |= (slot_number++ << 19); + slcap &= ~(0x0003 << 16); + slcap |= (info->pcie_power_limits[i].scale << 16); + slcap &= ~(0x00ff << 7); + slcap |= (info->pcie_power_limits[i].value << 7); + pci_write_config32(dev, D28Fx_SLCAP, slcap); + } + } + + /* Lock R/WO ASPM support bits. */ + for (i = 0; i < 6; ++i) { + reg32 = pci_read_config32(pciePort[i], 0x4c); + pci_write_config32(pciePort[i], 0x4c, reg32); + } +} + +static void i82801ix_ehci_init(void) +{ + const device_t pciEHCI1 = dev_find_slot(0, PCI_DEVFN(0x1d, 7)); + if (!pciEHCI1) + die("EHCI controller (00:1d.7) not listed in devicetree.\n"); + const device_t pciEHCI2 = dev_find_slot(0, PCI_DEVFN(0x1a, 7)); + if (!pciEHCI2) + die("EHCI controller (00:1a.7) not listed in devicetree.\n"); + + u32 reg32; + + /* TODO: Maybe we have to save and + restore these settings across S3. */ + reg32 = pci_read_config32(pciEHCI1, 0xfc); + pci_write_config32(pciEHCI1, 0xfc, (reg32 & ~(3 << 2)) | + (1 << 29) | (1 << 17) | (2 << 2)); + reg32 = pci_read_config32(pciEHCI2, 0xfc); + pci_write_config32(pciEHCI2, 0xfc, (reg32 & ~(3 << 2)) | + (1 << 29) | (1 << 17) | (2 << 2)); +} + +static int i82801ix_function_disabled(const unsigned devfn) +{ + const struct device *const dev = dev_find_slot(0, devfn); + if (!dev) { + printk(BIOS_EMERG, + "PCI device 00:%x.%x", + PCI_SLOT(devfn), PCI_FUNC(devfn)); + die(" is not listed in devicetree.\n"); + } + return !dev->enabled; +} + +static void i82801ix_hide_functions(void) +{ + int i; + u32 reg32; + + /* FIXME: This works pretty good if the devicetree is consistent. But + some functions have to be disabled in right order and/or have + other constraints. */ + + if (i82801ix_function_disabled(PCI_DEVFN(0x19, 0))) + RCBA32(RCBA_BUC) |= BUC_LAND; + + reg32 = RCBA32(RCBA_FD); + struct { + int devfn; + u32 mask; + } functions[] = { + { PCI_DEVFN(0x1a, 0), FD_U4D }, /* UHCI #4 */ + { PCI_DEVFN(0x1a, 1), FD_U5D }, /* UHCI #5 */ + { PCI_DEVFN(0x1a, 2), FD_U6D }, /* UHCI #6 */ + { PCI_DEVFN(0x1a, 7), FD_EHCI2D }, /* EHCI #2 */ + { PCI_DEVFN(0x1b, 0), FD_HDAD }, /* HD Audio */ + { PCI_DEVFN(0x1c, 0), FD_PE1D }, /* PCIe #1 */ + { PCI_DEVFN(0x1c, 1), FD_PE2D }, /* PCIe #2 */ + { PCI_DEVFN(0x1c, 2), FD_PE3D }, /* PCIe #3 */ + { PCI_DEVFN(0x1c, 3), FD_PE4D }, /* PCIe #4 */ + { PCI_DEVFN(0x1c, 4), FD_PE5D }, /* PCIe #5 */ + { PCI_DEVFN(0x1c, 5), FD_PE6D }, /* PCIe #6 */ + { PCI_DEVFN(0x1d, 0), FD_U1D }, /* UHCI #1 */ + { PCI_DEVFN(0x1d, 1), FD_U2D }, /* UHCI #2 */ + { PCI_DEVFN(0x1d, 2), FD_U3D }, /* UHCI #3 */ + { PCI_DEVFN(0x1d, 7), FD_EHCI1D }, /* EHCI #1 */ + { PCI_DEVFN(0x1f, 0), FD_LBD }, /* LPC */ + { PCI_DEVFN(0x1f, 2), FD_SAD1 }, /* SATA #1 */ + { PCI_DEVFN(0x1f, 3), FD_SD }, /* SMBus */ + { PCI_DEVFN(0x1f, 5), FD_SAD2 }, /* SATA #2 */ + { PCI_DEVFN(0x1f, 6), FD_TTD }, /* Thermal Throttle */ + }; + for (i = 0; i < ARRAY_SIZE(functions); ++i) { + if (i82801ix_function_disabled(functions[i].devfn)) + reg32 |= functions[i].mask; + } + RCBA32(RCBA_FD) = reg32; + RCBA32(RCBA_FD) |= (1 << 0); /* BIOS must write this... */ + RCBA32(RCBA_FDSW) |= (1 << 7); /* Lock function-disable? */ + + /* Hide PCIe root port PCI functions. RPFN is partially R/WO. */ + reg32 = RCBA32(RCBA_RPFN); + for (i = 0; i < 6; ++i) { + if (i82801ix_function_disabled(PCI_DEVFN(0x1c, i))) + reg32 |= (1 << ((i * 4) + 3)); + } + RCBA32(RCBA_RPFN) = reg32; + + /* Lock R/WO UHCI controller #6 remapping. */ + RCBA32(RCBA_MAP) = RCBA32(RCBA_MAP); +} + +static void i82801ix_init(void *chip_info) +{ + const config_t *const info = (config_t *)chip_info; + + printk(BIOS_DEBUG, "Initializing i82801ix southbridge...\n"); + + i82801ix_early_settings(info); + + /* PCI Express setup. */ + i82801ix_pcie_init(info); + + /* EHCI configuration. */ + i82801ix_ehci_init(); + + /* Now hide internal functions. We can't access them after this. */ + i82801ix_hide_functions(); + + /* Reset watchdog timer. */ +#if !CONFIG_HAVE_SMI_HANDLER + outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ +#endif + outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ + +#if CONFIG_HAVE_ACPI_RESUME + switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { + case SKPAD_NORMAL_BOOT_MAGIC: + printk(BIOS_DEBUG, "Normal boot.\n"); + acpi_slp_type=0; + break; + case SKPAD_ACPI_S3_MAGIC: + printk(BIOS_DEBUG, "S3 Resume.\n"); + acpi_slp_type=3; + break; + default: + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + acpi_slp_type=0; + break; + } +#endif +} + +struct chip_operations southbridge_intel_i82801ix_ops = { + CHIP_NAME("Intel ICH9/ICH9-M (82801Ix) Series Southbridge") + .enable_dev = i82801ix_enable_device, + .init = i82801ix_init, +}; diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h new file mode 100644 index 0000000..5b963e6 --- /dev/null +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H +#define SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H + +#ifndef __ACPI__ +#ifndef __ASSEMBLER__ +#include "chip.h" +#endif +#endif + +#define DEFAULT_TBAR 0xfed1b000 +#define DEFAULT_RCBA 0xfed1c000 +#define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ +#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) +#define DEFAULT_GPIOBASE 0x00000580 + + +#define APM_CNT 0xb2 + +#define PM1_STS 0x00 +#define PWRBTN_STS (1 << 8) +#define RTC_STS (1 << 10) +#define PM1_EN 0x02 +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define PM1_CNT 0x04 +#define SCI_EN (1 << 0) +#define PM_LV2 0x14 +#define PM_LV3 0x15 +#define PM_LV4 0x16 +#define PM_LV5 0x17 +#define PM_LV6 0x18 +#define GPE0_STS 0x20 +#define SMI_EN 0x30 +#define PERIODIC_EN (1 << 14) +#define TCO_EN (1 << 13) +#define APMC_EN (1 << 5) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define ALT_GP_SMI_EN 0x38 +#define ALT_GP_SMI_STS 0x3a + + +#define DEBUG_PERIODIC_SMIS 0 + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + + +/* D31:F0 LPC bridge */ +#define D31F0_PMBASE 0x40 +#define D31F0_ACPI_CNTL 0x44 +#define D31F0_GPIO_BASE 0x48 +#define D31F0_GPIO_CNTL 0x4c +#define D31F0_PIRQA_ROUT 0x60 +#define D31F0_PIRQB_ROUT 0x61 +#define D31F0_PIRQC_ROUT 0x62 +#define D31F0_PIRQD_ROUT 0x63 +#define D31F0_SERIRQ_CNTL 0x64 +#define D31F0_PIRQE_ROUT 0x68 +#define D31F0_PIRQF_ROUT 0x69 +#define D31F0_PIRQG_ROUT 0x6a +#define D31F0_PIRQH_ROUT 0x6b +#define D31F0_LPC_IODEC 0x80 +#define D31F0_LPC_EN 0x82 +#define D31F0_GEN1_DEC 0x84 +#define D31F0_GEN_PMCON_1 0xa0 +#define D31F0_GEN_PMCON_3 0xa4 +#define D31F0_C5_EXIT_TIMING 0xa8 +#define D31F0_CxSTATE_CNF 0xa9 +#define D31F0_C4TIMING_CNT 0xaa +#define D31F0_GPIO_ROUT 0xb8 +#define D31F0_RCBA 0xf0 + +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + + +/* D31:F2 SATA */ +#define D31F2_IDE_TIM_PRI 0x40 +#define D31F2_IDE_TIM_SEC 0x42 +#define D31F2_SIDX 0xa0 +#define D31F2_SDAT 0xa4 + + +/* D30:F0 PCI-to-PCI bridge */ +#define D30F0_SMLT 0x1b + + +/* D28:F0-5 PCIe root ports */ +#define D28Fx_XCAP 0x42 +#define D28Fx_SLCAP 0x54 + + +#define SMBUS_IO_BASE 0x0400 + +/* PCI Configuration Space (D31:F3): SMBus */ +#define SMB_BASE 0x20 +#define HOSTC 0x40 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) + + +#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) +#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) +#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) + +#define RCBA_V0CTL 0x0014 +#define RCBA_V1CAP 0x001c +#define RCBA_V1CTL 0x0020 +#define RCBA_V1STS 0x0026 +#define RCBA_PAT 0x0030 +#define RCBA_ESD 0x0104 +#define RCBA_ULD 0x0110 +#define RCBA_ULBA 0x0118 +#define RCBA_LCAP 0x01a4 +#define RCBA_LCTL 0x01a8 +#define RCBA_LSTS 0x01aa +#define RCBA_DMIC 0x0234 +#define RCBA_RPFN 0x0238 +#define RCBA_DMC 0x2010 +#define RCBA_HPTC 0x3404 +#define RCBA_BUC 0x3414 +#define RCBA_FD 0x3418 /* Function Disable, see below. */ +#define RCBA_CG 0x341c +#define RCBA_FDSW 0x3420 +#define RCBA_MAP 0x35f0 /* UHCI cotroller #6 remapping */ + +#define BUC_LAND (1 << 5) /* LAN */ +#define FD_SAD2 (1 << 25) /* SATA #2 */ +#define FD_TTD (1 << 24) /* Thermal Throttle */ +#define FD_PE6D (1 << 21) /* PCIe root port 6 */ +#define FD_PE5D (1 << 20) /* PCIe root port 5 */ +#define FD_PE4D (1 << 19) /* PCIe root port 4 */ +#define FD_PE3D (1 << 18) /* PCIe root port 3 */ +#define FD_PE2D (1 << 17) /* PCIe root port 2 */ +#define FD_PE1D (1 << 16) /* PCIe root port 1 */ +#define FD_EHCI1D (1 << 15) /* EHCI #1 */ +#define FD_LBD (1 << 14) /* LPC bridge */ +#define FD_EHCI2D (1 << 13) /* EHCI #2 */ +#define FD_U5D (1 << 12) /* UHCI #5 */ +#define FD_U4D (1 << 11) /* UHCI #4 */ +#define FD_U3D (1 << 10) /* UHCI #3 */ +#define FD_U2D (1 << 9) /* UHCI #2 */ +#define FD_U1D (1 << 8) /* UHCI #1 */ +#define FD_U6D (1 << 7) /* UHCI #6 */ +#define FD_HDAD (1 << 4) /* HD audio */ +#define FD_SD (1 << 3) /* SMBus */ +#define FD_SAD1 (1 << 2) /* SATA #1 */ + + +#define SKPAD_ACPI_S3_MAGIC 0xcafed00d +#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe + + +#ifndef __ACPI__ +#ifndef __ASSEMBLER__ + +static inline int lpc_is_mobile(const u16 devid) +{ + return (devid == 0x2917) || (devid == 0x2919); +} +#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) + +#if defined(__PRE_RAM__) +void enable_smbus(void); +int smbus_read_byte(unsigned device, unsigned address); +void i82801ix_early_init(void); +void i82801ix_dmi_setup(void); +void i82801ix_dmi_poll_vc1(void); +#endif + +#endif +#endif + +#endif diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c new file mode 100644 index 0000000..3c91cc2 --- /dev/null +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -0,0 +1,566 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include <pc80/isa-dma.h> +#include <pc80/i8259.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <cpu/cpu.h> +#include <cpu/x86/smm.h> +#include "i82801ix.h" + +#define NMI_OFF 0 + +#define ENABLE_ACPI_MODE_IN_COREBOOT 0 +#define TEST_SMM_FLASH_LOCKDOWN 0 + +typedef struct southbridge_intel_i82801ix_config config_t; + +static void i82801ix_enable_apic(struct device *dev) +{ + u8 dummy; + u32 reg32; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + + /* Enable IOAPIC. Keep APIC Range Select at zero. */ + RCBA8(0x31ff) = 0x03; + /* We have to read 0x31ff back if bit0 changed. */ + dummy = RCBA8(0x31ff); + + /* Lock maximum redirection entries (MRE), R/WO register. */ + *ioapic_index = 0x01; + reg32 = *ioapic_data; + *ioapic_index = 0x01; + *ioapic_data = reg32; + + setup_ioapic(IO_APIC_ADDR, 2); /* ICH7 code uses id 2. */ +} + +static void i82801ix_enable_serial_irqs(struct device *dev) +{ + /* Set packet length and toggle silent mode bit for one frame. */ + pci_write_config8(dev, D31F0_SERIRQ_CNTL, + (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); +} + +/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ + +static void i82801ix_pirq_init(device_t dev) +{ + device_t irq_dev; + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + pci_write_config8(dev, D31F0_PIRQA_ROUT, config->pirqa_routing); + pci_write_config8(dev, D31F0_PIRQB_ROUT, config->pirqb_routing); + pci_write_config8(dev, D31F0_PIRQC_ROUT, config->pirqc_routing); + pci_write_config8(dev, D31F0_PIRQD_ROUT, config->pirqd_routing); + + pci_write_config8(dev, D31F0_PIRQE_ROUT, config->pirqe_routing); + pci_write_config8(dev, D31F0_PIRQF_ROUT, config->pirqf_routing); + pci_write_config8(dev, D31F0_PIRQG_ROUT, config->pirqg_routing); + pci_write_config8(dev, D31F0_PIRQH_ROUT, config->pirqh_routing); + + /* Eric Biederman once said we should let the OS do this. + * I am not so sure anymore he was right. + */ + + for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + u8 int_pin=0, int_line=0; + + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; + + int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + + switch (int_pin) { + case 1: /* INTA# */ int_line = config->pirqa_routing; break; + case 2: /* INTB# */ int_line = config->pirqb_routing; break; + case 3: /* INTC# */ int_line = config->pirqc_routing; break; + case 4: /* INTD# */ int_line = config->pirqd_routing; break; + } + + if (!int_line) + continue; + + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } +} + +static void i82801ix_gpi_routing(device_t dev) +{ + /* Get the chip configuration */ + config_t *config = dev->chip_info; + u32 reg32 = 0; + + /* An array would be much nicer here, or some + * other method of doing this. + */ + reg32 |= (config->gpi0_routing & 0x03) << 0; + reg32 |= (config->gpi1_routing & 0x03) << 2; + reg32 |= (config->gpi2_routing & 0x03) << 4; + reg32 |= (config->gpi3_routing & 0x03) << 6; + reg32 |= (config->gpi4_routing & 0x03) << 8; + reg32 |= (config->gpi5_routing & 0x03) << 10; + reg32 |= (config->gpi6_routing & 0x03) << 12; + reg32 |= (config->gpi7_routing & 0x03) << 14; + reg32 |= (config->gpi8_routing & 0x03) << 16; + reg32 |= (config->gpi9_routing & 0x03) << 18; + reg32 |= (config->gpi10_routing & 0x03) << 20; + reg32 |= (config->gpi11_routing & 0x03) << 22; + reg32 |= (config->gpi12_routing & 0x03) << 24; + reg32 |= (config->gpi13_routing & 0x03) << 26; + reg32 |= (config->gpi14_routing & 0x03) << 28; + reg32 |= (config->gpi15_routing & 0x03) << 30; + + pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); +} + +static void i82801ix_power_options(device_t dev) +{ + u8 reg8; + u16 reg16, pmbase; + u32 reg32; + const char *state; + /* Get the chip configuration */ + config_t *config = dev->chip_info; + + int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int nmi_option; + + /* BIOS must program... */ + reg32 = pci_read_config32(dev, 0xac); + pci_write_config32(dev, 0xac, reg32 | (1 << 30) | (3 << 8)); + + /* Which state do we want to goto after g3 (power restored)? + * 0 == S0 Full On + * 1 == S5 Soft Off + * + * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. + */ + if (get_option(&pwr_on, "power_on_after_fail") < 0) + pwr_on = MAINBOARD_POWER_ON; + + reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); + reg8 &= 0xfe; + switch (pwr_on) { + case MAINBOARD_POWER_OFF: + reg8 |= 1; + state = "off"; + break; + case MAINBOARD_POWER_ON: + reg8 &= ~1; + state = "on"; + break; + case MAINBOARD_POWER_KEEP: + reg8 &= ~1; + state = "state keep"; + break; + default: + state = "undefined"; + } + + reg8 |= (3 << 4); /* avoid #S4 assertions */ + reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */ + + pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8); + printk(BIOS_INFO, "Set power %s after power failure.\n", state); + + /* Set up NMI on errors. */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ + // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ + reg8 |= (1 << 2); /* PCI SERR# Disable for now */ + outb(reg8, 0x61); + + reg8 = inb(0x74); /* Read from 0x74 as 0x70 is write only. */ + nmi_option = NMI_OFF; + get_option(&nmi_option, "nmi"); + if (nmi_option) { + printk(BIOS_INFO, "NMI sources enabled.\n"); + reg8 &= ~(1 << 7); /* Set NMI. */ + } else { + printk(BIOS_INFO, "NMI sources disabled.\n"); + reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ + } + outb(reg8, 0x70); + + /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ + reg16 = pci_read_config16(dev, D31F0_GEN_PMCON_1); + reg16 &= ~(3 << 0); // SMI# rate 1 minute + reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only + reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only + reg16 |= (1 << 5); // CPUSLP_EN Desktop only + + if (config->c4onc3_enable) + reg16 |= (1 << 7); + + // another laptop wants this? + // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only + reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only +#if DEBUG_PERIODIC_SMIS + /* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using + * periodic SMIs. + */ + reg16 |= (3 << 0); // Periodic SMI every 8s +#endif + if (config->c5_enable) + reg16 |= (1 << 11); /* Enable C5, C6 and PMSYNC# */ + pci_write_config16(dev, D31F0_GEN_PMCON_1, reg16); + + /* Set exit timings for C5/C6. */ + if (config->c5_enable) { + reg8 = pci_read_config8(dev, D31F0_C5_EXIT_TIMING); + reg8 &= ~((7 << 3) | (7 << 0)); + if (config->c6_enable) + reg8 |= (5 << 3) | (3 << 0); /* 38-44us PMSYNC# to STPCLK#, + 95-102us DPRSTP# to STP_CPU# */ + else + reg8 |= (0 << 3) | (1 << 0); /* 16-17us PMSYNC# to STPCLK#, + 34-40us DPRSTP# to STP_CPU# */ + pci_write_config8(dev, D31F0_C5_EXIT_TIMING, reg8); + } + + // Set the board's GPI routing. + i82801ix_gpi_routing(dev); + + pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + + outl(config->gpe0_en, pmbase + 0x28); + outw(config->alt_gp_smi_en, pmbase + 0x38); + + /* Set up power management block and determine sleep mode */ + reg16 = inw(pmbase + 0x00); /* PM1_STS */ + outw(reg16, pmbase + 0x00); /* Clear status bits. At least bit11 (power + button override) must be cleared or SCI + will be constantly fired and OSPM must + not know about it (ACPI spec says to + ignore the bit). */ + reg32 = inl(pmbase + 0x04); // PM1_CNT + reg32 &= ~(7 << 10); // SLP_TYP + outl(reg32, pmbase + 0x04); + + /* Set duty cycle for hardware throttling (defaults to 0x0: 50%). */ + reg32 = inl(pmbase + 0x10); + reg32 &= ~(7 << 5); + reg32 |= (config->throttle_duty & 7) << 5; + outl(reg32, pmbase + 0x10); +} + +static void i82801ix_configure_cstates(device_t dev) +{ + u8 reg8; + + reg8 = pci_read_config8(dev, D31F0_CxSTATE_CNF); + reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown + pci_write_config8(dev, D31F0_CxSTATE_CNF, reg8); + + // Set Deeper Sleep configuration to recommended values + reg8 = pci_read_config8(dev, D31F0_C4TIMING_CNT); + reg8 &= 0xf0; + reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us + reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us + pci_write_config8(dev, D31F0_C4TIMING_CNT, reg8); + + /* We could enable slow-C4 exit here, if someone needs it? */ +} + +static void i82801ix_rtc_init(struct device *dev) +{ + u8 reg8; + int rtc_failed; + + reg8 = pci_read_config8(dev, D31F0_GEN_PMCON_3); + rtc_failed = reg8 & RTC_BATTERY_DEAD; + if (rtc_failed) { + reg8 &= ~RTC_BATTERY_DEAD; + pci_write_config8(dev, D31F0_GEN_PMCON_3, reg8); + } + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); + + rtc_init(rtc_failed); +} + +static void enable_hpet(void) +{ + u32 reg32; + + /* Move HPET to default address 0xfed00000 and enable it */ + reg32 = RCBA32(RCBA_HPTC); + reg32 |= (1 << 7); // HPET Address Enable + reg32 &= ~(3 << 0); + RCBA32(RCBA_HPTC) = reg32; +} + +static void enable_clock_gating(void) +{ + u32 reg32; + + /* Enable DMI dynamic clock gating. */ + RCBA32(RCBA_DMIC) |= 3; + + /* Enable Clock Gating for most devices. */ + reg32 = RCBA32(RCBA_CG); + reg32 |= (1 << 31); /* LPC dynamic clock gating */ + /* USB UHCI dynamic clock gating: */ + reg32 |= (1 << 29) | (1 << 28); + /* SATA dynamic clock gating [0-3]: */ + reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); + reg32 |= (1 << 23); /* LAN static clock gating (if LAN disabled) */ + reg32 |= (1 << 22); /* HD audio dynamic clock gating */ + reg32 &= ~(1 << 21); /* No HD audio static clock gating */ + reg32 &= ~(1 << 20); /* No USB EHCI static clock gating */ + reg32 |= (1 << 19); /* USB EHCI dynamic clock gating */ + /* More SATA dynamic clock gating [4-5]: */ + reg32 |= (1 << 18) | (1 << 17); + reg32 |= (1 << 16); /* PCI dynamic clock gating */ + /* PCIe, DMI dynamic clock gating: */ + reg32 |= (1 << 4) | (1 << 3) | (1 << 2) | (1 << 1); + reg32 |= (1 << 0); /* PCIe root port static clock gating */ + RCBA32(RCBA_CG) = reg32; + + /* Enable SPI dynamic clock gating. */ + RCBA32(0x38c0) |= 7; +} + +#if CONFIG_HAVE_SMI_HANDLER +static void i82801ix_lock_smm(struct device *dev) +{ +#if TEST_SMM_FLASH_LOCKDOWN + u8 reg8; +#endif + + if (acpi_slp_type != 3) { +#if ENABLE_ACPI_MODE_IN_COREBOOT + printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode + printk(BIOS_DEBUG, "done.\n"); +#else + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); +#endif + } else { + printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); + } + /* Don't allow evil boot loaders, kernels, or + * userspace applications to deceive us: + */ + smm_lock(); + +#if TEST_SMM_FLASH_LOCKDOWN + /* Now try this: */ + printk(BIOS_DEBUG, "Locking BIOS to RO... "); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + (reg8&1)?"rw":"ro"); + reg8 &= ~(1 << 0); /* clear BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + reg8 |= (1 << 1); /* set BLE */ + pci_write_config8(dev, 0xdc, reg8); + printk(BIOS_DEBUG, "ok.\n"); + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + (reg8&1)?"rw":"ro"); + + printk(BIOS_DEBUG, "Writing:\n"); + *(volatile u8 *)0xfff00000 = 0x00; + printk(BIOS_DEBUG, "Testing:\n"); + reg8 |= (1 << 0); /* set BIOSWE */ + pci_write_config8(dev, 0xdc, reg8); + + reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + (reg8&1)?"rw":"ro"); + printk(BIOS_DEBUG, "Done.\n"); +#endif +} +#endif + +static void lpc_init(struct device *dev) +{ + printk(BIOS_DEBUG, "i82801ix: lpc_init\n"); + + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, 0x000f); + + /* IO APIC initialization. */ + i82801ix_enable_apic(dev); + + i82801ix_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + i82801ix_pirq_init(dev); + + /* Setup power options. */ + i82801ix_power_options(dev); + + /* Configure Cx state registers */ + if (LPC_IS_MOBILE(dev)) + i82801ix_configure_cstates(dev); + + /* Initialize the real time clock. */ + i82801ix_rtc_init(dev); + + /* Initialize ISA DMA. */ + isa_dma_init(); + + /* Initialize the High Precision Event Timers, if present. */ + enable_hpet(); + + /* Initialize Clock Gating */ + enable_clock_gating(); + + setup_i8259(); + + /* The OS should do this? */ + /* Interrupt 9 should be level triggered (SCI) */ + i8259_configure_irq_trigger(9, 1); + +#if CONFIG_HAVE_SMI_HANDLER + i82801ix_lock_smm(dev); +#endif +} + +static void i82801ix_lpc_read_resources(device_t dev) +{ + /* + * I/O Resources + * + * 0x0000 - 0x000f....ISA DMA + * 0x0010 - 0x001f....ISA DMA aliases + * 0x0020 ~ 0x003d....PIC + * 0x002e - 0x002f....Maybe Super I/O + * 0x0040 - 0x0043....Timer + * 0x004e - 0x004f....Maybe Super I/O + * 0x0050 - 0x0053....Timer aliases + * 0x0061.............NMI_SC + * 0x0070.............NMI_EN (readable in alternative access mode) + * 0x0070 - 0x0077....RTC + * 0x0080 - 0x008f....ISA DMA + * 0x0090 ~ 0x009f....ISA DMA aliases + * 0x0092.............Fast A20 and Init + * 0x00a0 ~ 0x00bd....PIC + * 0x00b2 - 0x00b3....APM + * 0x00c0 ~ 0x00de....ISA DMA + * 0x00c1 ~ 0x00df....ISA DMA aliases + * 0x00f0.............Coprocessor Error + * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit) + * 0x04d0 - 0x04d1....PIC + * 0x0500 - 0x057f....PM (DEFAULT_PMBASE) + * 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE) + * 0x05c0 - 0x05ff....SB GPIO cont. (mobile only) + * 0x0cf8 - 0x0cff....PCI + * 0x0cf9.............Reset Control + */ + + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = i82801ix_lpc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpc_init, + .scan_bus = scan_static_bus, + .ops_pci = &pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + 0x2912, /* ICH9DH */ + 0x2914, /* ICH9DO */ + 0x2916, /* ICH9R */ + 0x2918, /* ICH9 */ + 0x2917, /* ICH9M-E */ + 0x2919, /* ICH9M */ + 0 +}; + +static const struct pci_driver ich9_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; + diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h new file mode 100644 index 0000000..03f8de7 --- /dev/null +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +typedef struct { + /* Miscellaneous */ + u16 osys; /* 0x00 - Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 prm0; /* 0x03 - SMI function call parameter */ + u8 prm1; /* 0x04 - SMI function call parameter */ + u8 scif; /* 0x05 - SCI function call (via _L00) */ + u8 prm2; /* 0x06 - SCI function call parameter */ + u8 prm3; /* 0x07 - SCI function call parameter */ + u8 lckf; /* 0x08 - Global Lock function for EC */ + u8 prm4; /* 0x09 - Lock function parameter */ + u8 prm5; /* 0x0a - Lock function parameter */ + u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ + u8 lids; /* 0x0f - LID state (open = 1) */ + u8 pwrs; /* 0x10 - Power state (AC = 1) */ + u8 dbgs; /* 0x11 - Debug state */ + u8 linx; /* 0x12 - Linux OS */ + u8 dckn; /* 0x13 - PCIe docking state */ + /* Thermal policy */ + u8 actt; /* 0x14 - active trip point */ + u8 psvt; /* 0x15 - passive trip point */ + u8 tc1v; /* 0x16 - passive trip point TC1 */ + u8 tc2v; /* 0x17 - passive trip point TC2 */ + u8 tspv; /* 0x18 - passive trip point TSP */ + u8 crtt; /* 0x19 - critical trip point */ + u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ + u8 dts1; /* 0x1b - DT sensor 1 */ + u8 dts2; /* 0x1c - DT sensor 2 */ + u8 rsvd2; + /* Battery Support */ + u8 bnum; /* 0x1e - number of batteries */ + u8 b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */ + u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ + u8 rsvd3[3]; + /* Processor Identification */ + u8 apic; /* 0x28 - APIC enabled */ + u8 mpen; /* 0x29 - MP capable/enabled */ + u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ + u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ + u8 ppcm; /* 0x2c - Max. PPC state */ + u8 rsvd4[5]; + /* Super I/O & CMOS config */ + u8 natp; /* 0x32 - SIO type */ + u8 cmap; /* 0x33 - */ + u8 cmbp; /* 0x34 - */ + u8 lptp; /* 0x35 - LPT port */ + u8 fdcp; /* 0x36 - Floppy Disk Controller */ + u8 rfdv; /* 0x37 - */ + u8 hotk; /* 0x38 - Hot Key */ + u8 rtcf; + u8 util; + u8 acin; + /* Integrated Graphics Device */ + u8 igds; /* 0x3c - IGD state */ + u8 tlst; /* 0x3d - Display Toggle List Pointer */ + u8 cadl; /* 0x3e - currently attached devices */ + u8 padl; /* 0x3f - previously attached devices */ + u16 cste; /* 0x40 - current display state */ + u16 nste; /* 0x42 - next display state */ + u16 sste; /* 0x44 - set display state */ + u8 ndid; /* 0x46 - number of device ids */ + u32 did[5]; /* 0x47 - 5b device id 1..5 */ + u8 rsvd5[0x9]; + /* Backlight Control */ + u8 blcs; /* 0x64 - Backlight Control possible */ + u8 brtl; + u8 odds; + u8 rsvd6[0x7]; + /* Ambient Light Sensors*/ + u8 alse; /* 0x6e - ALS enable */ + u8 alaf; + u8 llow; + u8 lhih; + u8 rsvd7[0x6]; + /* EMA */ + u8 emae; /* 0x78 - EMA enable */ + u16 emap; + u16 emal; + u8 rsvd8[0x5]; + /* MEF */ + u8 mefe; /* 0x82 - MEF enable */ + u8 rsvd9[0x9]; + /* TPM support */ + u8 tpmp; /* 0x8c - TPM */ + u8 tpme; + u8 rsvd10[8]; + /* SATA */ + u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */ + u8 gtf1[7]; + u8 gtf2[7]; + u8 idem; + u8 idet; + u8 rsvd11[7]; + /* IGD OpRegion (not implemented yet) */ + u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ + u8 ibtt; + u8 ipat; + u8 itvf; + u8 itvm; + u8 ipsc; + u8 iblc; + u8 ibia; + u8 issc; + u8 i409; + u8 i509; + u8 i609; + u8 i709; + u8 idmm; + u8 idms; + u8 if1e; + u8 hvco; + u32 nxd[8]; + u8 rsvd12[8]; + /* Mainboard specific */ + u8 dock; /* 0xf0 - Docking Status */ + u8 bten; + u8 rsvd13[14]; +} __attribute__((packed)) global_nvs_t; + diff --git a/src/southbridge/intel/i82801ix/pci.c b/src/southbridge/intel/i82801ix/pci.c new file mode 100644 index 0000000..3d993ee --- /dev/null +++ b/src/southbridge/intel/i82801ix/pci.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801ix.h" + +static void pci_init(struct device *dev) +{ + u16 reg16; + u8 reg8; + + /* This device has no interrupt */ + pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); + + /* Master Latency Count must be set to 0x04! */ + reg8 = pci_read_config8(dev, D30F0_SMLT); + reg8 &= 0x07; + reg8 |= (0x04 << 3); + pci_write_config8(dev, D30F0_SMLT, reg8); + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, PCI_STATUS); + //reg16 |= 0xf900; + pci_write_config16(dev, PCI_STATUS, reg16); + + reg16 = pci_read_config16(dev, PCI_SEC_STATUS); + // reg16 |= 0xf900; + pci_write_config16(dev, PCI_SEC_STATUS, reg16); +} + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + /* NOTE: 0x54 is not the default position! */ + if (!vendor || !device) { + pci_write_config32(dev, 0x54, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, 0x54, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + 0x244e, /* Desktop */ + 0x2448, /* Mobile */ + 0 +}; + +static const struct pci_driver ich9_pci __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c new file mode 100644 index 0000000..fcf6668 --- /dev/null +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> + +static void pci_init(struct device *dev) +{ + u16 reg16; + u32 reg32; + + printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); + + /* Enable Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Set Cache Line Size to 0x10 */ + // This has no effect but the OS might expect it + pci_write_config8(dev, 0x0c, 0x10); + + reg16 = pci_read_config16(dev, 0x3e); + reg16 &= ~(1 << 0); /* disable parity error response */ + reg16 |= (1 << 2); /* ISA enable */ + pci_write_config16(dev, 0x3e, reg16); + + /* Enable IO xAPIC on this PCIe port */ + reg32 = pci_read_config32(dev, 0xd8); + reg32 |= (1 << 7); + pci_write_config32(dev, 0xd8, reg32); + + /* Enable Backbone Clock Gating */ + reg32 = pci_read_config32(dev, 0xe1); + reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); + pci_write_config32(dev, 0xe1, reg32); + +#if CONFIG_MMCONF_SUPPORT + /* Set VC0 transaction class */ + reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 &= 0xffffff00; + reg32 |= 1; + pci_mmio_write_config32(dev, 0x114, reg32); + + /* Mask completion timeouts */ + reg32 = pci_mmio_read_config32(dev, 0x148); + reg32 |= (1 << 14); + pci_mmio_write_config32(dev, 0x148, reg32); + + /* Lock R/WO Correctable Error Mask. */ + pci_mmio_write_config32(dev, 0x154, pci_mmio_read_config32(dev, 0x154)); +#else +#error "MMIO needed for ICH9 PCIe" +#endif + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, 0x06); + pci_write_config16(dev, 0x06, reg16); + reg16 = pci_read_config16(dev, 0x1e); + pci_write_config16(dev, 0x1e, reg16); + + /* Get configured ASPM state */ + const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3; + + /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ + if (apmc == PCIE_ASPM_BOTH) { + reg32 = pci_read_config32(dev, 0xe8); + reg32 |= (1 << 1); + pci_write_config32(dev, 0xe8, reg32); + } +} + +static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + /* NOTE: 0x94 is not the default position! */ + if (!vendor || !device) { + pci_write_config32(dev, 0x94, + pci_read_config32(dev, 0)); + } else { + pci_write_config32(dev, 0x94, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = pcie_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pci_init, + .scan_bus = pciexp_scan_bridge, + .ops_pci = &pci_ops, +}; + +/* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */ +static const unsigned short pci_device_ids[] = { + 0x2940, /* Port 1 */ + 0x2942, /* Port 2 */ + 0x2944, /* Port 3 */ + 0x2946, /* Port 4 */ + 0x2948, /* Port 5 */ + 0x294a, /* Port 6 */ + 0 +}; +static const struct pci_driver ich9_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; + diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c new file mode 100644 index 0000000..595b80c --- /dev/null +++ b/src/southbridge/intel/i82801ix/sata.c @@ -0,0 +1,285 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801ix.h" + +typedef struct southbridge_intel_i82801ix_config config_t; + +static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, + const int is_mobile) +{ + int i; + u32 reg32; + + /* Initialize AHCI memory-mapped space */ + const u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %08X\n", abar); + + /* Set AHCI access mode. + No other ABAR registers should be accessed before this. */ + reg32 = read32(abar + 0x04); + reg32 |= 1 << 31; + write32(abar + 0x04, reg32); + + /* CAP (HBA Capabilities) : enable power management */ + reg32 = read32(abar + 0x00); + /* CCCS must be set. */ + reg32 |= 0x0c006080; /* set CCCS+PSC+SSC+SALP+SSS */ + reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ + write32(abar + 0x00, reg32); + + /* PI (Ports implemented) */ + write32(abar + 0x0c, port_map); + /* PCH code reads back twice, do we need it, too? */ + (void) read32(abar + 0x0c); /* Read back 1 */ + (void) read32(abar + 0x0c); /* Read back 2 */ + + /* VSP (Vendor Specific Register) */ + reg32 = read32(abar + 0xa0); + reg32 &= ~0x00000001; /* clear SLPD */ + write32(abar + 0xa0, reg32); + + /* Lock R/WO bits in Port command registers. */ + for (i = 0; i < 6; ++i) { + if (((i == 2) || (i == 3)) && is_mobile) + continue; + const u32 addr = abar + 0x118 + (i * 0x80); + write32(addr, read32(addr)); + } +} + +static void sata_program_indexed(struct device *const dev, const int is_mobile) +{ + u32 reg32; + + pci_write_config8(dev, D31F2_SIDX, 0x18); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 6) | (7 << 3) | (7 << 0)); + reg32 |= (3 << 3) | (3 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); + + pci_write_config8(dev, D31F2_SIDX, 0x28); + pci_write_config32(dev, D31F2_SDAT, 0x00cc2080); + + pci_write_config8(dev, D31F2_SIDX, 0x40); + pci_write_config8(dev, D31F2_SDAT + 2, 0x22); + + pci_write_config8(dev, D31F2_SIDX, 0x78); + pci_write_config8(dev, D31F2_SDAT + 2, 0x22); + + if (!is_mobile) { + pci_write_config8(dev, D31F2_SIDX, 0x84); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 3) | (7 << 0)); + reg32 |= (3 << 3) | (3 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); + } + + pci_write_config8(dev, D31F2_SIDX, 0x88); + reg32 = pci_read_config32(dev, D31F2_SDAT); + if (!is_mobile) + reg32 &= ~((7 << 27) | (7 << 24) | (7 << 11) | (7 << 8)); + reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0)); + if (!is_mobile) + reg32 |= (4 << 27) | (4 << 24) | (2 << 11) | (2 << 8); + reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); + + pci_write_config8(dev, D31F2_SIDX, 0x8c); + reg32 = pci_read_config32(dev, D31F2_SDAT); + if (!is_mobile) + reg32 &= ~((7 << 27) | (7 << 24)); + reg32 &= ~((7 << 19) | (7 << 16) | 0xffff); + if (!is_mobile) + reg32 |= (2 << 27) | (2 << 24); + reg32 |= (2 << 19) | (2 << 16) | 0x00aa; + pci_write_config32(dev, D31F2_SDAT, reg32); + + pci_write_config8(dev, D31F2_SIDX, 0x94); + pci_write_config32(dev, D31F2_SDAT, 0x00000022); + + pci_write_config8(dev, D31F2_SIDX, 0xa0); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 3) | (7 << 0)); + reg32 |= (3 << 3) | (3 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); + + pci_write_config8(dev, D31F2_SIDX, 0xa8); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0)); + reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); + + pci_write_config8(dev, D31F2_SIDX, 0xac); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 19) | (7 << 16) | 0xffff); + reg32 |= (2 << 19) | (2 << 16) | 0x000a; + pci_write_config32(dev, D31F2_SDAT, reg32); +} + +static void sata_init(struct device *const dev) +{ + u16 reg16; + + /* Get the chip configuration */ + const config_t *const config = dev->chip_info; + + const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID); + const int is_mobile = (devid == 0x2928) || (devid == 0x2929); + + printk(BIOS_DEBUG, "i82801ix_sata: initializing...\n"); + + if (config == NULL) { + printk(BIOS_ERR, "i82801ix_sata: error: " + "device not in devicetree.cb!\n"); + return; + } + + /* + * TODO: In contrast to ICH7 and PCH code we don't set + * timings, dma and IDE-I/O settings here. Looks like they + * became obsolete with the fading of real IDE ports. + * Maybe we can safely remove those settings from PCH code and + * even ICH7 code if it doesn't use the feature to combine the + * IDE and SATA controllers. + */ + + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | /* read-only in IDE modes */ + PCI_COMMAND_IO); + if (!config->sata_ahci) + /* No AHCI: clear AHCI base */ + pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); + + if (config->ide_legacy_combined) { + printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); + } else if (config->sata_ahci) { + printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); + } else { + printk(BIOS_DEBUG, "SATA controller in native mode.\n"); + + /* Enable native mode on both primary and secondary. */ + pci_write_config8(dev, PCI_CLASS_PROG, 0x8f); + } + + /* Looks like we should only enable decoding here. */ + pci_write_config16(dev, D31F2_IDE_TIM_PRI, (1 << 15)); + pci_write_config16(dev, D31F2_IDE_TIM_SEC, (1 << 15)); + + /* Port enable. For AHCI, it's managed in memory mapped space. */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x3f; + reg16 |= (1 << 15) | (config->sata_ahci ? 0x3f : config->sata_port_map); + pci_write_config16(dev, 0x92, reg16); + + /* SATA clock settings */ + u32 sclkcg = 0; + if (config->sata_clock_request && + !(inb(DEFAULT_GPIOBASE + 0x30) & (1 << (35 - 32)))) + sclkcg |= 1 << 30; /* Enable SATA clock request. */ + /* Disable unused ports. */ + sclkcg |= ((~config->sata_port_map) & 0x3f) << 24; + /* Must be programmed. */ + sclkcg |= 0x193; + pci_write_config32(dev, 0x94, sclkcg); + + if (is_mobile && config->sata_traffic_monitor) { + const device_t lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) + >> 3) & 3) == 3) { + u8 reg8 = pci_read_config8(dev, 0x9c); + reg8 &= ~(0x1f << 2); + reg8 |= 3 << 2; + pci_write_config8(dev, 0x9c, reg8); + } + } + + if (config->sata_ahci) + sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + + sata_program_indexed(dev, is_mobile); +} + +static void sata_enable(device_t dev) +{ + /* Get the chip configuration */ + const config_t *const config = dev->chip_info; + + u16 map = 0; + + if (!config) + return; + + /* + * Set SATA controller mode early so the resource allocator can + * properly assign IO/Memory resources for the controller. + */ + if (config->sata_ahci) + map = 0x0040 | 0x0020; /* SATA mode + all ports on D31:F2 */ + + map |= (config->sata_port_map ^ 0x3f) << 8; + + pci_write_config16(dev, 0x90, map); +} + +static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations sata_pci_ops = { + .set_subsystem = sata_set_subsystem, +}; + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .enable = sata_enable, + .scan_bus = 0, + .ops_pci = &sata_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + 0x2920, 0x2921, 0x2922, 0x2923, + 0x2928, 0x2929, + 0, +}; + +static const struct pci_driver pch_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; + diff --git a/src/southbridge/intel/i82801ix/smbus.h b/src/southbridge/intel/i82801ix/smbus.h new file mode 100644 index 0000000..eff60ef --- /dev/null +++ b/src/southbridge/intel/i82801ix/smbus.h @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/smbus_def.h> +#include "i82801ix.h" + +static void smbus_delay(void) +{ + inb(0x80); +} + +static int smbus_wait_until_ready(u16 smbus_base) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_base + SMBHSTSTAT); + } while (byte & 1); + return loops ? 0 : -1; +} + +static int smbus_wait_until_done(u16 smbus_base) +{ + unsigned loops = SMBUS_TIMEOUT; + unsigned char byte; + do { + smbus_delay(); + if (--loops == 0) + break; + byte = inb(smbus_base + SMBHSTSTAT); + } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); + return loops ? 0 : -1; +} + +static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address) +{ + unsigned char global_status_register; + unsigned char byte; + + if (smbus_wait_until_ready(smbus_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(0, smbus_base + SMBHSTDAT0); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(smbus_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inb(smbus_base + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + byte = inb(smbus_base + SMBHSTDAT0); + if (global_status_register != (1 << 1)) { + return SMBUS_ERROR; + } + return byte; +} + diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c new file mode 100644 index 0000000..b0afd1f --- /dev/null +++ b/src/southbridge/intel/i82801ix/smi.c @@ -0,0 +1,392 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/io.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <string.h> +#include "i82801ix.h" + +extern unsigned char _binary_smm_start; +extern unsigned char _binary_smm_size; + +/* I945/GM45 */ +#define SMRAM 0x9d +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +/* While we read PMBASE dynamically in case it changed, let's + * initialize it with a sane value + */ +static u16 pmbase = DEFAULT_PMBASE; + +/** + * @brief read and clear PM1_STS + * @return PM1_STS register + */ +static u16 reset_pm1_status(void) +{ + u16 reg16; + + reg16 = inw(pmbase + PM1_STS); + /* set status bits are cleared by writing 1 to them */ + outw(reg16, pmbase + PM1_STS); + + return reg16; +} + +static void dump_pm1_status(u16 pm1_sts) +{ + printk(BIOS_DEBUG, "PM1_STS: "); + if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); + if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); + if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); + if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); + if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); + if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); + if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); + printk(BIOS_DEBUG, "\n"); +} + +/** + * @brief read and clear SMI_STS + * @return SMI_STS register + */ +static u32 reset_smi_status(void) +{ + u32 reg32; + + reg32 = inl(pmbase + SMI_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg32, pmbase + SMI_STS); + + return reg32; +} + +static void dump_smi_status(u32 smi_sts) +{ + printk(BIOS_DEBUG, "SMI_STS: "); + if (smi_sts & (1 << 27)) printk(BIOS_DEBUG, "GPIO_UNLOCK "); + if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); + if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); + if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); + if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); + if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); + if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); + if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); + if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); + if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); + if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); + if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); + if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); + printk(BIOS_DEBUG, "\n"); +} + + +/** + * @brief read and clear GPE0_STS + * @return GPE0_STS register + */ +static u64 reset_gpe0_status(void) +{ + u32 reg_h, reg_l; + + reg_l = inl(pmbase + GPE0_STS); + reg_h = inl(pmbase + GPE0_STS + 4); + /* set status bits are cleared by writing 1 to them */ + outl(reg_l, pmbase + GPE0_STS); + outl(reg_h, pmbase + GPE0_STS + 4); + + return (((u64)reg_h) << 32) | reg_l; +} + +static void dump_gpe0_status(u64 gpe0_sts) +{ + int i; + printk(BIOS_DEBUG, "GPE0_STS: "); + if (gpe0_sts & (1LL << 32)) printk(BIOS_DEBUG, "USB6 "); + for (i=31; i<= 16; i--) { + if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); + } + if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); + if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); + if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); + if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); + if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); + if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 "); + if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); + if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); + if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); + if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); + printk(BIOS_DEBUG, "\n"); +} + + +/** + * @brief read and clear ALT_GP_SMI_STS + * @return ALT_GP_SMI_STS register + */ +static u16 reset_alt_gp_smi_status(void) +{ + u16 reg16; + + reg16 = inl(pmbase + ALT_GP_SMI_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg16, pmbase + ALT_GP_SMI_STS); + + return reg16; +} + +static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) +{ + int i; + printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); + for (i=15; i<= 0; i--) { + if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16)); + } + printk(BIOS_DEBUG, "\n"); +} + + + +/** + * @brief read and clear TCOx_STS + * @return TCOx_STS registers + */ +static u32 reset_tco_status(void) +{ + u32 tcobase = pmbase + 0x60; + u32 reg32; + + reg32 = inl(tcobase + 0x04); + /* set status bits are cleared by writing 1 to them */ + outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS + if (reg32 & (1 << 18)) + outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS + + return reg32; +} + + +static void dump_tco_status(u32 tco_sts) +{ + printk(BIOS_DEBUG, "TCO_STS: "); + if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); + if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); + if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); + if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); + if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); + if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); + if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); + if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); + if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); + if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); + if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); + if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); + printk(BIOS_DEBUG, "\n"); +} + + +/** + * @brief Set the EOS bit + */ +static void smi_set_eos(void) +{ + u8 reg8; + + reg8 = inb(pmbase + SMI_EN); + reg8 |= EOS; + outb(reg8, pmbase + SMI_EN); +} + +extern uint8_t smm_relocation_start, smm_relocation_end; + +static void smm_relocate(void) +{ + u32 smi_en; + u16 pm1_en; + + printk(BIOS_DEBUG, "Initializing SMM handler..."); + + pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc; + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); + + smi_en = inl(pmbase + SMI_EN); + if (smi_en & GBL_SMI_EN) { + printk(BIOS_INFO, "SMI# handler already enabled?\n"); + return; + } + + /* copy the SMM relocation code */ + memcpy((void *)0x38000, &smm_relocation_start, + &smm_relocation_end - &smm_relocation_start); + + printk(BIOS_DEBUG, "\n"); + dump_smi_status(reset_smi_status()); + dump_pm1_status(reset_pm1_status()); + dump_gpe0_status(reset_gpe0_status()); + dump_alt_gp_smi_status(reset_alt_gp_smi_status()); + dump_tco_status(reset_tco_status()); + + /* Enable SMI generation: + * - on TCO events + * - on APMC writes (io 0xb2) + * - on writes to GBL_RLS (bios commands) + * No SMIs: + * - on microcontroller writes (io 0x62/0x66) + */ + + smi_en = 0; /* reset SMI enables */ + + smi_en |= TCO_EN; + smi_en |= APMC_EN; +#if DEBUG_PERIODIC_SMIS + /* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using + * periodic SMIs. + */ + smi_en |= PERIODIC_EN; +#endif + smi_en |= BIOS_EN; + + /* The following need to be on for SMIs to happen */ + smi_en |= EOS | GBL_SMI_EN; + + outl(smi_en, pmbase + SMI_EN); + + pm1_en = 0; + pm1_en |= PWRBTN_EN; + pm1_en |= GBL_EN; + outw(pm1_en, pmbase + PM1_EN); + + /** + * There are several methods of raising a controlled SMI# via + * software, among them: + * - Writes to io 0xb2 (APMC) + * - Writes to the Local Apic ICR with Delivery mode SMI. + * + * Using the local apic is a bit more tricky. According to + * AMD Family 11 Processor BKDG no destination shorthand must be + * used. + * The whole SMM initialization is quite a bit hardware specific, so + * I'm not too worried about the better of the methods at the moment + */ + + /* raise an SMI interrupt */ + printk(BIOS_SPEW, " ... raise SMI#\n"); + outb(0x00, 0xb2); +} + +static int smm_handler_copied = 0; + +static int is_wakeup(void) +{ + device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); + + if (!dev0) + return 0; + + return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; +} + +static void smm_install(void) +{ + /* The first CPU running this gets to copy the SMM handler. But not all + * of them. + */ + if (smm_handler_copied) + return; + smm_handler_copied = 1; + + + /* if we're resuming from S3, the SMM code is already in place, + * so don't copy it again to keep the current SMM state */ + + if (!is_wakeup()) { + /* enable the SMM memory window */ + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + D_OPEN | G_SMRAME | C_BASE_SEG); + + /* copy the real SMM handler */ + memcpy((void *)0xa0000, &_binary_smm_start, (size_t)&_binary_smm_size); + wbinvd(); + } + + /* close the SMM memory window and enable normal SMM */ + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + G_SMRAME | C_BASE_SEG); +} + +void smm_init(void) +{ + /* Put SMM code to 0xa0000 */ + smm_install(); + + /* Put relocation code to 0x38000 and relocate SMBASE */ + smm_relocate(); + + /* We're done. Make sure SMIs can happen! */ + smi_set_eos(); +} + +void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, + D_LCK | G_SMRAME | C_BASE_SEG); +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1) +{ + /* The GDT or coreboot table is going to live here. But a long time + * after we relocated the GNVS, so this is not troublesome. + */ + *(u32 *)0x500 = (u32)gnvs; + *(u32 *)0x504 = (u32)tcg; + *(u32 *)0x508 = (u32)smi1; + outb(APM_CNT_GNVS_UPDATE, 0xb2); +} diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c new file mode 100644 index 0000000..4e8edfe --- /dev/null +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -0,0 +1,532 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <console/console.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <device/pci_def.h> +#include <pc80/mc146818rtc.h> +#include "i82801ix.h" + +#include "nvs.h" + +/* While we read PMBASE dynamically in case it changed, let's + * initialize it with a sane value + */ +u16 pmbase = DEFAULT_PMBASE; +u8 smm_initialized = 0; + +/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located + * by coreboot. + */ +global_nvs_t *gnvs = (global_nvs_t *)0x0; +void *tcg = (void *)0x0; +void *smi1 = (void *)0x0; + +/** + * @brief read and clear PM1_STS + * @return PM1_STS register + */ +static u16 reset_pm1_status(void) +{ + u16 reg16; + + reg16 = inw(pmbase + PM1_STS); + /* set status bits are cleared by writing 1 to them */ + outw(reg16, pmbase + PM1_STS); + + return reg16; +} + +static void dump_pm1_status(u16 pm1_sts) +{ + printk(BIOS_DEBUG, "PM1_STS: "); + if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); + if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); + if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); + if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); + if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); + if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); + if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); + printk(BIOS_DEBUG, "\n"); +} + +/** + * @brief read and clear SMI_STS + * @return SMI_STS register + */ +static u32 reset_smi_status(void) +{ + u32 reg32; + + reg32 = inl(pmbase + SMI_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg32, pmbase + SMI_STS); + + return reg32; +} + +static void dump_smi_status(u32 smi_sts) +{ + printk(BIOS_DEBUG, "SMI_STS: "); + if (smi_sts & (1 << 27)) printk(BIOS_DEBUG, "GPIO_UNLOCK "); + if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); + if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); + if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); + if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); + if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); + if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); + if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); + if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); + if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); + if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); + if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); + if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); + printk(BIOS_DEBUG, "\n"); +} + + +/** + * @brief read and clear GPE0_STS + * @return GPE0_STS register + */ +static u64 reset_gpe0_status(void) +{ + u32 reg_h, reg_l; + + reg_l = inl(pmbase + GPE0_STS); + reg_h = inl(pmbase + GPE0_STS + 4); + /* set status bits are cleared by writing 1 to them */ + outl(reg_l, pmbase + GPE0_STS); + outl(reg_h, pmbase + GPE0_STS + 4); + + return (((u64)reg_h) << 32) | reg_l; +} + +static void dump_gpe0_status(u64 gpe0_sts) +{ + int i; + printk(BIOS_DEBUG, "GPE0_STS: "); + if (gpe0_sts & (1LL << 32)) printk(BIOS_DEBUG, "USB6 "); + for (i=31; i<= 16; i--) { + if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); + } + if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); + if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); + if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); + if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); + if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); + if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 "); + if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); + if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); + if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE "); + if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); + printk(BIOS_DEBUG, "\n"); +} + + + +/** + * @brief read and clear TCOx_STS + * @return TCOx_STS registers + */ +static u32 reset_tco_status(void) +{ + u32 tcobase = pmbase + 0x60; + u32 reg32; + + reg32 = inl(tcobase + 0x04); + /* set status bits are cleared by writing 1 to them */ + outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS + if (reg32 & (1 << 18)) + outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS + + return reg32; +} + + +static void dump_tco_status(u32 tco_sts) +{ + printk(BIOS_DEBUG, "TCO_STS: "); + if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); + if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); + if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); + if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); + if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); + if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); + if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); + if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); + if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); + if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); + if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); + if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); + printk(BIOS_DEBUG, "\n"); +} + +int southbridge_io_trap_handler(int smif) +{ + switch (smif) { + case 0x32: + printk(BIOS_DEBUG, "OS Init\n"); + /* gnvs->smif: + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + */ + gnvs->smif = 0; + return 1; /* IO trap handled */ + } + + /* Not handled */ + return 0; +} + +/** + * @brief Set the EOS bit + */ +void southbridge_smi_set_eos(void) +{ + u8 reg8; + + reg8 = inb(pmbase + SMI_EN); + reg8 |= EOS; + outb(reg8, pmbase + SMI_EN); +} + +static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save) +{ + u32 pmctrl; + u8 reg8; + + /* Emulate B2 register as the FADT / Linux expects it */ + + reg8 = inb(APM_CNT); + if (mainboard_smi_apmc && mainboard_smi_apmc(reg8)) + return; + + switch (reg8) { + case APM_CNT_CST_CONTROL: + /* Calling this function seems to cause + * some kind of race condition in Linux + * and causes a kernel oops + */ + printk(BIOS_DEBUG, "C-state control\n"); + break; + case APM_CNT_PST_CONTROL: + /* Calling this function seems to cause + * some kind of race condition in Linux + * and causes a kernel oops + */ + printk(BIOS_DEBUG, "P-state control\n"); + break; + case APM_CNT_ACPI_DISABLE: + pmctrl = inl(pmbase + PM1_CNT); + pmctrl &= ~SCI_EN; + outl(pmctrl, pmbase + PM1_CNT); + printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); + break; + case APM_CNT_ACPI_ENABLE: + pmctrl = inl(pmbase + PM1_CNT); + pmctrl |= SCI_EN; + outl(pmctrl, pmbase + PM1_CNT); + printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); + break; + case APM_CNT_GNVS_UPDATE: + if (smm_initialized) { + printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); + return; + } + gnvs = *(global_nvs_t **)0x500; + tcg = *(void **)0x504; + smi1 = *(void **)0x508; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); + break; + default: + printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8); + } +} + +static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save) +{ + u16 pm1_sts; + volatile u8 cmos_status; + + pm1_sts = reset_pm1_status(); + dump_pm1_status(pm1_sts); + + /* While OSPM is not active, poweroff immediately + * on a power button event. + */ + if (pm1_sts & PWRBTN_STS) { + // power button pressed + u32 reg32; + reg32 = (7 << 10) | (1 << 13); + outl(reg32, pmbase + PM1_CNT); + } + + if (pm1_sts & RTC_STS) { + /* read RTC status register to disable the interrupt */ + cmos_status = cmos_read(RTC_REG_C); + printk(BIOS_DEBUG, "RTC IRQ status: %02X\n", cmos_status); + } +} + +static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) +{ + u32 gpe0_sts; + + gpe0_sts = reset_gpe0_status(); + dump_gpe0_status(gpe0_sts); +} + +static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) +{ + u16 reg16; + reg16 = inw(pmbase + ALT_GP_SMI_STS); + outl(reg16, pmbase + ALT_GP_SMI_STS); + + reg16 &= inw(pmbase + ALT_GP_SMI_EN); + + if (mainboard_smi_gpi) { + mainboard_smi_gpi(reg16); + } else { + if (reg16) + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); + } +} + + +static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) +{ + u32 tco_sts; + + tco_sts = reset_tco_status(); + + /* Any TCO event? */ + if (!tco_sts) + return; + + if (tco_sts & (1 << 8)) { // BIOSWR + u8 bios_cntl; + + bios_cntl = pci_mmio_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + + if (bios_cntl & 1) { + /* BWE is RW, so the SMI was caused by a + * write to BWE, not by a write to the BIOS + */ + + /* This is the place where we notice someone + * is trying to tinker with the BIOS. We are + * trying to be nice and just ignore it. A more + * resolute answer would be to power down the + * box. + */ + printk(BIOS_DEBUG, "Switching back to RO\n"); + pci_mmio_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + } /* No else for now? */ + } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ + /* Handle TCO timeout */ + printk(BIOS_DEBUG, "TCO Timeout.\n"); + } else { + dump_tco_status(tco_sts); + } +} + +#if DEBUG_PERIODIC_SMIS +static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save) +{ + printk(BIOS_DEBUG, "Periodic SMI.\n"); +} +#endif + +static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) +{ +#define IOTRAP(x) (trap_sts & (1 << x)) + u32 trap_sts, trap_cycle; + u32 data, mask = 0; + int i; + + trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register + RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR + + trap_cycle = RCBA32(0x1e10); + for (i=16; i<20; i++) { + if (trap_cycle & (1 << i)) + mask |= (0xff << ((i - 16) << 3)); + } + + + /* IOTRAP(3) SMI function call */ + if (IOTRAP(3)) { + if (gnvs && gnvs->smif) + io_trap_handler(gnvs->smif); // call function smif + return; + } + + /* IOTRAP(2) currently unused + * IOTRAP(1) currently unused */ + + /* IOTRAP(0) SMIC */ + if (IOTRAP(0)) { + if (!(trap_cycle & (1 << 24))) { // It's a write + printk(BIOS_DEBUG, "SMI1 command\n"); + data = RCBA32(0x1e18); + data &= mask; + // if (smi1) + // southbridge_smi_command(data); + // return; + } + // Fall through to debug + } + + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); + printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); + printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); + + if (!(trap_cycle & (1 << 24))) { + /* Write Cycle */ + data = RCBA32(0x1e18); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); + } +#undef IOTRAP +} + +typedef void (*smi_handler_t)(unsigned int node, + smm_state_save_area_t *state_save); + +smi_handler_t southbridge_smi[32] = { + NULL, // [0] reserved + NULL, // [1] reserved + NULL, // [2] BIOS_STS + NULL, // [3] LEGACY_USB_STS + NULL, // [4] SLP_SMI_STS + southbridge_smi_apmc, // [5] APM_STS + NULL, // [6] SWSMI_TMR_STS + NULL, // [7] reserved + southbridge_smi_pm1, // [8] PM1_STS + southbridge_smi_gpe0, // [9] GPE0_STS + southbridge_smi_gpi, // [10] GPI_STS + NULL, // [11] MCSMI_STS + NULL, // [12] DEVMON_STS + southbridge_smi_tco, // [13] TCO_STS +#if DEBUG_PERIODIC_SMIS + southbridge_smi_periodic, // [14] PERIODIC_STS +#else + NULL, // [14] PERIODIC_STS +#endif + NULL, // [15] SERIRQ_SMI_STS + NULL, // [16] SMBUS_SMI_STS + NULL, // [17] LEGACY_USB2_STS + NULL, // [18] INTEL_USB2_STS + NULL, // [19] reserved + NULL, // [20] PCI_EXP_SMI_STS + southbridge_smi_monitor, // [21] MONITOR_STS + NULL, // [22] reserved + NULL, // [23] reserved + NULL, // [24] reserved + NULL, // [25] reserved + NULL, // [26] SPI_STS + NULL, // [27] reserved + NULL, // [28] reserved + NULL, // [29] reserved + NULL, // [30] reserved + NULL // [31] reserved +}; + +static u32 southbrigde_smi_mask_events(u32 smi_sts) +{ + /* Clear all disabled bits in SMI_EN but the reserved ones. */ + smi_sts &= inl(pmbase + SMI_EN) | 0xf7f99700; + + /* Check if SCI is enabled. */ + if (inl(pmbase + PM1_CNT) & SCI_EN) + /* Clear PM1, GPE. */ + smi_sts &= ~((1 << 8) | (1 << 9)); + + /* Check if SPI generates SMI. */ + if (!(RCBA16(0x3806) & (1 << 15)) && + !(RCBA16(0x3891) & (1 << 15))) + /* Clear SPI. */ + smi_sts &= ~(1 << 26); + + return smi_sts; +} + +/** + * @brief Interrupt handler for SMI# + * + * @param smm_revision revision of the smm state save map + */ +void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +{ + int i, dump = 0; + u32 smi_sts; + + /* Update global variable pmbase */ + pmbase = pci_mmio_read_config16(PCI_DEV(0, 0x1f, 0), D31F0_PMBASE) & 0xfffc; + + /* We need to clear the SMI status registers, or we won't see what's + * happening in the following calls. + */ + smi_sts = reset_smi_status(); + + /* Filter all non-enabled SMI events */ + smi_sts = southbrigde_smi_mask_events(smi_sts); + + /* Call SMI sub handler for each of the status bits */ + for (i = 0; i < 31; i++) { + if (smi_sts & (1 << i)) { + if (southbridge_smi[i]) + southbridge_smi[i](node, state_save); + else { + printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " + "handler available.\n", i); + dump = 1; + } + } + } + + if(dump) { + dump_smi_status(smi_sts); + } + +} diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c new file mode 100644 index 0000000..33fafd3 --- /dev/null +++ b/src/southbridge/intel/i82801ix/thermal.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * (Written by Nico Huber <nico.huber(a)secunet.com> for secunet) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include "i82801ix.h" + +static void thermal_init(struct device *dev) +{ + if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) + return; + + u8 reg8; + u32 reg32; + + pci_write_config32(dev, 0x10, DEFAULT_TBAR); + reg32 = pci_read_config32(dev, 0x04); + pci_write_config32(dev, 0x04, reg32 | (1 << 1)); + + write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */ + write32(DEFAULT_TBAR + 0x44, 0); + + write8(DEFAULT_TBAR + 0x01, 0xba); /* Enable sensor 0 + 1. */ + write8(DEFAULT_TBAR + 0x41, 0xba); + + reg8 = read8(DEFAULT_TBAR + 0x08); /* Lock thermal registers. */ + write8(DEFAULT_TBAR + 0x08, reg8 | (1 << 7)); + reg8 = read8(DEFAULT_TBAR + 0x48); + write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7)); + + reg32 = pci_read_config32(dev, 0x04); + pci_write_config32(dev, 0x04, reg32 & ~(1 << 1)); + pci_write_config32(dev, 0x10, 0); +} + +static void thermal_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations thermal_pci_ops = { + .set_subsystem = thermal_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = thermal_init, + .scan_bus = 0, + .ops_pci = &thermal_pci_ops, +}; + +static const struct pci_driver ich9_thermal __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2932, +}; diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c new file mode 100644 index 0000000..a7fbd69 --- /dev/null +++ b/src/southbridge/intel/i82801ix/usb_ehci.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82801ix.h" +#include <usbdebug.h> + +static void usb_ehci_init(struct device *dev) +{ + u32 reg32; + + printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + printk(BIOS_DEBUG, "done.\n"); +} + +static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + u8 access_cntl; + + access_cntl = pci_read_config8(dev, 0x80); + + /* Enable writes to protected registers. */ + pci_write_config8(dev, 0x80, access_cntl | 1); + + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } + + /* Restore protection. */ + pci_write_config8(dev, 0x80, access_cntl); +} + +static void usb_ehci_set_resources(struct device *dev) +{ +#if CONFIG_USBDEBUG + struct resource *res; + u32 base; + u32 usb_debug; + + usb_debug = get_ehci_debug(); + set_ehci_debug(0); +#endif + pci_dev_set_resources(dev); + +#if CONFIG_USBDEBUG + res = find_resource(dev, 0x10); + set_ehci_debug(usb_debug); + if (!res) return; + base = res->base; + set_ehci_base(base); + report_resource_stored(dev, res, ""); +#endif +} + + +static const unsigned short pci_device_ids[] = { + 0x293a, + 0x293c, + 0 +}; + +static struct pci_operations lops_pci = { + .set_subsystem = &usb_ehci_set_subsystem, +}; + +static struct device_operations usb_ehci_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = usb_ehci_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_ehci_init, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pch_usb_ehci1 __pci_driver = { + .ops = &usb_ehci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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coreboot November 2012