June 2011 - coreboot - mail.coreboot.org

Re: [coreboot] About grub.cfg——Building coreboot with grub2 payload
by Cui Lei June 1, 2011

June 1, 2011

Thank you for your help, I have changed my operation, but my coreboot still step to grub. /************************************* LOG *********************************************************/ Check fallback/payload Got a payload Loading segment from rom address 0xfff29ff8 data (compression=1) New segment dstaddr 0x8200 memsize 0xd8b8 srcaddr 0xfff2a04c filesize 0x3a69 (cleaned up) New segment addr 0x8200 size 0xd8b8 offset 0xfff2a04c filesize 0x3a69 Loading segment from rom address 0xfff2a014 data (compression=1) New segment dstaddr 0x15ab8 memsize 0x69914 srcaddr 0xfff2dab5 filesize 0x1d0c0 (cleaned up) New segment addr 0x15ab8 size 0x69914 offset 0xfff2dab5 filesize 0x1d0c0 Loading segment from rom address 0xfff2a030 Entry Point 0x00008200 Loading Segment: addr: 0x0000000000008200 memsz: 0x000000000000d8b8 filesz: 0x0000000000003a69 lb: [0x0000000000100000, 0x0000000000164000) Post relocation: addr: 0x0000000000008200 memsz: 0x000000000000d8b8 filesz: 0x0000000000003a69 using LZMA [ 0x00008200, 0000e51b, 0x00015ab8) <- fff2a04c Clearing Segment: addr: 0x000000000000e51b memsz: 0x000000000000759d dest 00008200, end 00015ab8, bouncebuffer 7fe28000 Loading Segment: addr: 0x0000000000015ab8 memsz: 0x0000000000069914 filesz: 0x000000000001d0c0 lb: [0x0000000000100000, 0x0000000000164000) Post relocation: addr: 0x0000000000015ab8 memsz: 0x0000000000069914 filesz: 0x000000000001d0c0 using LZMA [ 0x00015ab8, 0007f3cc, 0x0007f3cc) <- fff2dab5 dest 00015ab8, end 0007f3cc, bouncebuffer 7fe28000 Loaded segments Jumping to boot code at 8200 entry = 0x00008200 lb_start = 0x00100000 lb_size = 0x00064000 adjust = 0x7fd8c000 buffer = 0x7fe28000 elf_boot_notes = 0x0011622c adjusted_boot_notes = 0x7fea222c /****************************************************************************************************/ I have added "grub_printf("Enter grub_main()!\n")" in the top of grub_main()(defined in grub-core/kern/main.c). Unfortunately, nothing can be printed out when booting. I don't know it is stopped before grub C code or I don't open some grub2 option which close the standard output mode. > 2011/5/31 Cui Lei<neverforget_2002(a)163.com>: >> I am working hard at building coreboot with grub2 payload. Now I can build >> a grub2 payload as follow: >> 1: Download the lastest grub2 source code. >> 2: ./autogen.sh >> ./configure --with-platform=coreboot >> make >> 3: Use grub-mkimage to generate a "payload.elf", detail: >> ./grub-mkimage -d . -O i386-coreboot -o ../coreboot-v4/payload.elf >> --prefix='/boot/grub2' >> memdisk cpio -m ../memdisk.tar >> >> Accoding the coreboot website(http://www.coreboot.org/Talk:GRUB2), >> memdisk is a virtual disk >> in grub image and it is suggested that grub.cfg is contained in a >> memdisk image. So I made >> folders boot/grub2 in my work folder and add a new grub.cfg and some >> modules(such as >> memdisk.mod cpio.mod ...) into the boot/grub2, then tar boot/grub2 to >> memdisk.tar(according >> to the website tar can be used to build a memdisk image). >> >> Problems: >> 1: I don't know wether grub2 can found my grub.cfg ,if I set " >> --prefix='/boot/grub2' " ? >> On the coreboot website,a sample is --prefix='(ata0)/boot/grub2'. I >> think the ata0 is hard disk. >> but I use the memdisk image, what should I do ? >> > I use this to create a custom grub2 efi app with memdisk embedded - > > /bin/grub-mkimage --directory=/usr/lib/grub/x86_64-efi > --memdisk="${memdisk_64_img}" --prefix='(memdisk)/efi/grub2' > --format=x86_64-efi --compression=xz > --output="${grub2_efi_mp}/efi/boot/bootx64.efi" ${GRUB2_MODULES} > > Hope this helps. > >> 2: I want my grub.cfg in memdisk to load the grub.cfg from my hard disk. >> Because I have install the >> ubuntu11.04 on my hard disk, a grub.cfg file should be in the >> /boot/grub. So my grub.cfg just like >> this: >> search -f -s /boot/grub/grub.cfg >> configfile /boot/grub/grub.cfg >> >> Is this practicable? >> > Make it > > search --file --no-floppy --set=root /boot/grub/grub.cfg > configfile (${root})/boot/grub/grub.cfg > >> 3: I want the gurb can boot into the grub-shell, how to ? >> > I can't understand the question. You want grub to boot into > grub-shell? Don't create a ${prefix}/grub.cfg file. > >> BRs, >> >> Rock.C >> > Regards. > > Keshav >

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amd sb800 wrapper compile warning fix
by She, Kerry May 31, 2011

May 31, 2011

Hello, This patch fix a AMD sb800 wrapper compile warning: src/southbridge/amd/cimx_wrapper/sb800/late call clear_ioapic but not include the prototype declare header file. and remove some trivial blanks. Signed-off-by Kerry She <Kerry.she(a)amd.com> Regards, Kerry She < kerry.she(a)amd.com> Tel: 86-10-6280-1415 Mobile: 86 - 152 1018 2083

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[commit] r6614 - in trunk/src: southbridge/amd/cimx_wrapper/sb800 vendorcode/amd/cimx/sb800
by repository service May 31, 2011

May 31, 2011

Author: kerry Date: Wed Jun 1 04:00:30 2011 New Revision: 6614 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6614 Log: trivial remove blanks at the end of line Signed-off-by: Kerry She <kerry.she(a)amd.com> Acked-by: Kerry She <kerry.she(a)amd.com> Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c trunk/src/vendorcode/amd/cimx/sb800/SATA.c Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Wed Jun 1 03:56:49 2011 (r6613) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Wed Jun 1 04:00:30 2011 (r6614) @@ -27,7 +27,7 @@ #include "lpc.h" /* lpc_read_resources */ #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ -#include "chip.h" /* struct southbridge_amd_cimx_wrapper_sb800_config */ +#include "chip.h" /* struct southbridge_amd_cimx_wrapper_sb800_config */ /*implement in mainboard.c*/ @@ -363,7 +363,7 @@ /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); #elif (CONFIG_APIC_ID_OFFSET > 0) - /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ + /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ setup_ioapic(ioapic_base, 0); #else #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" Modified: trunk/src/vendorcode/amd/cimx/sb800/SATA.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/SATA.c Wed Jun 1 03:56:49 2011 (r6613) +++ trunk/src/vendorcode/amd/cimx/sb800/SATA.c Wed Jun 1 04:00:30 2011 (r6614) @@ -43,7 +43,7 @@ * *************************************************************************** * */ - + #include "SBPLATFORM.h" #include "cbtypes.h" @@ -317,7 +317,7 @@ } if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) || ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) { - if ( pConfig->BuildParameters.SataAHCISsid != NULL ) { + if ( pConfig->BuildParameters.SataAHCISsid != NULL ) { ddTempVar = pConfig->BuildParameters.SataAHCISsid; } }

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[commit] r6613 - in trunk/src: southbridge/amd/cimx_wrapper/sb800 vendorcode/amd/cimx/sb800
by repository service May 31, 2011

May 31, 2011

Author: kerry Date: Wed Jun 1 03:56:49 2011 New Revision: 6613 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6613 Log: This patch fix a AMD sb800 wrapper compile warning: src/southbridge/amd/cimx_wrapper/sb800/late call clear_ioapic but not include the prototype declare header file. Signed-off-by: Kerry She <kerry.she(a)amd.com> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c trunk/src/vendorcode/amd/cimx/sb800/EC.c trunk/src/vendorcode/amd/cimx/sb800/SATA.c trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h Tue May 24 00:48:13 2011 (r6612) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/cfg.h Wed Jun 1 03:56:49 2011 (r6613) @@ -100,7 +100,7 @@ * @breif INCHIP Sata Controller */ #ifndef SATA_CONTROLLER - #define SATA_CONTROLLER ENABLED + #define SATA_CONTROLLER CIMX_OPTION_ENABLED #endif /** @@ -202,7 +202,7 @@ * @def GPP_CONTROLLER */ #ifndef GPP_CONTROLLER - #define GPP_CONTROLLER ENABLED + #define GPP_CONTROLLER CIMX_OPTION_ENABLED #endif /** Modified: trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c ============================================================================== --- trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Tue May 24 00:48:13 2011 (r6612) +++ trunk/src/southbridge/amd/cimx_wrapper/sb800/late.c Wed Jun 1 03:56:49 2011 (r6613) @@ -21,6 +21,7 @@ #include <device/device.h> /* device_t */ #include <device/pci.h> /* device_operations */ #include <device/pci_ids.h> +#include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <console/console.h> /* printk */ #include "lpc.h" /* lpc_read_resources */ @@ -328,13 +329,13 @@ switch (dev->path.pci.devfn) { case (0x11 << 3) | 0: /* 0:11.0 SATA */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = ENABLED; + sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { - sb_config->SATAMODE.SataMode.SataController = DISABLED; + sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; } sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY @@ -352,11 +353,10 @@ case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ { - u8 byte; u32 ioapic_base; printk(BIOS_INFO, "sm_init().\n"); - ioapic_base = 0xFEC00000; + ioapic_base = IO_APIC_ADDR; clear_ioapic(ioapic_base); /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) @@ -374,9 +374,9 @@ case (0x14 << 3) | 1: /* 0:14:1 IDE */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED; } else { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED; } sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY break; Modified: trunk/src/vendorcode/amd/cimx/sb800/EC.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/EC.c Tue May 24 00:48:13 2011 (r6612) +++ trunk/src/vendorcode/amd/cimx/sb800/EC.c Wed Jun 1 03:56:49 2011 (r6613) @@ -71,7 +71,7 @@ RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1 - if ( pConfig->BuildParameters.EcKbd == ENABLED) { + if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) { //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3); @@ -83,7 +83,7 @@ RWEC8 (0x30, 0x00, 0x01); } - if ( pConfig->BuildParameters.EcChannel0 == ENABLED) { + if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) { //Logical device 0x03 RWEC8 (0x07, 0x00, 0x03); RWEC8 (0x60, 0x00, 0x00); Modified: trunk/src/vendorcode/amd/cimx/sb800/SATA.c ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/SATA.c Tue May 24 00:48:13 2011 (r6612) +++ trunk/src/vendorcode/amd/cimx/sb800/SATA.c Wed Jun 1 03:56:49 2011 (r6613) @@ -470,7 +470,7 @@ if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) { // RIAD or AHCI - if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) { + if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. @@ -631,7 +631,7 @@ //Enable write access to pci header, pm capabilities RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); -// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) { +// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7); // } sataBar5setting (pConfig, &ddBar5); Modified: trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h Tue May 24 00:48:13 2011 (r6612) +++ trunk/src/vendorcode/amd/cimx/sb800/SBTYPE.h Wed Jun 1 03:56:49 2011 (r6613) @@ -1093,13 +1093,13 @@ #pragma pack (pop) /** - * DISABLED - Define disable in module + * CIMX_OPTION_DISABLED - Define disable in module */ -#define DISABLED 0 +#define CIMX_OPTION_DISABLED 0 /** - * ENABLED - Define enable in module + * CIMX_OPTION_ENABLED - Define enable in module */ -#define ENABLED 1 +#define CIMX_OPTION_ENABLED 1 // mov al, code // out 80h, al

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