coreboot November 2011

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Patch set updated for coreboot: 2cc61ee make GPIOs and misc configurable via devicetree
by Florian Zumbiehl 22 Nov '11

22 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/387 -gerrit commit 2cc61ee0fcf4305e54cb12949bb79c325e1b0a74 Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 1 20:19:37 2011 +0100 make GPIOs and misc configurable via devicetree Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315 Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/southbridge/via/vt8237r/chip.h | 5 +++++ src/southbridge/via/vt8237r/lpc.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h index be5e7fc..64b8e8e 100644 --- a/src/southbridge/via/vt8237r/chip.h +++ b/src/southbridge/via/vt8237r/chip.h @@ -71,6 +71,11 @@ struct southbridge_via_vt8237r_config { u8 usb2_dpll_delay; u8 no_int_efgh; + u8 enable_gpo3; + u8 disable_gpo26_gpo27; + u8 enable_aol_2_smb_slave; + u8 enable_gpo5; + u8 gpio15_12_dir_output; }; #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */ diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 5aac518..ceb6d2c 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -159,6 +159,10 @@ static void pci_routing_fixup(struct device *dev) static void setup_pm(device_t dev) { u16 tmp; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; + /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -187,7 +191,10 @@ static void setup_pm(device_t dev) * 5 = Internal PLL reset from susp disabled * 2 = GPO2 is SUSA# */ - pci_write_config8(dev, 0x94, 0xa0); + tmp = 0xa0; + if (cfg && cfg->enable_gpo3) + tmp |= 0x10; + pci_write_config8(dev, 0x94, tmp); /* * 7 = stp to sust delay 1msec @@ -203,7 +210,14 @@ static void setup_pm(device_t dev) #if CONFIG_EPIA_VT8237R_INIT pci_write_config8(dev, 0x95, 0xc2); #else - pci_write_config8(dev, 0x95, 0xcc); + tmp = 0xcc; + if (cfg) { + if (cfg->disable_gpo26_gpo27) + tmp &= ~0x08; + if (cfg->enable_aol_2_smb_slave) + tmp &= ~0x04; + } + pci_write_config8(dev, 0x95, tmp); #endif /* Disable GP3 timer. */ @@ -255,6 +269,9 @@ static void setup_pm(device_t dev) static void vt8237r_init(struct device *dev) { u8 enables; + struct southbridge_via_vt8237r_config *cfg; + + cfg = dev->chip_info; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); @@ -290,8 +307,15 @@ static void vt8237r_init(struct device *dev) */ pci_write_config8(dev, 0xe5, 0x09); + enables = 0x4; + if (cfg) { + if (cfg->enable_gpo5) + enables |= 0x01; + if (cfg->gpio15_12_dir_output) + enables |= 0x10; + } /* REQ5 as PCI request input - should be together with INTE-INTH. */ - pci_write_config8(dev, 0xe4, 0x4); + pci_write_config8(dev, 0xe4, enables); #endif /* Set bit 3 of 0x4f (use INIT# as CPU reset). */

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New patch to review for coreboot: 5b687b2 k8 raminit: add workaround for erratum #181 on non-fam-f
by Florian Zumbiehl 22 Nov '11

22 Nov '11

Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/448 -gerrit commit 5b687b2c7ab6c1ca9647e9e714f87a619029777f Author: Florian Zumbiehl <florz(a)florz.de> Date: Tue Nov 22 21:32:31 2011 +0100 k8 raminit: add workaround for erratum #181 on non-fam-f Disable DRAM controller on non-fam-f CPUs not using fam-f register layout. Change-Id: I2cc87857452555011d69bfebe9f9c4c17cef8f6c Signed-off-by: Florian Zumbiehl <florz(a)florz.de> --- src/cpu/amd/model_fxx/fidvid.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 6395a1e..06ff636 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -45,10 +45,19 @@ static void enable_fid_change(void) pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0xd4, dword); /* disable the DRAM interface at first, it will be enabled - * by raminit again */ + * by raminit again (see also erratum #181) */ +#if CONFIG_K8_REV_F_SUPPORT dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94); dword |= (1 << 14); pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword); +#else + dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x90); + dword |= (1 << 24); + pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x90, dword); + dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94); + dword |= (1 << 25); + pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword); +#endif dword = 0x23070700; /* enable FID/VID change */ // dword = 0x00070000; /* enable FID/VID change */

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Patch set updated for coreboot: 1e2bec3 Remove unused code files and cosmetic changes
by Kyösti Mälkki 22 Nov '11

22 Nov '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/440 -gerrit commit 1e2bec3cb90b23b7b69236c14b882b771e431bdc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 22 20:21:06 2011 +0200 Remove unused code files and cosmetic changes Following files were no longer used in the build and are deleted: src/arch/x86/init/entry.S src/arch/x86/init/ldscript.ld Also fix ugly whitespace in code copyrights and comments. Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/entry.S | 149 ----------------------------------------- src/arch/x86/init/ldscript.ld | 40 ----------- src/cpu/x86/16bit/entry16.inc | 57 ++++++++-------- 3 files changed, 29 insertions(+), 217 deletions(-) diff --git a/src/arch/x86/init/entry.S b/src/arch/x86/init/entry.S deleted file mode 100644 index af29296..0000000 --- a/src/arch/x86/init/entry.S +++ /dev/null @@ -1,149 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 1999 Ronald G. Minnich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <arch/rom_segs.h> - .code16 - .globl _stage0 -_stage0: - cli - - /* Save the BIST result. */ - movl %eax, %ebp; - - /* thanks to kmliu(a)sis.com.tw for this TLB fix */ - /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before - * executing any further code. Even though paging is disabled we - * could still get false address translations due to the TLB if we - * didn't invalidate it. - */ - xorl %eax, %eax - movl %eax, %cr3 /* Invalidate TLB. */ - - /* Switch to protected mode. */ - - /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux) - * using BFD version 2.15.94.0.2.2 20041220 this works fine without all - * the ld hackery and other things. So leave it as is with this comment. - */ - - data32 lgdt %cs:gdtptr - - movl %cr0, %eax - andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */ - orl $0x60000001, %eax /* CD, NW, PE = 1 */ - movl %eax, %cr0 - - /* Restore BIST result. */ - movl %ebp, %eax - - // port80_post(0x23) - /* Now we are in protected mode. Jump to a 32 bit code segment. */ - data32 ljmp $ROM_CODE_SEG, $protected_stage0 - - /* I am leaving this weird jump in here in the event that future gas - * bugs force it to be used. - */ - /* .byte 0x66 */ - .code32 - /* ljmp $ROM_CODE_SEG, $protected_stage0 */ - - /* .code16 */ - .align 4 - .globl gdt16 -gdt16 = . - _stage0 -gdt16x: - .word gdt16xend - gdt16x -1 /* Compute the table limit. */ - .long gdt16x - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 -gdt16xend: - - /* From now on we are 32 bit. */ - .code32 - - /* We have two gdts where we could have one. That is ok. - * - * Let's not worry about this -- optimizing gdt is pointless since - * we're only in it for a little bit. - * - * Btw. note the trick below: The GDT points to ITSELF, and the first - * good descriptor is at offset 8. So you word-align the table, and - * then because you chose 8, you get a nice 64-bit aligned GDT entry, - * which is good as this is the size of the entry. - * Just in case you ever wonder why people do this. - */ - .align 4 - .globl gdtptr - .globl gdt_limit -gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */ - -gdt: -gdtptr: - .word gdt_end - gdt -1 /* Compute the table limit. */ - .long gdt /* We know the offset. */ - .word 0 - - /* selgdt 0x08, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 - - /* selgdt 0x10, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 - -gdt_end: - -/* Reset vector. */ - -/* - * RVECTOR: Size of reset vector, default is 0x10. - * RESRVED: Size of vpd code, default is 0xf0. - * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b). - */ - -SEGMENT_SIZE = 0x10000 -RVECTOR = 0x00010 - -/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here. - * I think we should leave it this way forever, as the bugs come and - * go -- and come again. - * - * .code16 - * .section ".rom.text" - */ -.section ".reset", "ax" - .globl _resetjump -_resetjump: - /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */ - /* jmp _stage0 */ - .byte 0xe9 - .int _stage0 - ( . + 2 ) - - /* Note: The above jump is hand coded to work around bugs in binutils. - * 5 bytes are used for a 3 byte instruction. This works because x86 - * is little endian and allows us to use supported 32 bit relocations - * instead of the weird 16 bit relocations that binutils does not - * handle consistenly between versions because they are used so rarely. - */ diff --git a/src/arch/x86/init/ldscript.ld b/src/arch/x86/init/ldscript.ld deleted file mode 100644 index 149f048..0000000 --- a/src/arch/x86/init/ldscript.ld +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Ronald G. Minnich <rminnich(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -TARGET(binary) -SECTIONS -{ - /DISCARD/ : { - *(.comment) - *(.note.*) - *(.note) - } -} - -SECTIONS { - _ROMTOP = 0xfffffff0; - . = _ROMTOP; - .resetvector . : { - *(.reset) - . = 15 ; - BYTE(0x00); - } -} - diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 9b7b69c..fb21155 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -1,31 +1,32 @@ /* -This software and ancillary information (herein called SOFTWARE ) -called LinuxBIOS is made available under the terms described -here. The SOFTWARE has been approved for release with associated -LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has -been authored by an employee or employees of the University of -California, operator of the Los Alamos National Laboratory under -Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The -U.S. Government has rights to use, reproduce, and distribute this -SOFTWARE. The public may copy, distribute, prepare derivative works -and publicly display this SOFTWARE without charge, provided that this -Notice and any statement of authorship are reproduced on all copies. -Neither the Government nor the University makes any warranty, express -or implied, or assumes any liability or responsibility for the use of -this SOFTWARE. If SOFTWARE is modified to produce derivative works, -such modified SOFTWARE should be clearly marked, so as not to confuse -it with the version available from LANL. - */ -/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL - * rminnich(a)lanl.gov + * This software and ancillary information (herein called SOFTWARE) + * called LinuxBIOS is made available under the terms described here. + * + * The SOFTWARE has been approved for release with associated + * LA-CC Number 00-34. Unless otherwise indicated, this SOFTWARE has + * been authored by an employee or employees of the University of + * California, operator of the Los Alamos National Laboratory under + * Contract No. W-7405-ENG-36 with the U.S. Department of Energy. + * + * The U.S. Government has rights to use, reproduce, and distribute this + * SOFTWARE. The public may copy, distribute, prepare derivative works + * and publicly display this SOFTWARE without charge, provided that this + * Notice and any statement of authorship are reproduced on all copies. + * + * Neither the Government nor the University makes any warranty, express + * or implied, or assumes any liability or responsibility for the use of + * this SOFTWARE. If SOFTWARE is modified to produce derivative works, + * such modified SOFTWARE should be clearly marked, so as not to confuse + * it with the version available from LANL. + * + * Copyright (C) 2000, Ron Minnich rminnich(a)lanl.gov + * Advanced Computing Lab, LANL */ -/** Start code to put an i386 or later processor into 32-bit - * protected mode. +/* Start code to put an i386 or later processor into 32-bit protected mode. */ -/* .section ".rom.text" */ #include <arch/rom_segs.h> .code16 .globl _start @@ -38,12 +39,12 @@ _start: post_code(POST_RESET_VECTOR_CORRECT) -/* thanks to kmliu(a)sis.tw.com for this TBL fix ... */ -/**/ -/* IMMEDIATELY invalidate the translation lookaside buffer before executing*/ -/* any further code. Even though paging is disabled we could still get*/ -/*false address translations due to the TLB if we didn't invalidate it.*/ -/**/ + /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before + * executing any further code. Even though paging is disabled we + * could still get false address translations due to the TLB if we + * didn't invalidate it. Thanks to kmliu(a)sis.com.tw for this TLB fix. + */ + xorl %eax, %eax movl %eax, %cr3 /* Invalidate TLB*/

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New patch to review for coreboot: 25a3cef Bootblock does not need a unique boot_cpu()
by Kyösti Mälkki 22 Nov '11

22 Nov '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/447 -gerrit commit 25a3cef94d64e5aa954e9b61dd9432c1acc2d230 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 22 19:44:45 2011 +0200 Bootblock does not need a unique boot_cpu() Detection of a CPU being a BSP CPU is not dependent of the existence of northbridge and/or southbridge init code in the bootblock. Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP CPU of a hyper-threading CPU and needs to return actual BSP bit from MSR. Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/bootblock_common.h | 5 ----- src/cpu/x86/lapic/boot_cpu.c | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h index 4c4a092..bd19682 100644 --- a/src/arch/x86/include/bootblock_common.h +++ b/src/arch/x86/include/bootblock_common.h @@ -1,9 +1,4 @@ -#if CONFIG_LOGICAL_CPUS && \ - (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT)) #include <cpu/x86/lapic/boot_cpu.c> -#else -#define boot_cpu(x) 1 -#endif #ifdef CONFIG_BOOTBLOCK_CPU_INIT #include CONFIG_BOOTBLOCK_CPU_INIT diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index bca73e1..87418d0 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -1,5 +1,6 @@ #include <cpu/x86/msr.h> +#if CONFIG_SMP static int boot_cpu(void) { int bsp; @@ -8,3 +9,7 @@ static int boot_cpu(void) bsp = !!(msr.lo & (1 << 8)); return bsp; } +#else +#define boot_cpu(x) 1 +#endif +

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New patch to review for coreboot: 4f13c1e Only BSP CPU writes CMOS in bootblock code
by Kyösti Mälkki 22 Nov '11

22 Nov '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/446 -gerrit commit 4f13c1e5ae4dc77e33b30af056fcdee4fea892e8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 22 19:20:22 2011 +0200 Only BSP CPU writes CMOS in bootblock code CMOS accesses are not safe for multi-processor and only the BSP CPU should count reboots and test CMOS sanity. A questionable single byte CMOS read access from AP CPUs remains. Change-Id: I29118e33c07c0080c94abb90f703e38312c72432 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/bootblock_normal.c | 18 ++++++++++++++---- src/arch/x86/init/bootblock_simple.c | 4 ++-- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c index db9d0f9..a0b7b37 100644 --- a/src/arch/x86/init/bootblock_normal.c +++ b/src/arch/x86/init/bootblock_normal.c @@ -3,18 +3,28 @@ static void main(unsigned long bist) { + unsigned long entry; + int boot_mode; + if (boot_cpu()) { bootblock_northbridge_init(); bootblock_southbridge_init(); bootblock_cpu_init(); - } #if CONFIG_USE_OPTION_TABLE - sanitize_cmos(); + sanitize_cmos(); #endif + boot_mode = do_normal_boot(); + } else { + + /* Questionable single byte read from CMOS. + * Do not add any other CMOS access in the + * bootblock for AP CPUs. + */ + boot_mode = last_boot_normal(); + } - unsigned long entry; - if (do_normal_boot()) + if (boot_mode) entry = findstage("normal/romstage"); else entry = findstage("fallback/romstage"); diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c index 5d7c611..41f73b4 100644 --- a/src/arch/x86/init/bootblock_simple.c +++ b/src/arch/x86/init/bootblock_simple.c @@ -6,11 +6,11 @@ static void main(unsigned long bist) bootblock_northbridge_init(); bootblock_southbridge_init(); bootblock_cpu_init(); - } #if CONFIG_USE_OPTION_TABLE - sanitize_cmos(); + sanitize_cmos(); #endif + } const char* target1 = "fallback/romstage"; unsigned long entry;

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Init for multi-processor
by Kyösti Mälkki 22 Nov '11

22 Nov '11

Hi Could someone explain the use of boot_cpu() in bootblock_normal.c main()? I thought only the BSP CPU executes this code (currently)? I am about to push a change that does early SMP init for hyper-threading CPUs to allow cache-as-ram implementation. Shared cache remains disabled until both/all logical CPUs enable it. Thanks, Kyösti

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Re: [coreboot] (no subject)
by Jimmy Pan 22 Nov '11

22 Nov '11

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New patch to review for coreboot: 38d51a3 libpayload: add set_option() function
by Patrick Georgi 22 Nov '11

22 Nov '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/445 -gerrit commit 38d51a3033e667fbde619793de3f8dc127669da6 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 22 13:07:45 2011 +0100 libpayload: add set_option() function It allows to change CMOS values from payloads Change-Id: I4872fc27476923adafe13504126235b92b30de85 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/options.c | 57 ++++++++++++++++++++++++++++-- payloads/libpayload/include/libpayload.h | 1 + 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 394c792..e3f0847 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -91,7 +91,36 @@ static int get_cmos_value(u32 bitnum, u32 len, void *valptr) return 0; } -int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name) +static int set_cmos_value(u32 bitnum, u32 len, void *valptr) +{ + u8 *value = (u8 *)valptr; + int offs = 0; + u32 addr, bit; + u8 reg8; + + /* Convert to byte borders */ + addr=(bitnum / 8); + bit=(bitnum % 8); + + /* Handle single byte or less */ + if (len <= 8) { + reg8 = nvram_read(addr); + reg8 &= ~(((1 << len) - 1) << bit); + reg8 |= (value[0] & ((1 << len) - 1)) << bit; + nvram_write(reg8, addr); + return 0; + } + + /* When handling more than a byte, copy whole bytes */ + while (len > 0) { + len -= 8; + nvram_write(value[offs++], addr++); + } + + return 0; +} + +static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, char *name) { struct cb_cmos_entries *cmos_entry; int len = strnlen(name, CMOS_MAX_NAME_LENGTH); @@ -103,6 +132,17 @@ int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char cmos_entry = (struct cb_cmos_entries*)((unsigned char *)cmos_entry + cmos_entry->size)) { if (memcmp((const char*)cmos_entry->name, name, len)) continue; + return cmos_entry; + } + + printf("ERROR: No such CMOS option (%s)\n", name); + return NULL; +} + +int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name) +{ + struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); + if (cmos_entry) { if(get_cmos_value(cmos_entry->bit, cmos_entry->length, dest)) return 1; @@ -111,8 +151,6 @@ int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char return 0; } - - printf("ERROR: No such CMOS option (%s)\n", name); return 1; } @@ -121,3 +159,16 @@ int get_option(void *dest, char *name) struct cb_cmos_option_table *option_table = phys_to_virt(lib_sysinfo.option_table); return get_option_from(option_table, dest, name); } + +int set_option(void *value, char *name) +{ + struct cb_cmos_option_table *option_table = phys_to_virt(lib_sysinfo.option_table); + struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); + if (cmos_entry) { + set_cmos_value(cmos_entry->bit, cmos_entry->length, value); + fix_options_checksum(); + return 0; + } + return 1; +} + diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 0e892c8..8c8abc4 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -197,6 +197,7 @@ void video_console_set_cursor(unsigned int cursorx, unsigned int cursory); void fix_options_checksum(void); int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name); int get_option(void *dest, char *name); +int set_option(void *value, char *name); /** * @defgroup console Console functions

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New patch to review for coreboot: 66e420b i82801gx: Support power-on-after-power-fail better
by Patrick Georgi 22 Nov '11

22 Nov '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/444 -gerrit commit 66e420bb2be78c6062c2b5a7266f9c56b5abd911 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 22 10:52:43 2011 +0100 i82801gx: Support power-on-after-power-fail better Changing CMOS value for power-on-after-power-fail was only honored after reboot, which is counter intuitive (set from "enable" to "disable", power-off, replug device -> device turns on; and similar cases). Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/southbridge/intel/i82801gx/smihandler.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 85ee2b4..a021d1f 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -310,16 +310,16 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat outl(0, pmbase + GPE0_EN); - /* Should we keep the power state after a power loss? - * In case the setting is "ON" or "OFF" we don't have - * to do anything. But if it's "KEEP" we have to switch - * to "OFF" before entering S5. + /* Always set the flag in case CMOS was changed on runtime. For + * "KEEP", switch to "OFF" - KEEP is software emulated */ - if (s5pwr == MAINBOARD_POWER_KEEP) { - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + if (s5pwr == MAINBOARD_POWER_ON) { + reg8 &= ~1; + } else { reg8 |= 1; - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); } + pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0);

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New patch to review for coreboot: c7965e3 i82801gx: Use CMOS variable if available for power-on on power failure
by Patrick Georgi 22 Nov '11

22 Nov '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/443 -gerrit commit c7965e36565a1674eb8fbb7167b5390dd543a3a4 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Tue Nov 22 10:28:46 2011 +0100 i82801gx: Use CMOS variable if available for power-on on power failure We used a hard coded value for some reason. Don't do that, but use CMOS instead. Change-Id: Ib83aa07a3e55bed075150354a060317ebc9d5ba7 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/southbridge/intel/i82801gx/smihandler.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 48375e4..85ee2b4 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -279,11 +279,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat u8 reg8; u32 reg32; u8 slp_typ; - /* FIXME: the power state on boot should be read from - * CMOS or even better from GNVS. Right now it's hard - * coded at compile time. - */ + u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&s5pwr, "power_on_after_fail"); /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN);

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coreboot November 2011