coreboot October 2011

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501 discussions

New patch to review for coreboot: 9f88de6 fix compilation of intel/sch northbridge code with gcc 4.6
by Stefan Reinauer 14 Oct '11

14 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/264 -gerrit commit 9f88de6eea53205fac34158c9c71f258a159a364 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Oct 13 16:53:11 2011 -0700 fix compilation of intel/sch northbridge code with gcc 4.6 Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/sch/raminit.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/sch/raminit.c b/src/northbridge/intel/sch/raminit.c index 5e49682..ae308ee 100644 --- a/src/northbridge/intel/sch/raminit.c +++ b/src/northbridge/intel/sch/raminit.c @@ -70,6 +70,9 @@ static u32 detect_softstrap_base(void) case 4: base_addr = 0xFFFE0000; break; + default: + base_addr = 0; + die("No valid softstrap base found.\n"); } return base_addr; }

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New patch to review for coreboot: 06fb731 Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6
by Stefan Reinauer 14 Oct '11

14 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/263 -gerrit commit 06fb7317666ca52a7d88292c2a6d890005488e91 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Oct 13 16:52:27 2011 -0700 Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6 Change-Id: I347dd84a61244eed145c02a080309d5a34c5394a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/init/bootblock.ld | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld index eab64cf..dae17bd 100644 --- a/src/arch/x86/init/bootblock.ld +++ b/src/arch/x86/init/bootblock.ld @@ -39,6 +39,7 @@ SECTIONS *(.rodata); *(.rodata.*); *(.rom.data.*); + *(.eh_frame); . = ALIGN(16); _erom = .; }

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Patch merged into coreboot/master: 9570367 Prevent build breakage without consoles enabled
by gerrit＠coreboot.org 13 Oct '11

13 Oct '11

the following patch was just integrated into master: commit 957036708c6ce1396fc1ebbf33e3e3a01af09bc7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 1 14:04:50 2011 -0700 Prevent build breakage without consoles enabled If all console types are disabled, coreboot will fail to compile because static code is unused. This patch fixes the issue. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: Ie9c8bf2a78e3aeba4c2908b06bc03f0f5af37db2 See http://review.coreboot.org/260 for details. -gerrit

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Patch merged into coreboot/master: b043841 Fix compilation of x86emu with gcc 4.6.x
by gerrit＠coreboot.org 13 Oct '11

13 Oct '11

the following patch was just integrated into master: commit b0438411e379d3fa1e3e7f43963138eb2d46a2fd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Oct 4 10:34:37 2011 -0700 Fix compilation of x86emu with gcc 4.6.x gcc 4.6 complains about unused but set variables in x86emu. Particularly some variables are always set but only used in debug mode, or when FPU support is enabled. Change-Id: Ic53bd2303171ab717eb2d2c0ed72744d3eb6989e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/258 for details. -gerrit

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Patch merged into coreboot/master: 6faf97c Fix native x86 option rom initialization
by gerrit＠coreboot.org 13 Oct '11

13 Oct '11

the following patch was just integrated into master: commit 6faf97c0c1a10c44fbfebcd25d8b93967263fdfd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Oct 12 14:35:54 2011 -0700 Fix native x86 option rom initialization - Intel option roms want an initialized i8259 or they will throw an exception 6. This should be done in the southbridge code, but that is executed much later than the VGA init, so initialize the i8259 in src/devices/oprom/x86.c. In the long run this will allow getting rid of some of the ugly hacks in some AMD boards' romstage.c - Don't overwrite the mode when copying mode info information back from 0x600. Change-Id: Idb01f13dbcd736d8d830b222ffe1ea85799fcd9c Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/257 for details. -gerrit

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Patch merged into coreboot/master: b296563 refactor vesa mode setting code and bootsplash code
by gerrit＠coreboot.org 13 Oct '11

13 Oct '11

the following patch was just integrated into master: commit b296563878a245bc138fb213f1fb60e04ae1751a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Oct 12 14:30:59 2011 -0700 refactor vesa mode setting code and bootsplash code - adds possibility to set a vesa mode without showing a bootsplash - make bootsplash / mode setting code available in real mode. Change-Id: I0045c9d75757657f4ce531889593102ea1e39ce5 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/256 for details. -gerrit

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Patch merged into coreboot/master: 38860f7 Refactor option rom initialization code in coreboot.
by gerrit＠coreboot.org 13 Oct '11

13 Oct '11

the following patch was just integrated into master: commit 38860f7f936d58ca777a55dfc3c458feccfc0137 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Oct 12 14:25:07 2011 -0700 Refactor option rom initialization code in coreboot. - move int15 handler out of the generic code into the mainboard directories of those mainboards that actually use it. - move vbe headers to vbe.h - move function prototypes used in native oprom code to x86.h Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/255 for details. -gerrit

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Patch merged into coreboot/master: b49e5b5 Enable/fix compilation of i8254 code in ram stage.
by gerrit＠coreboot.org 13 Oct '11

13 Oct '11

the following patch was just integrated into master: commit b49e5b5bb66a9194728471ed7c04badf5897fb46 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Sep 27 16:26:05 2011 -0700 Enable/fix compilation of i8254 code in ram stage. Change-Id: I3bbe795d8e6e576be9e94d6cd888e78a116ddbbd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/254 for details. -gerrit

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Patch merged into coreboot/master: 7c934a0 Update "STABLE" SeaBIOS selection to release 1.6.3
by gerrit＠coreboot.org 13 Oct '11

13 Oct '11

the following patch was just integrated into master: commit 7c934a0665195ffb523cdc05366492e7acfb0ff0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Oct 12 14:05:49 2011 -0700 Update "STABLE" SeaBIOS selection to release 1.6.3 1.6.3 has a lot of benefits over the previous version, the two most important being: - working AHCI support - compiles with gcc 4.6.x Change-Id: Ie3a4d8f2624e0aa85e48ca09da53474c085838db Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/253 for details. -gerrit

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Patch merged into coreboot/master: 2a52406 Use default table creator macro for all SSDTs
by gerrit＠coreboot.org 13 Oct '11

13 Oct '11

the following patch was just integrated into master: commit 2a5240633d7e9b768f959b24afb2ab199ed2632f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Oct 13 01:18:29 2011 +0200 Use default table creator macro for all SSDTs Change-Id: I0c138ebfdc6d4d5ae7d3512b0dd68df20485690e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/262 for details. -gerrit

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coreboot October 2011