coreboot October 2011

coreboot@coreboot.org

46 participants
501 discussions

how to delete symbol link created at compile time
by She, Kerry 14 Oct '11

14 Oct '11

Hello, Some mainboard support more than one family of CPUs with same socket type, Such as SuperMicro/h8scm: http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.c fm My implementation is the mainboard CPU type can be configured as family10 or family15 CPU. In order to eliminate the duplicated code, both configuration shares most of the platform code, but some code can't be shared between different family of CPUs. Take devicetree.cb as an example, I have created 2 devicetree file : devicetree_f15.cb for platform with family 15 CPU devicetree_f10.cb for platform with family 10 CPU I changed the makefile to create a symbol link "devicetree.cb" link to devicetree_f10.cb or devicetree_f15.cb at compile time. The problem is that I can't delete the symbol link when make clean/distclean. I found that make clean/distclean will not traverse the src/ directory. How can I get this symbol link removed when doing a make clean. Any other suggestion is welcome. Regards, Kerry Sheh < kerry.she(a)amd.com> Tel: 86-10-6280-1415 Mobile: 86 - 152 1018 2083

3 2

Re: [coreboot] [SeaBIOS] usb boot issue
by Marshall Buschman 14 Oct '11

14 Oct '11

On 10/14/2011 10:49 AM, Wolfgang Kamp - datakamp wrote: > Hi Kevin, > > the problem occurs when I try to boot from USB Stick on AMD DBFT1 Persimmon board. > I have tried a couple of sticks in different USB slots but it is always the same issue. > If Ubuntu has booted from HD the stick will be recognized correctly. > The log is attached. Tell me if you need more information. > In testing on the ASRock E350M1 (also SB800-based), I am not able to correctly access USB disks under linux. Reads fail and the USB disk device disappears and reappears. The time before failure appears to be random, although the most data I've been able to read from the device (using a simple file copy) is 500MB. I do not believe failure will occur unless you attempt to read data from the USB disk. You said you're able to boot from the hard drive, and then read from the USB disk correctly. It would be interesting to know if once booted, you can read significant quantities of data reliably. I am guessing you will not be able to, and that whatever bug causes this is also responsible for the USB boot issue. > Regards > > Wolfgang > > > -----Ursprüngliche Nachricht----- > Von: Kevin O'Connor [mailto:kevin@koconnor.net] > Gesendet: Freitag, 14. Oktober 2011 01:15 > An: Wolfgang Kamp - datakamp > Cc: coreboot(a)coreboot.org; seabios(a)seabios.org > Betreff: Re: [SeaBIOS] usb boot issue > > On Thu, Oct 13, 2011 at 03:56:48PM +0200, Wolfgang Kamp - datakamp wrote: >> Hi, >> >> is there any solution for the usb boot issue of the AMD SB800 Persimmon platform >> with SeaBIOS 1.6.3 and actual Coreboot version? > I'm unfamiliar with the issue. Can you post the SeaBIOS debug output > along with a description of the issue you are seeing? > > -Kevin > > >

1 0

Patch set updated for coreboot: d2e2c79 console: support integrated 7-segment displays for POST codes
by Christoph Grenz 14 Oct '11

14 Oct '11

Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/221 -gerrit commit d2e2c796580078a568d66e59db805ceb69a1e774 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Sun Sep 18 22:54:51 2011 +0200 console: support integrated 7-segment displays for POST codes Add a configuration option POST_PORT which defaults to 0x80 and can be redefined by boards which have integrated POST displays on another I/O port. Change post.c to output POST codes to this port instead of 0x80 hardcoded. Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/console/Kconfig | 4 ++++ src/console/post.c | 2 +- 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 02244d7..8382695 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -333,6 +333,10 @@ config NO_POST bool "Don't show any POST codes" default n +config POST_PORT + int + default 0x80 + config CONSOLE_POST bool "Show POST codes on the debug console" depends on !NO_POST diff --git a/src/console/post.c b/src/console/post.c index 3872c2d..7fc9d6f 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -32,6 +32,6 @@ void post_code(uint8_t value) print_emerg_hex8(value); print_emerg("\n"); #endif - outb(value, 0x80); + outb(value, CONFIG_POST_PORT); #endif }

1 0

Patch merged into coreboot/master: 9f88de6 fix compilation of intel/sch northbridge code with gcc 4.6
by gerrit＠coreboot.org 14 Oct '11

14 Oct '11

the following patch was just integrated into master: commit 9f88de6eea53205fac34158c9c71f258a159a364 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Oct 13 16:53:11 2011 -0700 fix compilation of intel/sch northbridge code with gcc 4.6 Change-Id: I57804dff9e37f0127900ebb7a67118382944eb89 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/264 for details. -gerrit

1 0

Patch merged into coreboot/master: 06fb731 Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6
by gerrit＠coreboot.org 14 Oct '11

14 Oct '11

the following patch was just integrated into master: commit 06fb7317666ca52a7d88292c2a6d890005488e91 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Oct 13 16:52:27 2011 -0700 Add eh_frame to rom section to fix compilation of coreboot with gcc 4.6 Change-Id: I347dd84a61244eed145c02a080309d5a34c5394a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/263 for details. -gerrit

1 0

Re: [coreboot] how to delete symbol link created at compile time
by She, Kerry 14 Oct '11

14 Oct '11

Hello, Marc > -----Original Message----- > From: Marc Jones [mailto:marcj303@gmail.com] > Sent: Friday, October 14, 2011 12:22 PM > To: She, Kerry > Cc: coreboot > Subject: Re: [coreboot] how to delete symbol link created at compile time > > On Thu, Oct 13, 2011 at 3:19 AM, She, Kerry <Kerry.She(a)amd.com> wrote: > > Hello, > > > > > > > > Some mainboard support more than one family of CPUs with same socket > type, > > > > Such as SuperMicro/h8scm: > > > > http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM- > F.cfm > > > > > > > > My implementation is the mainboard CPU type can be configured as > family10 or > > family15 CPU. > > > > In order to eliminate the duplicated code, both configuration shares > most of > > the platform code, > > > > but some code can't be shared between different family of CPUs. > > > > Take devicetree.cb as an example, > > > > I have created 2 devicetree file : > > > > devicetree_f15.cb for platform with family 15 CPU > > > > devicetree_f10.cb for platform with family 10 CPU > > > > > > > > I changed the makefile to create a symbol link "devicetree.cb" link to > > devicetree_f10.cb or devicetree_f15.cb at compile time. > > > > The problem is that I can't delete the symbol link when make > > clean/distclean. > > > > > > > > I found that make clean/distclean will not traverse the src/ directory. > > > > How can I get this symbol link removed when doing a make clean. > > > > Any other suggestion is welcome. > > > > Regards, > > Kerry Sheh < kerry.she(a)amd.com> > > Tel: 86-10-6280-1415 > > Mobile: 86 - 152 1018 2083 > > Kerry, > > I thought about a recursive call through the subdirs to do a make > clean, but that would make a lot of errors for most Makefiles.inc > because they don't have a clean target. I wonder if there is a better > way. Yes, you are right! My temporary solution is adding a target in the mainboard Makefile, not modify any of the top level Makefile. --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -50,3 +50,5 @@ endif subdirs-y += ../../../../$(AGESA_ROOT) +clean-mainboard: + $(RM) $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb But I think a better and more generic solution should be considered. thanks

1 0

New patch to review for coreboot: 634373f Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6
by Stefan Reinauer 14 Oct '11

14 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/268 -gerrit commit 634373f4296d80fb0cb6f7df669351f83788d4ee Author: Stefan Reinauer <reinauer(a)google.com> Date: Thu Oct 13 17:26:43 2011 -0700 Fix AMD SB800 (cimx) southbridge code to compile with gcc 4.6 Change-Id: I672135a9b6e3b641ceb655cb00d40ee760c17edc Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 164a651..d7317a2 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -155,4 +155,7 @@ typedef union _PCI_ADDR { #define cimEhciTrafficHandingDefault FALSE #define cimFusionMsgCMultiCoreDefault FALSE #define cimFusionMsgCStageDefault FALSE + +#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" + #endif // _AMD_SBPLATFORM_H_

1 0

New patch to review for coreboot: 8b99e13 Fix compilation of AMD GX2 northbridge code with gcc 4.6
by Stefan Reinauer 14 Oct '11

14 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/267 -gerrit commit 8b99e131dab9680feb84d4a1e126b58ea12aa8d0 Author: Stefan Reinauer <reinauer(a)google.com> Date: Thu Oct 13 17:26:10 2011 -0700 Fix compilation of AMD GX2 northbridge code with gcc 4.6 Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/amd/gx2/northbridgeinit.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index fd8d3f9..e4aaa8b 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -485,7 +485,7 @@ performance: static void GeodeLinkPriority(void) { - msr_t msr; + msr_t msr = { 0, 0 }; struct msrinit *prio = GeodeLinkPriorityTable; int i; @@ -526,7 +526,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) /* ok this is whacky bit translation time. */ int bit; uint8_t shadowByte; - msr_t msr; + msr_t msr = { 0, 0 }; shadowByte = (uint8_t) (shadowLo >> 16); /* load up D000 settings in edx. */

1 0

New patch to review for coreboot: 4876404 AMD CPU and chipset fixes for compilation with gcc 4.6
by Stefan Reinauer 14 Oct '11

14 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/266 -gerrit commit 48764047d8720e3e6f9ae9119f8ae16b9d875cd7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Oct 13 17:04:02 2011 -0700 AMD CPU and chipset fixes for compilation with gcc 4.6 Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/amd/amdk8/early_ht.c | 4 ++-- src/northbridge/amd/amdk8/incoherent_ht.c | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 ++-- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 2 +- src/southbridge/amd/rs780/rs780.c | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index bf80ef8..2ecc0d0 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -16,8 +16,8 @@ static void enumerate_ht_chain(void) device_t dev; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE - unsigned real_last_unitid; - uint8_t real_last_pos; + unsigned real_last_unitid = 0; + uint8_t real_last_pos = 0; int ht_dev_num = 0; // except host_bridge uint8_t end_used = 0; #endif diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 4d0d025..a14adac 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -305,8 +305,8 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE - unsigned real_last_unitid; - uint8_t real_last_pos; + unsigned real_last_unitid = 0; + uint8_t real_last_pos = 0; int ht_dev_num = 0; uint8_t end_used = 0; #endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1191536..1faed5a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1353,7 +1353,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, u16 tCKproposed16x; u8 CLactual, CLdesired, CLT_Fail; - u8 smbaddr, byte, bytex; + u8 smbaddr, byte = 0, bytex = 0; CASLatLow = 0xFF; CASLatHigh = 0xFF; @@ -2768,7 +2768,7 @@ static void Get_DqsRcvEnGross_Diff(struct DCTStatStruc *pDCTstat, static void Get_WrDatGross_Diff(struct DCTStatStruc *pDCTstat, u8 dct, u32 dev, u32 index_reg) { - u8 Smallest, Largest; + u8 Smallest = 0, Largest = 0; u32 val; u8 byte, bytex; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 54fdedf..3e1b13d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -849,7 +849,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat u32 value; u8 j; u32 value_test; - u32 value_r, value_r_test; + u32 value_r = 0, value_r_test = 0; u8 pattern, channel, BeatCnt; struct DCTStatStruc *ptrAddr; diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index b8c7d04..cf6d2df 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -190,7 +190,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) { /* NB_InitGFXStraps */ u32 MMIOBase, apc04, apc18, apc24, romstrap2; - msr_t pcie_mmio_save; + msr_t pcie_mmio_save = { 0, 0 }; volatile u32 * strap; // disable processor pcie mmio, if enabled

1 0

New patch to review for coreboot: 59f4c2c Fix compilation of VIA CN700 northbridge code with gcc 4.6
by Stefan Reinauer 14 Oct '11

14 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/265 -gerrit commit 59f4c2c0d334d96a6045ba12782c318cbda01997 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Oct 13 17:03:04 2011 -0700 Fix compilation of VIA CN700 northbridge code with gcc 4.6 Change-Id: Ia52d21c5c467ec08bc7b958ee1a8e37e7d3e025b Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/via/cn700/raminit.c | 12 ++++++++++-- 1 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index df4010e..2c387bb 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -179,12 +179,20 @@ static void sdram_set_size(const struct mem_controller *ctrl) case 0x01: result = 0x10; /* 1GB */ break; + default: + result = 0; } - if (result == 0xff) + switch (result) { + case 0xff: die("DRAM module size too big, not supported by CN700\n"); - else + break; + case 0: + die("DRAM module has unknown density\n"); + break; + default: printk(BIOS_DEBUG, "Found %iMB of ram\n", result * ranks * 64); + } pci_write_config8(ctrl->d0f3, 0x40, result); pci_write_config8(ctrl->d0f3, 0x48, 0x00);

1 0

← Newer
1
...
33
34
35
36
37
38
39
...
51
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot October 2011