coreboot October 2011

coreboot@coreboot.org

46 participants
501 discussions

Re: [coreboot] some url for SB700 in Wiki broken
by Peter Stuge 15 Oct '11

15 Oct '11

mopz0506 mopz0506 wrote: > the new url is : http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf > the new url is: http://developer.amd.com/assets/45215_sb710_ds_pub_1.25.pdf I've updated all URLs for SB7x0. Thanks. //Peter

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some url for SB700 in Wiki broken
by mopz0506 mopz0506 15 Oct '11

15 Oct '11

Hi, I tried to download SB700 manual and it seems broken, in this page: http://www.coreboot.org/Datasheets#AMD_SB700.2FSB710.2FSB750 the guest disabled to edit it so I report it here. AMD SB700/710/750 BIOS Developer’s Guide (BDG) http://support.amd.com/us/Embedded_TechDocs/43366_sb7xx_bdg_pub_1.00.pdf the new url is : http://developer.amd.com/assets/43366_sb7xx_bdg_pub_1.00.pdf AMD SB710 Databook http://support.amd.com/us/Embedded_TechDocs/45215_sb710_ds_pub_1.25.pdf the new url is: http://developer.amd.com/assets/45215_sb710_ds_pub_1.25.pdf Thank you, mopz0506

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How to make "System Restart after Power Fail" working on SB800?
by mopz0506 mopz0506 15 Oct '11

15 Oct '11

Hi, My mainboard is ASRock E350M1, it's sourthbridge is AMD SB800. I want the machine to restart once I connect the power cable to it, without press the POWER button on the front panel. The ASRock's EFI BIOS can do this by set "Always Power On" to "enable". At present the coreboot (the cimx module) seems does not touch "System Restart after Power Fail" feature. If I use vendor's EFI BIOS and set "always restart after the power is restored", then flash the coreboot to it, the box always restart when power connected and I need not to press the POWER button. If I use vendor's EFI BIOS and set "keep power off after the power is restored", then flash the coreboot to it, the box does not up and I must press the POWER button. If I clear the BIOS by connect the jumper to (pin1 - pin2), then all setting lost and I must press the POWER button. So seems the coreboot just use the setting (but never set it). I think the code is in src\vendorcode\amd\cimx\sb800\SBPOR.c const static AcpiRegWrite sbPmioPorInitTable[] = ...... {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3}, ...... } and yes it does not touch the BIT1. The BIOS Developer's Guide 3.6, P20, said I must to set PMIO 74h [bits 1:0] to [01b] to get "always power on" working. [00] / [10] / [11] does not work as what I hope. So I change the line to always clean BIT1 to 0, as BDG required, {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF4, BIT0 + BIT3}, (just for test, I think the proper way is give a pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr to overwrite CIMX's default setting) but it has no effect, the box keep off until I press POWER button. before this code PMIO 24h [AcpiMMioEn] has been enabled so MMIO working. I checked the SB700 code src\southbridge\amd\sb700\sm.c, to see how coreboot set "power_on_after_fail" bit in other chipset. =================== code start ================= /* power after power fail */ on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pm_ioread(0x74); byte &= ~0x03; if (on) { byte |= 2; } byte |= 1 << 2; pm_iowrite(0x74, byte); printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); =================== code end ================= what it did is a litter different and always set bit0 to 0 (CIMX set bit0 to 1, which is required by the manual): 1) clear bit[1:0] to [00b] 2) set bit[1] to [1b] 3) set bit[2] to [1b] I don't know this code working or not since I do not own a SB700 mainboard. If I did it on SB800 as below {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xFC, BIT1 + BIT2}, coreboot fail to boot. SB800 obsolete those coreboot code and replace it with new CIMX code. I read the documents about all PM registers, and found nothing. I search "power" in the whole .pdf, but most of them is difficult to understand for me. I search the archive of mail list and seems every mainboard has different method to set this feature. I had tried set it on superio code (Winbond W83267hf), and does not work. Also I observe that BIT0 is "Decen_acpi", and BIT1 is "Gbl_en_en", and they are not "power on after power fail" bit. Did I did anything wrong? Did these bits need some ACPI code to working? When the power cable connected, before I press the POWER button, the mainboard keeps off due to the setting. in this case, the BIOS code running or not? Any suggesting? Thanks for your help in advance, mopz0506

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New patch to review for coreboot: faa83fd Move linux 2.6.11 workaround to generic code
by Patrick Georgi 15 Oct '11

15 Oct '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/280 -gerrit commit faa83fd3074371696f40629a174dad2e883a7553 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Oct 14 23:02:57 2011 +0200 Move linux 2.6.11 workaround to generic code Linux 2.6.11 seems to require a certain order in CPUs listed in mptable, so enforce it. This was only done on arima/hdama, but now is generic. Unfortunately this is somewhat slow. Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/boot/mpspec.c | 15 +++++++--- src/mainboard/arima/hdama/mptable.c | 50 +---------------------------------- 2 files changed, 12 insertions(+), 53 deletions(-) diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c index 209e0bb..d519cfa 100644 --- a/src/arch/x86/boot/mpspec.c +++ b/src/arch/x86/boot/mpspec.c @@ -134,6 +134,7 @@ void smp_write_processor(struct mp_config_table *mc, void smp_write_processors(struct mp_config_table *mc) { int boot_apic_id; + int order_id; unsigned apic_version; unsigned cpu_features; unsigned cpu_feature_flags; @@ -145,6 +146,8 @@ void smp_write_processors(struct mp_config_table *mc) result = cpuid(1); cpu_features = result.eax; cpu_feature_flags = result.edx; + /* order the output of the cpus to fix a bug in kernel 2.6.11 */ + for(order_id = 0;order_id <256; order_id++) { for(cpu = all_devices; cpu; cpu = cpu->next) { unsigned long cpu_flag; if ((cpu->path.type != DEVICE_PATH_APIC) || @@ -159,10 +162,14 @@ void smp_write_processors(struct mp_config_table *mc) if (boot_apic_id == cpu->path.apic.apic_id) { cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; } - smp_write_processor(mc, - cpu->path.apic.apic_id, apic_version, - cpu_flag, cpu_features, cpu_feature_flags - ); + if(cpu->path.apic.apic_id == order_id) { + smp_write_processor(mc, + cpu->path.apic.apic_id, apic_version, + cpu_flag, cpu_features, cpu_feature_flags + ); + break; + } + } } } diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 19bbf25..466ba88 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -11,54 +11,6 @@ #define HT_INIT_CONTROL 0x6c #define HTIC_BIOSR_Detect (1<<5) -/* If we assume a symmetric processor configuration we can - * get all of the information we need to write the processor - * entry from the bootstrap processor. - * Plus I don't think linux really even cares. - * Having the proper apicid's in the table so the non-bootstrap - * processors can be woken up should be enough. Linux-2.6.11 work-around. - */ -static void smp_write_processors_inorder(struct mp_config_table *mc) -{ - int boot_apic_id; - int order_id; - unsigned apic_version; - unsigned cpu_features; - unsigned cpu_feature_flags; - struct cpuid_result result; - device_t cpu; - - boot_apic_id = lapicid(); - apic_version = lapic_read(LAPIC_LVR) & 0xff; - result = cpuid(1); - cpu_features = result.eax; - cpu_feature_flags = result.edx; - /* order the output of the cpus to fix a bug in kernel 6 11 */ - for(order_id = 0;order_id <256; order_id++) { - for(cpu = all_devices; cpu; cpu = cpu->next) { - unsigned long cpu_flag; - if ((cpu->path.type != DEVICE_PATH_APIC) || - (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) - { - continue; - } - if (!cpu->enabled) { - continue; - } - cpu_flag = MPC_CPU_ENABLED; - if (boot_apic_id == cpu->path.apic.apic_id) { - cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; - } - if(cpu->path.apic.apic_id == order_id) { - smp_write_processor(mc, - cpu->path.apic.apic_id, apic_version, - cpu_flag, cpu_features, cpu_feature_flags); - break; - } - } - } -} - static unsigned node_link_to_bus(unsigned node, unsigned link) { device_t dev; @@ -125,7 +77,7 @@ static void *smp_write_config_table(void *v) mptable_init(mc, LAPIC_ADDR); - smp_write_processors_inorder(mc); + smp_write_processors(mc); apicid_base = max_apicid() + 1; apicid_8111 = apicid_base;

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New patch to review for coreboot: 7ae18c2 Fix our CMOS checksum algorithm so it matches what /dev/nvram expects
by Stefan Reinauer 15 Oct '11

15 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/279 -gerrit commit 7ae18c212c2ccca0c7f4691db0bfb5c89d8ce0ac Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:24:03 2011 -0700 Fix our CMOS checksum algorithm so it matches what /dev/nvram expects Our cmos checksum is inverted to what the Linux /dev/nvram device expects (and BIOSes use). This makes it impossible to use /dev/nvram with coreboot. Fix it! Change-Id: I239f7e3aca05d3691aee16490dd801df2ccaefd1 Signed-off-by: Vadim Bendebury <vbendeb(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/mc146818rtc.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c index f3bee9b..034957a 100644 --- a/src/pc80/mc146818rtc.c +++ b/src/pc80/mc146818rtc.c @@ -98,7 +98,6 @@ static void rtc_set_checksum(int range_start, int range_end, int cks_loc) for(i = range_start; i <= range_end; i++) { sum += cmos_read(i); } - sum = ~(sum & 0x0ffff); cmos_write(((sum >> 8) & 0x0ff), cks_loc); cmos_write(((sum >> 0) & 0x0ff), cks_loc+1); }

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New patch to review for coreboot: 30cb6c7 rework RTC driver output to make it more consistent.
by Stefan Reinauer 15 Oct '11

15 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/278 -gerrit commit 30cb6c723bce9cac3c8e5af1b1458352d7e68002 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:22:52 2011 -0700 rework RTC driver output to make it more consistent. Also add a meaningful define (Not hooked up in Kconfig, that might or might not follow) Change-Id: I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/pc80/mc146818rtc.c | 13 ++++++++----- 1 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c index 4bbfa9e..f3bee9b 100644 --- a/src/pc80/mc146818rtc.c +++ b/src/pc80/mc146818rtc.c @@ -132,12 +132,14 @@ void rtc_init(int invalid) checksum_invalid = !rtc_checksum_valid(PC_CKS_RANGE_START, PC_CKS_RANGE_END,PC_CKS_LOC); +#define CLEAR_CMOS 0 if (invalid || cmos_invalid || checksum_invalid) { - printk(BIOS_WARNING, "RTC:%s%s%s zeroing cmos\n", + printk(BIOS_WARNING, "RTC:%s%s%s%s\n", invalid?" Clear requested":"", cmos_invalid?" Power Problem":"", - checksum_invalid?" Checksum invalid":""); -#if 0 + checksum_invalid?" Checksum invalid":"", + CLEAR_CMOS?" zeroing cmos":""); +#if CLEAR_CMOS cmos_write(0, 0x01); cmos_write(0, 0x03); cmos_write(0, 0x05); @@ -169,7 +171,7 @@ void rtc_init(int invalid) checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END,LB_CKS_LOC); if(checksum_invalid) - printk(BIOS_DEBUG, "Invalid CMOS LB checksum\n"); + printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n"); /* Make certain we have a valid checksum */ rtc_set_checksum(PC_CKS_RANGE_START, @@ -229,7 +231,8 @@ int get_option(void *dest, const char *name) /* find the requested entry record */ ct=cbfs_find_file("cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT); if (!ct) { - printk(BIOS_ERR, "cmos_layout.bin could not be found. Options are disabled\n"); + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); return(-2); } ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);

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New patch to review for coreboot: 027f405 use byteorder.h instead of implementing another byte swap function
by Stefan Reinauer 15 Oct '11

15 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/277 -gerrit commit 027f405c81ed81698bc089a742a7e05a8b3d7ad4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:19:21 2011 -0700 use byteorder.h instead of implementing another byte swap function Change-Id: Id5fe7b597256ddf5d4ef408ec82cd94d84e7a0cd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/boot/selfboot.c | 8 +------- 1 files changed, 1 insertions(+), 7 deletions(-) diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index 5f7a8f1..7ae9f8c 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ +#include <arch/byteorder.h> #include <console/console.h> #include <fallback.h> #include <boot/elf.h> @@ -30,13 +31,6 @@ #include <cbfs.h> #include <lib.h> -#if !CONFIG_BIG_ENDIAN -#define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \ - ((x&0xff0000) >> 8) | ((x&0xff000000) >> 24) ) -#else -#define ntohl(x) (x) -#endif - /* Maximum physical address we can use for the coreboot bounce buffer. */ #ifndef MAX_ADDR

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New patch to review for coreboot: 4c00556 use acpi.h include instead of manually adding acpi_slp_type.
by Stefan Reinauer 15 Oct '11

15 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/276 -gerrit commit 4c00556c2f3a2a814c3a484f4ee924c5678037b0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:18:29 2011 -0700 use acpi.h include instead of manually adding acpi_slp_type. Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/northbridge/intel/i945/northbridge.c | 3 +-- src/northbridge/intel/sch/northbridge.c | 3 +-- src/southbridge/intel/i82801gx/lpc.c | 3 +-- src/southbridge/via/vt8237r/lpc.c | 4 +--- 4 files changed, 4 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index dfe4fe7..a10bb4a 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -29,6 +29,7 @@ #include <bitops.h> #include <cpu/cpu.h> #include <boot/tables.h> +#include <arch/acpi.h> #include "chip.h" #include "i945.h" @@ -252,8 +253,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } #if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; - static void northbridge_init(struct device *dev) { switch (pci_read_config32(dev, SKPAD)) { diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index ccd0d33..7b7c67b 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -29,6 +29,7 @@ #include <bitops.h> #include <cpu/cpu.h> #include <boot/tables.h> +#include <arch/acpi.h> #include "chip.h" #include "sch.h" @@ -267,8 +268,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } #if CONFIG_HAVE_ACPI_RESUME -extern u8 acpi_slp_type; - static void northbridge_init(struct device *dev) { switch (pci_read_config32(dev, SKPAD)) { diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index b4b2f41..ab3c915 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -27,6 +27,7 @@ #include <pc80/i8259.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> #include <cpu/cpu.h> #include "i82801gx.h" #include <cpu/x86/smm.h> @@ -170,8 +171,6 @@ static void i82801gx_gpi_routing(device_t dev) pci_write_config32(dev, 0xb8, reg32); } -extern u8 acpi_slp_type; - static void i82801gx_power_options(device_t dev) { u8 reg8; diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index 61f4989..3e2f215 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -32,6 +32,7 @@ #include <pc80/keyboard.h> #include <pc80/i8259.h> #include <stdlib.h> +#include <arch/acpi.h> #include "vt8237r.h" #include "chip.h" @@ -147,9 +148,6 @@ static void pci_routing_fixup(struct device *dev) * This avoids having to handle any System Management Interrupts (SMIs). */ -extern u8 acpi_slp_type; - - static void setup_pm(device_t dev) { u16 tmp;

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New patch to review for coreboot: 20a75ca Add macros for 64bit byte order swapping
by Stefan Reinauer 15 Oct '11

15 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/275 -gerrit commit 20a75ca9c0a326ab4113311f6a56dd668be4e283 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:11:16 2011 -0700 Add macros for 64bit byte order swapping Change-Id: Ic31ccd41ba3e0af7046eafc29221810d4cd196c8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/byteorder.h | 4 ++++ src/include/swab.h | 11 +++++++++++ 2 files changed, 15 insertions(+), 0 deletions(-) diff --git a/src/arch/x86/include/arch/byteorder.h b/src/arch/x86/include/arch/byteorder.h index ab344e6..7ba6290 100644 --- a/src/arch/x86/include/arch/byteorder.h +++ b/src/arch/x86/include/arch/byteorder.h @@ -5,10 +5,14 @@ #include <swab.h> +#define cpu_to_le64(x) ((unsigned long)(x)) +#define le64_to_cpu(x) ((unsigned long)(x)) #define cpu_to_le32(x) ((unsigned int)(x)) #define le32_to_cpu(x) ((unsigned int)(x)) #define cpu_to_le16(x) ((unsigned short)(x)) #define le16_to_cpu(x) ((unsigned short)(x)) +#define cpu_to_be64(x) swab64(x) +#define be64_to_cpu(x) swab64(x) #define cpu_to_be32(x) swab32((x)) #define be32_to_cpu(x) swab32((x)) #define cpu_to_be16(x) swab16((x)) diff --git a/src/include/swab.h b/src/include/swab.h index 3a16686..c5e4370 100644 --- a/src/include/swab.h +++ b/src/include/swab.h @@ -30,4 +30,15 @@ (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \ (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) )) +#define swab64(x) \ + ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56) )) + #endif /* _SWAB_H */

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New patch to review for coreboot: 43c4af9 reformat Makefile.bootblock.inc (>80 lines per char)
by Stefan Reinauer 15 Oct '11

15 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/274 -gerrit commit 43c4af942273a396bda883d7f4f92c17f3a9c408 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:09:25 2011 -0700 reformat Makefile.bootblock.inc (>80 lines per char) Change-Id: I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/Makefile.bootblock.inc | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/arch/x86/Makefile.bootblock.inc b/src/arch/x86/Makefile.bootblock.inc index f076238..806afea 100644 --- a/src/arch/x86/Makefile.bootblock.inc +++ b/src/arch/x86/Makefile.bootblock.inc @@ -5,7 +5,8 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL) @printf " CBFS $(subst $(obj)/,,$(@))\n" rm -f $@ cp $(obj)/coreboot.pre1 $@ - $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) + $(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \ + $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt) #FIXME: location.txt might require an offset of header size #######################################################################

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coreboot October 2011