coreboot October 2011

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New patch to review for coreboot: 6cf3c92 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
by Sven Schnelle 15 Oct '11

15 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/282 -gerrit commit 6cf3c92e3b8d09814af569a4f1a5d64e3c572241 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sat Oct 15 17:31:01 2011 +0200 T60: Add support for Ultrabay Legacy I/O devices (40Y8122) Those modules have basically the same Super I/O capabilities as the Docking station. Unfortunately, the Super I/O in the module shares the same I/O address as the Docking station, so we're not allowed to connect the LPC Docking Bus if such a module is present. To be able to detect this device and use it as early console for coreboot, we have to initialize the GPIO Controller before, as this device is detected via GPIO06. Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/dock.c | 30 +++++++++++++++++++++++++++++- src/mainboard/lenovo/t60/dock.h | 3 +++ src/mainboard/lenovo/t60/mainboard.c | 7 ++++++- src/mainboard/lenovo/t60/mainboard_smi.c | 7 ++++++- src/mainboard/lenovo/t60/romstage.c | 20 +++++++++++++------- 5 files changed, 57 insertions(+), 10 deletions(-) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 6642bb3..f0b5a3d 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -28,6 +28,7 @@ #include "dock.h" #include "superio/nsc/pc87384/pc87384.h" #include "ec/acpi/ec.h" +#include "ec/lenovo/pmh7/pmh7.h" #include "southbridge/intel/i82801gx/i82801gx.h" static void dlpc_write_register(int reg, int value) @@ -108,6 +109,9 @@ int dlpc_init(void) /* Activate DLPC */ dlpc_write_register(0x30, 0x01); + /* Reset docking state */ + outb(0x00, 0x164c); + dlpc_gpio_init(); return 0; } @@ -127,7 +131,7 @@ static int dock_superio_init(void) /* set GPIO pins to Serial/Parallel Port * functions */ - dock_write_register(0x22, 0xeb); + dock_write_register(0x22, 0xa9); dock_write_register(0x07, PC87384_GPIO); dock_write_register(0x60, 0x16); @@ -217,3 +221,27 @@ int dock_present(void) return inb(0x15ee) & 1; } +static void pmh7_write(int reg, u8 val) +{ + outb(reg, EC_LENOVO_PMH7_ADDR); + outb(val, EC_LENOVO_PMH7_DATA); +} + +static u8 pmh7_read(int reg) +{ + outb(reg, EC_LENOVO_PMH7_ADDR); + return inb(EC_LENOVO_PMH7_DATA); +} + +int legacy_io_present(void) +{ + return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40); +} + +void legacy_io_init(void) +{ + /* Enable Power for Ultrabay slot */ + pmh7_write(0x62, pmh7_read(0x62) & ~0x01); + udelay(100000); + dock_superio_init(); +} diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h index 9d35d9f..631f007 100644 --- a/src/mainboard/lenovo/t60/dock.h +++ b/src/mainboard/lenovo/t60/dock.h @@ -24,4 +24,7 @@ extern int dock_connect(void); extern void dock_disconnect(void); extern int dock_present(void); extern int dlpc_init(void); + +extern int legacy_io_present(void); +extern void legacy_io_init(void); #endif diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 2b8c5fe..5da6318 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -50,7 +50,12 @@ static void mainboard_enable(device_t dev) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); - if (idedev && idedev->chip_info && h8_ultrabay_device_present()) { + + if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) { + /* legacy I/O connected */ + pmh7_ultrabay_power_enable(1); + ec_write(0x0c, 0x84); + } else if (idedev && idedev->chip_info && h8_ultrabay_device_present()) { struct southbridge_intel_i82801gx_config *config = idedev->chip_info; config->ide_enable_primary = 1; pmh7_ultrabay_power_enable(1); diff --git a/src/mainboard/lenovo/t60/mainboard_smi.c b/src/mainboard/lenovo/t60/mainboard_smi.c index 4a0b506..2ab1d4d 100644 --- a/src/mainboard/lenovo/t60/mainboard_smi.c +++ b/src/mainboard/lenovo/t60/mainboard_smi.c @@ -75,7 +75,12 @@ int mainboard_io_trap_handler(int smif) switch (smif) { case SMI_DOCK_CONNECT: - dlpc_init(); + /* If there's an legacy I/O module present, we're not + allowed to connect the Docking LPC Bus, as both Super I/O + chips are using 0x2e as base address. */ + if (legacy_io_present()) + break; + if (!dock_connect()) { /* set dock LED to indicate status */ ec_write(0x0c, 0x08); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 252ae40..45e5710 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -210,7 +210,7 @@ static void early_ich7_init(void) void main(unsigned long bist) { u32 reg32; - int boot_mode = 0; + int boot_mode = 0, dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; if (bist == 0) @@ -223,15 +223,20 @@ void main(unsigned long bist) ich7_enable_lpc(); + /* We want early GPIO setup, to be able to detect legacy I/O module */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */ + setup_ich7_gpios(); - /* dock_init initializes the DLPC switch on - * thinpad side, so this is required even - * if we're undocked. - */ - if (!dlpc_init() && dock_present()) { + dock_err = dlpc_init(); + + /* We prefer Legacy I/O module over docking */ + if (legacy_io_present()) { + legacy_io_init(); + early_superio_config(); + } else if (!dock_err && dock_present()) { dock_connect(); early_superio_config(); - /* Set up the console */ } #if CONFIG_USBDEBUG @@ -239,6 +244,7 @@ void main(unsigned long bist) early_usbdebug_init(); #endif + /* Setup the console */ console_init(); /* Halt if there was a built in self test failure */

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Patch merged into coreboot/master: 027f405 use byteorder.h instead of implementing another byte swap function
by gerrit＠coreboot.org 15 Oct '11

15 Oct '11

the following patch was just integrated into master: commit 027f405c81ed81698bc089a742a7e05a8b3d7ad4 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:19:21 2011 -0700 use byteorder.h instead of implementing another byte swap function Change-Id: Id5fe7b597256ddf5d4ef408ec82cd94d84e7a0cd Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/277 for details. -gerrit

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coreboot support for laptop HP 635 with AMD E-350 CPU: system data/information (flashrom, lspci, superiotool)
by Paul Menzel 15 Oct '11

15 Oct '11

Dear coreboot and flashrom folks, Carl-Daniel asked me on IRC to relay the following information to you list subscribers. In summary Carl-Daniel is trying to get the HP 635 laptop supported by flashrom and to port coreboot to it. In this message you will find the information/data/specifications [1] Carl-Daniel found out until now attached and the URL of the file in flashrom’s file upload service. The HP 635 is a laptop with a AMD E-350 CPU and costs inclusive shipping 269 € (price comparison: [2]). flashrom runs on the system but does not find a chip [3]. Found chipset "AMD SB700/SB710/SB750/SB850" with PCI ID 1002:439d Super I/O ID 0x8518 is not on the list of flash capable controllers “This means we not only have a really well-supported chipset (AMD RS880M/A50M) the EC in that laptop ITE IT8518 is well-documented as well. I have the IT8512 docs and they are quite extensive. Does anyone have ITE IT8518 docs?” “Ah yes, indeed an ITE EC: The BIOS image contains "EC-V11 Copyright ITE Tech. Inc.. This also means we can ask ITE nicely for distribution rights without worrying about some closed bios vendor having a copyright on that EC image.” Output of `lspci` [4] and of `superiotool` [5] are also available. The forced dump of the BIOS image [6] has a size of 2 MB and probably contains some garbage. The access is restricted to a few though. The executable of the BIOS upgrade file [7, probably different version] can be extracted using `cabextract` [8]. Uwe noted the following. SCH5317 is LPC, so unlikely to be the match, yes. SMSC _does_ have some ECs though IIRC Carl-Daniel will probably not have any Internet access during the next two weeks. But I guess when getting back he would be delighted if he receives some answer from other interested people porting the HP 635 and he could get the documentation of the EC he asked for. I do not know if he starts hacking and for example already works on the flashrom support. Please join the channels #flashrom or #coreboot to get a hold of him and discuss these issues with Carl-Daniel and the rest of the coreboot/flashrom folks. Thanks, Paul PS: Stefan, Uwe, I hope this message is what Carl-Daniel expected. If not please correct my mistakes. [1] http://www.coreboot.org/FAQ#Will_coreboot_work_on_my_machine.3F [2] http://www.heise.de/preisvergleich/638422 [3] http://paste.flashrom.org/view.php?id=851 [4] http://paste.flashrom.org/view.php?id=852 [5] http://paste.flashrom.org/view.php?id=853 [6] http://paste.flashrom.org/view.php?id=854 size: 2097152 bytes md5sum 31147d4d0371fb9bedc7c2cc01eb96ef [7] ftp://ftp.hp.com/pub/softpaq/sp54001-54500/sp54155.exe [8] http://www.cabextract.org.uk/

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Re: [coreboot] How to make "System Restart after Power Fail" working on SB800?
by mopz0506 mopz0506 15 Oct '11

15 Oct '11

Hi, I fetch and read the RRG for SB700, found PMIO_REG74 is PwrFailShadow. for SB800 there is no PwrFailShadow any more, instead AMD give it a new, nonsense name, RtcShadow / RtcShawdow (typo?) and put it to PMIO_REG5B. Sucks. I download SB800 BDG following URL in coreboot Wiki, PN is "45483_sb800_bdg_pub_3.02". I check the SB900 code and there is a function AcLossControl(), which used RtcShadow to control "System Restart after Power Fail". So I guess the BDG v3.02 for SB800 (3.6, P20) is a mistake. Maybe someone copy & paste it from SB700 Guide (in a bugfix , Rev. 1.01, ha ha!) Anyway I change const static AcpiRegWrite sbPmioPorInitTable[] = { ... ... {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2}, ... ... } to 1) {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF0, BIT0 + BIT2}, 2) {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF0, BIT0 + BIT2 + BIT3}, both still does not work and I had to press POWER button. Any idea? Thanks, mopz0506 On Sat, Oct 15, 2011 at 9:57 AM, mopz0506 mopz0506 <mopz0506(a)gmail.com> wrote: > Hi, > > My mainboard is ASRock E350M1, it's sourthbridge is AMD SB800. > > I want the machine to restart once I connect the power cable to > it, without press the POWER button on the front panel. > > The ASRock's EFI BIOS can do this by set "Always Power On" to > "enable". > > At present the coreboot (the cimx module) seems does not touch > "System Restart after Power Fail" feature. > > If I use vendor's EFI BIOS and set "always restart after the > power is restored", then flash the coreboot to it, the box always > restart when power connected and I need not to press the POWER > button. > > If I use vendor's EFI BIOS and set "keep power off after the > power is restored", then flash the coreboot to it, the box does > not up and I must press the POWER button. > > If I clear the BIOS by connect the jumper to (pin1 - pin2), then > all setting lost and I must press the POWER button. > > So seems the coreboot just use the setting (but never set it). > > I think the code is in src\vendorcode\amd\cimx\sb800\SBPOR.c > > const static AcpiRegWrite sbPmioPorInitTable[] = > ...... > {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3}, > ...... > } > > and yes it does not touch the BIT1. > > The BIOS Developer's Guide 3.6, P20, said I must to set > PMIO 74h [bits 1:0] to [01b] to get "always power on" working. > [00] / [10] / [11] does not work as what I hope. > > So I change the line to always clean BIT1 to 0, as BDG required, > > {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF4, BIT0 + BIT3}, > > (just for test, I think the proper way is give a > pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr to overwrite > CIMX's default setting) > > but it has no effect, the box keep off until I press POWER button. > > before this code PMIO 24h [AcpiMMioEn] has been enabled so > MMIO working. > > I checked the SB700 code src\southbridge\amd\sb700\sm.c, to see > how coreboot set "power_on_after_fail" bit in other chipset. > > =================== code start ================= > /* power after power fail */ > > on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; > > get_option(&on, "power_on_after_fail"); > > byte = pm_ioread(0x74); > > byte &= ~0x03; > > if (on) { > byte |= 2; > } > > byte |= 1 << 2; > > pm_iowrite(0x74, byte); > > printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); > =================== code end ================= > > what it did is a litter different and always set bit0 to 0 (CIMX set bit0 > to 1, which is required by the manual): > > 1) clear bit[1:0] to [00b] > 2) set bit[1] to [1b] > 3) set bit[2] to [1b] > > I don't know this code working or not since I do not own a SB700 mainboard. > > If I did it on SB800 as below > > {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xFC, BIT1 + BIT2}, > > coreboot fail to boot. > > SB800 obsolete those coreboot code and replace it with new CIMX code. > > I read the documents about all PM registers, and found nothing. > I search "power" in the whole .pdf, but most of them is difficult to > understand for me. > I search the archive of mail list and seems every mainboard has different > method to set this feature. > > I had tried set it on superio code (Winbond W83267hf), and does not work. > > Also I observe that BIT0 is "Decen_acpi", and BIT1 is "Gbl_en_en", and > they are not "power on after power fail" bit. > > Did I did anything wrong? > > Did these bits need some ACPI code to working? > > When the power cable connected, before I press the POWER button, the > mainboard keeps off due to the setting. in this case, the BIOS code > running or not? > > Any suggesting? > > Thanks for your help in advance, > > mopz0506 >

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Patch merged into coreboot/master: 4876404 AMD CPU and chipset fixes for compilation with gcc 4.6
by gerrit＠coreboot.org 15 Oct '11

15 Oct '11

the following patch was just integrated into master: commit 48764047d8720e3e6f9ae9119f8ae16b9d875cd7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Oct 13 17:04:02 2011 -0700 AMD CPU and chipset fixes for compilation with gcc 4.6 Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/266 for details. -gerrit

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New patch to review for coreboot: 437e073 Added block smbus block operations for amd8111 Fixed bug in one function prototype also: smbus_block_read should pass pointer to block length, not value. Makes no sense to me to pass a value.
by Oskar Enoksson 15 Oct '11

15 Oct '11

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/281 -gerrit commit 437e07301e3239e50f842aa95fcbaf5525f1ae92 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Fri Oct 14 02:16:48 2011 +0200 Added block smbus block operations for amd8111 Fixed bug in one function prototype also: smbus_block_read should pass pointer to block length, not value. Makes no sense to me to pass a value. Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> Change-Id: I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc --- src/devices/smbus_ops.c | 2 +- src/include/device/smbus.h | 4 +- src/southbridge/amd/amd8111/acpi.c | 25 +++++++ src/southbridge/amd/amd8111/amd8111_smbus.h | 98 +++++++++++++++++++++++++++ src/southbridge/amd/amd8111/early_smbus.c | 9 +++ 5 files changed, 135 insertions(+), 3 deletions(-) diff --git a/src/devices/smbus_ops.c b/src/devices/smbus_ops.c index 75ca42b..d0e226f 100644 --- a/src/devices/smbus_ops.c +++ b/src/devices/smbus_ops.c @@ -124,7 +124,7 @@ int smbus_process_call(device_t dev, u8 cmd, u16 data) return ops_smbus_bus(get_pbus_smbus(dev))->process_call(dev, cmd, data); } -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer) +int smbus_block_read(device_t dev, u8 cmd, u8 *bytes, u8 *buffer) { return ops_smbus_bus(get_pbus_smbus(dev))->block_read(dev, cmd, bytes, buffer); diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 073d7e2..bd8f8ce 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -17,7 +17,7 @@ struct smbus_bus_operations { int (*read_word) (device_t dev, u8 addr); int (*write_word) (device_t dev, u8 addr, u16 value); int (*process_call)(device_t dev, u8 cmd, u16 data); - int (*block_read) (device_t dev, u8 cmd, u8 bytes, u8 *buffer); + int (*block_read) (device_t dev, u8 cmd, u8 *bytes, u8 *buffer); int (*block_write) (device_t dev, u8 cmd, u8 bytes, const u8 *buffer); }; @@ -44,7 +44,7 @@ int smbus_write_byte(device_t dev, u8 addr, u8 val); int smbus_read_word(device_t dev, u8 addr); int smbus_write_word(device_t dev, u8 addr, u16 val); int smbus_process_call(device_t dev, u8 cmd, u16 data); -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_read(device_t dev, u8 cmd, u8 *bytes, u8 *buffer); int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer); #endif /* DEVICE_SMBUS_H */ diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 2ad54b7..0c78b91 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -66,6 +66,29 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) return do_smbus_write_byte(res->base, device, address, val); } +static int lsmbus_block_read(device_t dev, uint8_t cmd, u8 *bytes, u8 *buffer) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_block_read(res->base, device, cmd, bytes, buffer); +} + +static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buffer) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_block_write(res->base, device, cmd, bytes, buffer); +} + + #if CONFIG_GENERATE_ACPI_TABLES == 1 unsigned pm_base; #endif @@ -191,6 +214,8 @@ static struct smbus_bus_operations lops_smbus_bus = { .send_byte = lsmbus_send_byte, .read_byte = lsmbus_read_byte, .write_byte = lsmbus_write_byte, + .block_read = lsmbus_block_read, + .block_write= lsmbus_block_write, }; static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index fe9b3bf..f07893d 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -222,3 +222,101 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned return 0; } +static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned cmd, u8 *bytes, u8 *buf) +{ + unsigned global_status_register; + unsigned i; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + /* set the command/address... */ + outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD); + /* set up for a block data read */ + outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL); + + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); + + /* clear the length word...*/ + outw(0, smbus_io_base + SMBHSTDAT); + + /* start the command */ + outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inw(smbus_io_base + SMBGSTATUS); + + /* read results of transaction */ + *bytes = inw(smbus_io_base + SMBHSTDAT) & 0x3f; + + if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { + return SMBUS_ERROR; + } + + /* read data block */ + for(i=0; i<*bytes; i++) { + buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff; + } + + return 0; +} + +static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +{ + unsigned global_status_register; + unsigned i; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + /* set the command/address... */ + outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD); + /* set up for a block data write */ + outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL); + + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); + + /* set the length word...*/ + outw(bytes, smbus_io_base + SMBHSTDAT); + + /* set the data block */ + for(i=0; i<bytes; i++) { + outw(buf[i], smbus_io_base + SMBHSTFIFO); + } + + /* start the command */ + outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + global_status_register = inw(smbus_io_base + SMBGSTATUS); + + if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { + return SMBUS_ERROR; + } + return 0; +} + + diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index e6d7084..9a58a99 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -46,3 +46,12 @@ static inline int smbus_write_byte(unsigned device, unsigned address, unsigned c return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } +static inline int smbus_block_read(unsigned device, unsigned cmd, u8 *bytes, u8 *buf) +{ + return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); +} + +static inline int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +{ + return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); +}

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Patch merged into coreboot/master: 4c00556 use acpi.h include instead of manually adding acpi_slp_type.
by gerrit＠coreboot.org 15 Oct '11

15 Oct '11

the following patch was just integrated into master: commit 4c00556c2f3a2a814c3a484f4ee924c5678037b0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:18:29 2011 -0700 use acpi.h include instead of manually adding acpi_slp_type. Change-Id: I2a3aaf10e453fa6cce8a993356f2a0587178209a Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/276 for details. -gerrit

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Patch merged into coreboot/master: 6a8e422 cbfs_and_run_core() is not part of the API, make it static.
by gerrit＠coreboot.org 15 Oct '11

15 Oct '11

the following patch was just integrated into master: commit 6a8e4225befd6f6a6e035e628cb5e12b2b23bffc Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 14:50:19 2011 -0700 cbfs_and_run_core() is not part of the API, make it static. It's only used in cbfs_and_run.c Change-Id: Ibcfcefbeb0c5722eb3888f0d60127229a2badcf6 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/273 for details. -gerrit

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Patch merged into coreboot/master: 43c4af9 reformat Makefile.bootblock.inc (>80 lines per char)
by gerrit＠coreboot.org 15 Oct '11

15 Oct '11

the following patch was just integrated into master: commit 43c4af942273a396bda883d7f4f92c17f3a9c408 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:09:25 2011 -0700 reformat Makefile.bootblock.inc (>80 lines per char) Change-Id: I0ff02fa72ff5a14d8c166686bb3d66fe1e887ea4 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/274 for details. -gerrit

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Patch set updated for coreboot: 9114cfc Fixes several issues with amd k8 SSDT P-state generation
by Oskar Enoksson 15 Oct '11

15 Oct '11

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/239 -gerrit commit 9114cfc332720cedb487c140913a45cb65b9e5e1 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Thu Oct 6 18:43:43 2011 +0200 Fixes several issues with amd k8 SSDT P-state generation First issue fixed: For multi-socket CPU the current implementation emitted Processor objects for cores in the first CPU only. This commit fixes the bug by really emitting one Processor object for each core. However, the unlikely case of mixed CPU models is still not handled correctly. Second issue fixed: One loop was wrong in case a processor in the table declares no P-states at all. The rewritten loop is safe. Some possibly dangerous array lengths were also fixed. Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV according to the BKDG. The current implementation always set it to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS. Fourth issue: If a processor without PowerNow! support was inserted in a system with coreboot configured with SET_FIDVID then the boot process hanged mysteriously and very early. Apparently because init_fidvid_ap tampers with non-existing registers. This commit fixes the bug by bailing out from init_fidvid_ap if PowerNow! capability is missing. Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417 --- src/cpu/amd/model_fxx/fidvid.c | 6 ++- src/cpu/amd/model_fxx/powernow_acpi.c | 89 +++++++++++++++++++++++++-------- 2 files changed, 73 insertions(+), 22 deletions(-) diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index bbafde6..6395a1e 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -347,13 +347,17 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) u32 fid_max; int loop; + if((cpuid_edx(0x80000007)&0x06)!=0x06) { + return; /* FID/VID change not supported */ + } + msr = rdmsr(0xc0010042); fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */ #if FX_SUPPORT if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */ fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* maxFID = minFID + 1G */ if (fid_max >= ((25 - 4) * 2)) { - fid_max = (10 - 4) * 2; // hard set to 2G + fid_max = (10 - 4) * 2; /* hard set to 2G */ } } #endif diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index bbcf013..83d34f1 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -586,15 +586,27 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) u8 cmp_cap; struct cpuentry *data = NULL; uint32_t control; - int i = 0, index, len = 0, Pstate_num = 0; + int i = 0, index = 0, len = 0, Pstate_num = 0, dev = 0; msr_t msr; - u8 Pstate_fid[10]; - u16 Pstate_feq[10]; - u8 Pstate_vid[10]; - u32 Pstate_power[10]; + u8 Pstate_fid[MAXP+1]; + u16 Pstate_feq[MAXP+1]; + u8 Pstate_vid[MAXP+1]; + u32 Pstate_power[MAXP+1]; u8 Max_fid, Start_fid, Start_vid, Max_vid; - struct cpuid_result cpuid1 = cpuid(0x80000001); + struct cpuid_result cpuid1; + + /* See if the CPUID(0x80000007) returned EDX[2:1]==11b */ + cpuid1 = cpuid(0x80000007); + if((cpuid1.edx & 0x6)!=0x6) { + printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n"); + return 0; + } + cpuid1 = cpuid(0x80000001); + + /* It has been said that we can safely assume that all CPU's + * in the system have the same SYSCONF values + */ msr = rdmsr(0xc0010042); Max_fid = (msr.lo & 0x3F0000) >> 16; Max_vid = (msr.hi & 0x3F0000) >> 16; @@ -620,24 +632,51 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) return 0; } - /* IRT 80us, PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */ - control = (3 << 30) | (2 << 20) | (0 << 18) | (5 << 11) | (1 << 29); +#if CONFIG_MAX_PHYSICAL_CPUS==1 + /* IRT 80us RVO = 50mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */ + control = (3 << 30) | (2 << 28) | (2 << 20) | (0 << 18) | (5 << 11); +#else + /* MP-systems should default to RVO=0mV (no ramp voltage) */ + /* IRT 80us RVO = 0mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */ + + control = (3 << 30) | (0 << 28) | (2 << 20) | (0 << 18) | (5 << 11); +#endif + /* RVO (Ramp Voltage Offset) + * 00 0mV (default for MP-systems) + * 01 25mV + * 10 50mV (default) + * 11 75mV + * IRT (Isochronous Release Time) + * 00 10uS + * 01 20uS + * 10 40uS + * 11 80uS (default) + * MVS (Maximum Voltage Step) + * 00 25mV (default) + * 01 50mV (reserved) + * 10 100mV (reserved) + * 11 200mV (reserved) + * VST (Voltage Stabilization Time) + * time = value*20uS (default value: 5 => 100uS) + * PLL_LOCK_TIME + * time = value*1uS (often seen value: 2uS) + */ + len = 0; - Pstate_num = 0; - Pstate_fid[Pstate_num] = Max_fid; - Pstate_feq[Pstate_num] = fid_to_freq(Max_fid); - Pstate_vid[Pstate_num] = Max_vid; - Pstate_power[Pstate_num] = data->pwr * 100; - Pstate_num++; + Pstate_fid[0] = Max_fid; + Pstate_feq[0] = fid_to_freq(Max_fid); + Pstate_vid[0] = Max_vid; + Pstate_power[0] = data->pwr * 100; - do { + for(Pstate_num = 1; + (Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0); + Pstate_num++) { Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f; Pstate_feq[Pstate_num] = data->pstates[Pstate_num - 1].freqMhz; Pstate_vid[Pstate_num] = vid_to_reg(data->pstates[Pstate_num - 1].voltage); Pstate_power[Pstate_num] = data->pstates[Pstate_num - 1].tdp * 100; - Pstate_num++; - } while ((Pstate_num < MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0)); + } for (i=0;i<Pstate_num;i++) printk(BIOS_DEBUG, "P#%d freq %d [MHz] voltage %d [mV] TDP %d [mW]\n", i, @@ -645,11 +684,19 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) vid_from_reg(Pstate_vid[i]), Pstate_power[i]); - for (index = 0; index < (cmp_cap + 1); index++) { - len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid, - Pstate_fid, Pstate_power, index, - pcontrol_blk, plen, onlyBSP, control); + /* Loop over all CPU's */ + for (dev = 0x18; dev < 0x1c; dev++) { + if(dev_find_slot(0, PCI_DEVFN(dev, 0)) == NULL) + continue; + + for (i = 0; i < (cmp_cap + 1); i++) { + len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid, + Pstate_fid, Pstate_power, index+i, + pcontrol_blk, plen, onlyBSP, control); + } + index += i; } + printk(BIOS_DEBUG,"%d Processor objects emitted to SSDT\n",index); return len; }

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coreboot October 2011