coreboot October 2011

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501 discussions

Patch merged into coreboot/master: 1448012 Re-worked devicetree.cb for DL145 G1
by gerrit＠coreboot.org 17 Oct '11

17 Oct '11

the following patch was just integrated into master: commit 144801207d5b1ad494d7b89b8c7156f8ae7ebd22 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Oct 4 22:34:11 2011 +0200 Re-worked devicetree.cb for DL145 G1 After a lot of experimentation this commit improves some hardware features that were not recognized or incorrectly configured before. The only thing not tested is SCSI-option board (I dont have one). Misleading errors in comments have been corrected. (Note BTW that the DL145 G1 mainboard is identical to AMD Serenade which was supported in early versions of coreboot but was dropped for some reason.) Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e See http://review.coreboot.org/237 for details. -gerrit

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Patch merged into coreboot/master: 9114cfc Fixes several issues with amd k8 SSDT P-state generation
by gerrit＠coreboot.org 17 Oct '11

17 Oct '11

the following patch was just integrated into master: commit 9114cfc332720cedb487c140913a45cb65b9e5e1 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Thu Oct 6 18:43:43 2011 +0200 Fixes several issues with amd k8 SSDT P-state generation First issue fixed: For multi-socket CPU the current implementation emitted Processor objects for cores in the first CPU only. This commit fixes the bug by really emitting one Processor object for each core. However, the unlikely case of mixed CPU models is still not handled correctly. Second issue fixed: One loop was wrong in case a processor in the table declares no P-states at all. The rewritten loop is safe. Some possibly dangerous array lengths were also fixed. Third issue: on MP-boards the recommended ramp-voltage (RVO) is 0mV according to the BKDG. The current implementation always set it to 25mV. This commit selects 0 or 25mV depending on CONFIG_MAX_PHYSICAL_CPUS. Fourth issue: If a processor without PowerNow! support was inserted in a system with coreboot configured with SET_FIDVID then the boot process hanged mysteriously and very early. Apparently because init_fidvid_ap tampers with non-existing registers. This commit fixes the bug by bailing out from init_fidvid_ap if PowerNow! capability is missing. Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> Change-Id: I61f6e2210b84ccba33a36c5efc866447b7134417 See http://review.coreboot.org/239 for details. -gerrit

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Re: [coreboot] How to make "System Restart after Power Fail" working onSB800?
by Patrick Georgi 17 Oct '11

17 Oct '11

Am Mo 17 Okt 2011 03:24:53 CEST schrieb mopz0506 mopz0506: > coreboot is really really too hard for those users who just want > to run a NAS / BT server in his/her living room. That's because the kind of problems that coreboot solves are hard without some knowledge about the inner workings of computers. Not much we can do about it. Of course there are places in coreboot that are more complex/complicated than necessary. It's an ongoing effort to simplify those, and we gladly accept help and patches in that area! Regards, Patrick

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RAMINIT_SYSINFO?
by Oskar Enoksson 17 Oct '11

17 Oct '11

Can someone explain what RAMINIT_SYSINFO configuration option does? I thought I understood, but I don't. /Oskar

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Re: [coreboot] How to make "System Restart after Power Fail" working onSB800?
by mopz0506 mopz0506 17 Oct '11

17 Oct '11

Hi Scott, Yes it works now. Even though ASRock put this "Always Power On" feature under "SouthBridge Configuration" menu item (mislead me very much), it actually controlled by SIO, NUVOTON NCT5572D. I think the E350M1 + coreboot is perfect for me now. so nice to get a login: in 2 seconds. But it is really hard to get this done for a user as me. Several times I almost give up. coreboot is really really too hard for those users who just want to run a NAS / BT server in his/her living room. Many thanks for your help, mopz0506 On Sun, Oct 16, 2011 at 8:40 AM, mopz0506 mopz0506 <mopz0506(a)gmail.com> wrote: > I'll give it a try. > > Thanks, > mopz0506 > > On 10/16/11, Scott Duplichan <scott(a)notabs.org> wrote: >> mopz0506 wrote: >> >> ]Hi, >> ] >> ]My mainboard is ASRock E350M1, it's sourthbridge is AMD SB800. >> ] >> ]I want the machine to restart once I connect the power cable to >> ]it, without press the POWER button on the front panel. >> ]... >> >> I worked on a similar problem a wile back, though I don't >> remember if it was with ASRock E350M1 or something else. >> Anyway, I finally came to the conclusion that my board used >> the SIO for this function, and not the SB800. I think I used the >> OEM BIOS and compared SIO registers with both settings. It might >> be logical device A, CR E4h bits 5 and 6, though I don't have >> the exact datasheet. >> >> Thanks, >> Scott >> >> >

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Re: [coreboot] how to delete symbol link created at compile time
by Stefan Reinauer 16 Oct '11

16 Oct '11

* Marc Jones <marcj303(a)gmail.com> [111014 06:22]: > On Thu, Oct 13, 2011 at 3:19 AM, She, Kerry <Kerry.She(a)amd.com> wrote: > > Hello, > > > > > > > > Some mainboard support more than one family of CPUs with same socket type, > > > > Such as SuperMicro/h8scm: > > > > http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm > > > > > > > > My implementation is the mainboard CPU type can be configured as family10 or > > family15 CPU. > > > > In order to eliminate the duplicated code, both configuration shares most of > > the platform code, > > > > but some code can’t be shared between different family of CPUs. > > > > Take devicetree.cb as an example, > > > > I have created 2 devicetree file : > > > > devicetree_f15.cb for platform with family 15 CPU > > > > devicetree_f10.cb for platform with family 10 CPU > > > > > > > > I changed the makefile to create a symbol link “devicetree.cb” link to > > devicetree_f10.cb or devicetree_f15.cb at compile time. > > > > The problem is that I can’t delete the symbol link when make > > clean/distclean. Please fix the problem by using one device tree for both platforms.

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Re: [coreboot] How to make "System Restart after Power Fail" working onSB800?
by Scott Duplichan 16 Oct '11

16 Oct '11

mopz0506 wrote: ]Hi, ] ]My mainboard is ASRock E350M1, it's sourthbridge is AMD SB800. ] ]I want the machine to restart once I connect the power cable to ]it, without press the POWER button on the front panel. ]... I worked on a similar problem a wile back, though I don't remember if it was with ASRock E350M1 or something else. Anyway, I finally came to the conclusion that my board used the SIO for this function, and not the SB800. I think I used the OEM BIOS and compared SIO registers with both settings. It might be logical device A, CR E4h bits 5 and 6, though I don't have the exact datasheet. Thanks, Scott

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Patch merged into coreboot/master: a05c290 SMM: Move wbinvd after pmode jump
by gerrit＠coreboot.org 15 Oct '11

15 Oct '11

the following patch was just integrated into master: commit a05c29057681e69485387f2846b44af503f82534 Author: Stefan Reinauer <reinauer(a)google.com> Date: Sat Oct 15 11:23:04 2011 -0700 SMM: Move wbinvd after pmode jump According to Rudolf Marek putting a memory instruction between the CR0 write and the jmp in protected mode switching might hang the machine. Move it after the jmp. There might be a better solution for this, such as enabling the cache, as keeping it disabled does not prevent cache poisoning attacks, so there is no real point. However, Intel docs say that SMM code in ASEG is always running uncached, so we might want to consider running SMM out of TSEG instead, as well. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: Id396acf3c8a79a9f1abcc557af6e0cce099955ec See http://review.coreboot.org/283 for details. -gerrit

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Patch set updated for coreboot: f7195d2 Add macros for 64bit byte order swapping
by Stefan Reinauer 15 Oct '11

15 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/275 -gerrit commit f7195d2b65fb571ab7e3a9950bf8eaef878c411a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:11:16 2011 -0700 Add macros for 64bit byte order swapping Change-Id: Ic31ccd41ba3e0af7046eafc29221810d4cd196c8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/byteorder.h | 13 +++++++++---- src/include/swab.h | 11 +++++++++++ 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/include/arch/byteorder.h b/src/arch/x86/include/arch/byteorder.h index ab344e6..1184ed2 100644 --- a/src/arch/x86/include/arch/byteorder.h +++ b/src/arch/x86/include/arch/byteorder.h @@ -3,12 +3,17 @@ #define __LITTLE_ENDIAN 1234 +#include <stdint.h> #include <swab.h> -#define cpu_to_le32(x) ((unsigned int)(x)) -#define le32_to_cpu(x) ((unsigned int)(x)) -#define cpu_to_le16(x) ((unsigned short)(x)) -#define le16_to_cpu(x) ((unsigned short)(x)) +#define cpu_to_le64(x) ((uint64_t)(x)) +#define le64_to_cpu(x) ((uint64_t)(x)) +#define cpu_to_le32(x) ((uint32_t)(x)) +#define le32_to_cpu(x) ((uint32_t)(x)) +#define cpu_to_le16(x) ((uint16_t)(x)) +#define le16_to_cpu(x) ((uint16_t)(x)) +#define cpu_to_be64(x) swab64(x) +#define be64_to_cpu(x) swab64(x) #define cpu_to_be32(x) swab32((x)) #define be32_to_cpu(x) swab32((x)) #define cpu_to_be16(x) swab16((x)) diff --git a/src/include/swab.h b/src/include/swab.h index 3a16686..c5e4370 100644 --- a/src/include/swab.h +++ b/src/include/swab.h @@ -30,4 +30,15 @@ (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \ (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) )) +#define swab64(x) \ + ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56) )) + #endif /* _SWAB_H */

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New patch to review for coreboot: a05c290 SMM: Move wbinvd after pmode jump
by Stefan Reinauer 15 Oct '11

15 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/283 -gerrit commit a05c29057681e69485387f2846b44af503f82534 Author: Stefan Reinauer <reinauer(a)google.com> Date: Sat Oct 15 11:23:04 2011 -0700 SMM: Move wbinvd after pmode jump According to Rudolf Marek putting a memory instruction between the CR0 write and the jmp in protected mode switching might hang the machine. Move it after the jmp. There might be a better solution for this, such as enabling the cache, as keeping it disabled does not prevent cache poisoning attacks, so there is no real point. However, Intel docs say that SMM code in ASEG is always running uncached, so we might want to consider running SMM out of TSEG instead, as well. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: Id396acf3c8a79a9f1abcc557af6e0cce099955ec --- src/cpu/x86/smm/smmhandler.S | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 450aa53..774088e 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -83,13 +83,15 @@ smm_handler_start: andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 - wbinvd /* Enable protected mode */ data32 ljmp $0x08, $1f .code32 1: + /* flush the cache after disabling it */ + wbinvd + /* Use flat data segment */ movw $0x10, %ax movw %ax, %ds

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coreboot October 2011