coreboot October 2011

coreboot@coreboot.org

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501 discussions

Patch set updated for coreboot: f8d44a0 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
by Sven Schnelle 17 Oct '11

17 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/282 -gerrit commit f8d44a08ac615fdc2ea680c187bb556e330663cc Author: Sven Schnelle <svens(a)stackframe.org> Date: Sat Oct 15 17:31:01 2011 +0200 T60: Add support for Ultrabay Legacy I/O devices (40Y8122) Those modules have basically the same Super I/O capabilities as the Docking station. Unfortunately, the Super I/O in the module shares the same I/O address as the Docking station, so we're not allowed to connect the LPC Docking Bus if such a module is present. To be able to detect this device and use it as early console for coreboot, we have to initialize the GPIO Controller before, as this device is detected via GPIO06. Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/mainboard/lenovo/t60/dock.c | 49 +++++++++++++++++++++++------ src/mainboard/lenovo/t60/dock.h | 3 ++ src/mainboard/lenovo/t60/mainboard.c | 11 +++++- src/mainboard/lenovo/t60/mainboard_smi.c | 8 ++++- src/mainboard/lenovo/t60/romstage.c | 21 ++++++++---- 5 files changed, 72 insertions(+), 20 deletions(-) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 6642bb3..b37c2bf 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -28,8 +28,11 @@ #include "dock.h" #include "superio/nsc/pc87384/pc87384.h" #include "ec/acpi/ec.h" +#include "ec/lenovo/pmh7/pmh7.h" #include "southbridge/intel/i82801gx/i82801gx.h" +#define DLPC_CONTROL 0x164c + static void dlpc_write_register(int reg, int value) { outb(reg, 0x164e); @@ -102,12 +105,15 @@ int dlpc_init(void) /* Select DLPC module */ dlpc_write_register(0x07, 0x19); - /* DLPC Base Address 0x164c */ - dlpc_write_register(0x60, 0x16); - dlpc_write_register(0x61, 0x4c); + /* DLPC Base Address */ + dlpc_write_register(0x60, (DLPC_CONTROL >> 8) & 0xff); + dlpc_write_register(0x61, DLPC_CONTROL & 0xff); /* Activate DLPC */ dlpc_write_register(0x30, 0x01); + /* Reset docking state */ + outb(0x00, DLPC_CONTROL); + dlpc_gpio_init(); return 0; } @@ -127,7 +133,7 @@ static int dock_superio_init(void) /* set GPIO pins to Serial/Parallel Port * functions */ - dock_write_register(0x22, 0xeb); + dock_write_register(0x22, 0xa9); dock_write_register(0x07, PC87384_GPIO); dock_write_register(0x60, 0x16); @@ -179,16 +185,16 @@ int dock_connect(void) { int timeout = 1000; - outb(0x07, 0x164c); + outb(0x07, DLPC_CONTROL); timeout = 1000; - while(!(inb(0x164c) & 8) && timeout--) + while(!(inb(DLPC_CONTROL) & 8) && timeout--) udelay(1000); if (!timeout) { /* docking failed, disable DLPC switch */ - outb(0x00, 0x164c); + outb(0x00, DLPC_CONTROL); dlpc_write_register(0x30, 0x00); return 1; } @@ -206,14 +212,37 @@ int dock_connect(void) void dock_disconnect(void) { /* disconnect LPC bus */ - outb(0x00, 0x164c); + outb(0x00, DLPC_CONTROL); /* Assert PLTRST and DLPCPD */ outb(0xfc, 0x1680); } +static void pmh7_write(int reg, u8 val) +{ + outb(reg, EC_LENOVO_PMH7_ADDR); + outb(val, EC_LENOVO_PMH7_DATA); +} + +static u8 pmh7_read(int reg) +{ + outb(reg, EC_LENOVO_PMH7_ADDR); + return inb(EC_LENOVO_PMH7_DATA); +} + int dock_present(void) { - outb(0x61, 0x15ec); - return inb(0x15ee) & 1; + return pmh7_read(0x61) & 1; } +int legacy_io_present(void) +{ + return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40); +} + +void legacy_io_init(void) +{ + /* Enable Power for Ultrabay slot */ + pmh7_write(0x62, pmh7_read(0x62) & ~0x01); + udelay(100000); + dock_superio_init(); +} diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h index 9d35d9f..631f007 100644 --- a/src/mainboard/lenovo/t60/dock.h +++ b/src/mainboard/lenovo/t60/dock.h @@ -24,4 +24,7 @@ extern int dock_connect(void); extern void dock_disconnect(void); extern int dock_present(void); extern int dlpc_init(void); + +extern int legacy_io_present(void); +extern void legacy_io_init(void); #endif diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 2b8c5fe..8456992 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -38,6 +38,7 @@ static void mainboard_enable(device_t dev) { + struct southbridge_intel_i82801gx_config *config; device_t dev0, idedev; u8 defaults_loaded = 0; @@ -50,8 +51,14 @@ static void mainboard_enable(device_t dev) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); - if (idedev && idedev->chip_info && h8_ultrabay_device_present()) { - struct southbridge_intel_i82801gx_config *config = idedev->chip_info; + + if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) { + /* legacy I/O connected */ + pmh7_ultrabay_power_enable(1); + ec_write(0x0c, 0x84); + } else if (idedev && idedev->chip_info && + h8_ultrabay_device_present()) { + config = idedev->chip_info; config->ide_enable_primary = 1; pmh7_ultrabay_power_enable(1); ec_write(0x0c, 0x84); diff --git a/src/mainboard/lenovo/t60/mainboard_smi.c b/src/mainboard/lenovo/t60/mainboard_smi.c index 4a0b506..eb28256 100644 --- a/src/mainboard/lenovo/t60/mainboard_smi.c +++ b/src/mainboard/lenovo/t60/mainboard_smi.c @@ -75,7 +75,13 @@ int mainboard_io_trap_handler(int smif) switch (smif) { case SMI_DOCK_CONNECT: - dlpc_init(); + /* If there's an legacy I/O module present, we're not + * allowed to connect the Docking LPC Bus, as both Super I/O + * chips are using 0x2e as base address. + */ + if (legacy_io_present()) + break; + if (!dock_connect()) { /* set dock LED to indicate status */ ec_write(0x0c, 0x08); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 252ae40..7ed7768 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -210,7 +210,7 @@ static void early_ich7_init(void) void main(unsigned long bist) { u32 reg32; - int boot_mode = 0; + int boot_mode = 0, dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; if (bist == 0) @@ -223,15 +223,21 @@ void main(unsigned long bist) ich7_enable_lpc(); + /* We want early GPIO setup, to be able to detect legacy I/O module */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + /* Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + setup_ich7_gpios(); - /* dock_init initializes the DLPC switch on - * thinpad side, so this is required even - * if we're undocked. - */ - if (!dlpc_init() && dock_present()) { + dock_err = dlpc_init(); + + /* We prefer Legacy I/O module over docking */ + if (legacy_io_present()) { + legacy_io_init(); + early_superio_config(); + } else if (!dock_err && dock_present()) { dock_connect(); early_superio_config(); - /* Set up the console */ } #if CONFIG_USBDEBUG @@ -239,6 +245,7 @@ void main(unsigned long bist) early_usbdebug_init(); #endif + /* Setup the console */ console_init(); /* Halt if there was a built in self test failure */

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Patch set updated for coreboot: d2708a3 Add macros for 64bit byte order swapping
by Stefan Reinauer 17 Oct '11

17 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/275 -gerrit commit d2708a3116aebba4345189ba5eb94600b7c00720 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:11:16 2011 -0700 Add macros for 64bit byte order swapping Change-Id: Ic31ccd41ba3e0af7046eafc29221810d4cd196c8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/x86/include/arch/byteorder.h | 19 +++++++++++++------ src/include/swab.h | 11 +++++++++++ 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/include/arch/byteorder.h b/src/arch/x86/include/arch/byteorder.h index ab344e6..8dc069f 100644 --- a/src/arch/x86/include/arch/byteorder.h +++ b/src/arch/x86/include/arch/byteorder.h @@ -3,18 +3,25 @@ #define __LITTLE_ENDIAN 1234 +#include <stdint.h> #include <swab.h> -#define cpu_to_le32(x) ((unsigned int)(x)) -#define le32_to_cpu(x) ((unsigned int)(x)) -#define cpu_to_le16(x) ((unsigned short)(x)) -#define le16_to_cpu(x) ((unsigned short)(x)) +#define cpu_to_le64(x) ((uint64_t)(x)) +#define le64_to_cpu(x) ((uint64_t)(x)) +#define cpu_to_le32(x) ((uint32_t)(x)) +#define le32_to_cpu(x) ((uint32_t)(x)) +#define cpu_to_le16(x) ((uint16_t)(x)) +#define le16_to_cpu(x) ((uint16_t)(x)) +#define cpu_to_be64(x) swab64(x) +#define be64_to_cpu(x) swab64(x) #define cpu_to_be32(x) swab32((x)) #define be32_to_cpu(x) swab32((x)) #define cpu_to_be16(x) swab16((x)) #define be16_to_cpu(x) swab16((x)) -#define ntohl(x) be32_to_cpu(x) -#define htonl(x) cpu_to_be32(x) +#define ntohll(x) be64_to_cpu(x) +#define htonll(x) cpu_to_be64(x) +#define ntohl(x) be32_to_cpu(x) +#define htonl(x) cpu_to_be32(x) #endif /* _BYTEORDER_H */ diff --git a/src/include/swab.h b/src/include/swab.h index 3a16686..c5e4370 100644 --- a/src/include/swab.h +++ b/src/include/swab.h @@ -30,4 +30,15 @@ (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \ (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) )) +#define swab64(x) \ + ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56) )) + #endif /* _SWAB_H */

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New patch to review for coreboot: 699632f Use ntohll where appropriate.
by Stefan Reinauer 17 Oct '11

17 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/288 -gerrit commit 699632f2925fdcb16d4dcdaed99728e29588e083 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Oct 17 09:51:15 2011 -0700 Use ntohll where appropriate. also clean out a local copy of ntohl in yabel. Change-Id: Iffe85a53c9ea25abeb3ac663870eb7eb4874a704 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/boot/selfboot.c | 16 +++++++++------- src/devices/oprom/yabel/vbe.c | 1 - src/lib/cbfs.c | 4 ++-- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c index 7ae9f8c..cdb1fa1 100644 --- a/src/boot/selfboot.c +++ b/src/boot/selfboot.c @@ -349,11 +349,12 @@ static int build_self_segment_list( segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", ntohl(segment->compression)); new = malloc(sizeof(*new)); - new->s_dstaddr = ntohl((u32) segment->load_addr); + new->s_dstaddr = ntohll(segment->load_addr); new->s_memsz = ntohl(segment->mem_len); new->compression = ntohl(segment->compression); - new->s_srcaddr = (u32) ((unsigned char *) first_segment) + ntohl(segment->offset); + new->s_srcaddr = (u32) ((unsigned char *)first_segment) + + ntohl(segment->offset); new->s_filesz = ntohl(segment->len); printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); @@ -366,17 +367,18 @@ static int build_self_segment_list( break; case PAYLOAD_SEGMENT_BSS: - printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) ntohl((u32) segment->load_addr), - ntohl(segment->mem_len)); + printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) + (intptr_t)ntohll(segment->load_addr), + ntohl(segment->mem_len)); new = malloc(sizeof(*new)); new->s_filesz = 0; - new->s_dstaddr = ntohl((u32) segment->load_addr); + new->s_dstaddr = ntohll(segment->load_addr); new->s_memsz = ntohl(segment->mem_len); break; case PAYLOAD_SEGMENT_ENTRY: printk(BIOS_DEBUG, " Entry Point 0x%p\n", (void *) ntohl((u32) segment->load_addr)); - *entry = ntohl((u32) segment->load_addr); + *entry = ntohll(segment->load_addr); /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurence of the * entry point as break condition for the loop. @@ -396,7 +398,7 @@ static int build_self_segment_list( // FIXME: Explain what this is for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (new->s_srcaddr < ntohl((u32) segment->load_addr)) + if (new->s_srcaddr < ntohll(segment->load_addr)) break; } diff --git a/src/devices/oprom/yabel/vbe.c b/src/devices/oprom/yabel/vbe.c index b1d6984..a9cee30 100644 --- a/src/devices/oprom/yabel/vbe.c +++ b/src/devices/oprom/yabel/vbe.c @@ -18,7 +18,6 @@ #endif #include <arch/byteorder.h> -#define ntohl(x) be32_to_cpu(x) #include "debug.h" diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 20c9d49..33fa799 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -116,7 +116,7 @@ void * cbfs_load_stage(const char *name) printk(BIOS_DEBUG, "Stage: done loading.\n"); entry = stage->entry; - // entry = ntohl((u32) stage->entry); + // entry = ntohll(stage->entry); return (void *) entry; } @@ -137,7 +137,7 @@ int cbfs_execute_stage(const char *name) /* FIXME: This isn't right */ printk(BIOS_INFO, "CBFS: run @ %p\n", (void *) ntohl((u32) stage->entry)); - return run_address((void *) ntohl((u32) stage->entry)); + return run_address((void *) (intptr_t)ntohll(stage->entry)); } /**

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Re: [coreboot] Getting serial output from w83627hf?
by Peter Stuge 17 Oct '11

17 Oct '11

QingPei Wang wrote: > the superio part should placed under the LCP bridge. > for your mainboard, > it should under > " device pci 1f.0 on end # LPC bridge > " The "end" on this line goes after the newly introduced chip block. > add the superio things like: > " > device pci 1f.0 on end # LPC bridge So the above line should be: device pci 1f.0 on # LPC bridge Followed by the newly added chip block: > chip superio/winbond/w83627hf > device pnp 2e.0 on # Floppy > io 0x60 = 0x3f0 > irq 0x70 = 6 > drq 0x74 = 2 > end And finally the end for the 1f.0 pci device: end //Peter

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Re: [coreboot] Getting serial output from w83627hf?
by Idwer Vollering 17 Oct '11

17 Oct '11

Comments inline: 2011/10/17 Idwer Vollering <vidwer(a)gmail.com> > > > 2011/10/17 Alp Eren Köse <alperenkose(a)buyutech.com.tr> > >> Hi all, >> >> I can't get serial output from the board I am trying to put coreboot on, >> so I am not able to go any further to see whats going on.. >> > >> The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e. >> > > It is likely that you need to set the serial port's speed in romstage.c: > > // omitting includes, license header > #include "superio/winbond/w83627hf/early_serial.c" > #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) > > Add this line to main(): > w83627hf_set_clksel_48(SERIAL_DEV); > The bit that controls the clock speed is in CR24. > > >> >> I couldn't figure out where to put the "chip superio/winbond/w83627hf" >> section in the "devicetree.cb" file layout? >> > > SCH boards don't use the serial port but the EHCI debug port to show output > on? See src/mainboard/iwave/iWRainbowG6/devicetree.cb, it doesn't have the > superio included. > > What I would do is put it inside the LPC bridge section, note that I don't > know how the superio is actually attached and therefore could be wrong. > So: > chip southbridge/intel/i82801ex > Replace i82801ex with sch, ofcourse. > device pci 1f.0 on # lpc bridge > chip superio/winbond/w83627hf > end # superio > end # 1f.0 > > > >> Could someone please explain the devicetree.cb file structure? or point a >> way? >> >> The "lspci -tvnn" output and my modified "devicetree.cb" file are at the >> attachment. >> > Can you show the output from "superiotool -deV" too? Thanks. >> Thanks in advance, >> Alp >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > >

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New patch to review for coreboot: d59cb75 nvramtool: Fix CMOS checksum to match coreboot (and /dev/nvram)
by Stefan Reinauer 17 Oct '11

17 Oct '11

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/287 -gerrit commit d59cb7508b77d9f8cc9ed75320c74842674224a0 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Oct 17 08:58:27 2011 -0700 nvramtool: Fix CMOS checksum to match coreboot (and /dev/nvram) Change-Id: I28b0dbad36403a31be83581107f40b3ca1332dcc Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- util/nvramtool/cmos_ops.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/nvramtool/cmos_ops.c b/util/nvramtool/cmos_ops.c index 2bbc8a1..91c9f45 100644 --- a/util/nvramtool/cmos_ops.c +++ b/util/nvramtool/cmos_ops.c @@ -210,7 +210,7 @@ uint16_t cmos_checksum_compute(void) for (i = cmos_checksum_start; i <= cmos_checksum_end; i++) sum += cmos_read_byte(i); - return ~((uint16_t) (sum & 0xffff)); + return (uint16_t)(sum & 0xffff); } /****************************************************************************

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Patch merged into coreboot/master: 7ae18c2 Fix our CMOS checksum algorithm so it matches what /dev/nvram expects
by gerrit＠coreboot.org 17 Oct '11

17 Oct '11

the following patch was just integrated into master: commit 7ae18c212c2ccca0c7f4691db0bfb5c89d8ce0ac Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:24:03 2011 -0700 Fix our CMOS checksum algorithm so it matches what /dev/nvram expects Our cmos checksum is inverted to what the Linux /dev/nvram device expects (and BIOSes use). This makes it impossible to use /dev/nvram with coreboot. Fix it! Change-Id: I239f7e3aca05d3691aee16490dd801df2ccaefd1 Signed-off-by: Vadim Bendebury <vbendeb(a)google.com> Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/279 for details. -gerrit

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Patch merged into coreboot/master: 30cb6c7 rework RTC driver output to make it more consistent.
by gerrit＠coreboot.org 17 Oct '11

17 Oct '11

the following patch was just integrated into master: commit 30cb6c723bce9cac3c8e5af1b1458352d7e68002 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:22:52 2011 -0700 rework RTC driver output to make it more consistent. Also add a meaningful define (Not hooked up in Kconfig, that might or might not follow) Change-Id: I9cc4bca0d23d75e6a1d767932ec62e8c68b39d71 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/278 for details. -gerrit

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Patch merged into coreboot/master: b11deb8 cbfstool: improve error messages
by gerrit＠coreboot.org 17 Oct '11

17 Oct '11

the following patch was just integrated into master: commit b11deb89f181728f75071778f22580408e74c3fd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 12:44:14 2011 -0700 cbfstool: improve error messages If a file can't be added by cbfstool, print the type and name of the file in the error message. Change-Id: I369d6f5be09ec53ee5beea2cfea65a80407f0ba3 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/271 for details. -gerrit

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Re: [coreboot] Getting serial output from w83627hf?
by QingPei Wang 17 Oct '11

17 Oct '11

the superio part should placed under the LCP bridge. for your mainboard, it should under " device pci 1f.0 on end # LPC bridge " add the superio things like: " device pci 1f.0 on end # LPC bridge chip superio/winbond/w83627hf device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end " Best wishes QingPei Wang Phone: 86+018930528086 2011/10/17 Alp Eren Köse <alperenkose(a)buyutech.com.tr> > Hi all, > > I can't get serial output from the board I am trying to put coreboot on, so > I am not able to go any further to see whats going on.. > > The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e. > > I couldn't figure out where to put the "chip superio/winbond/w83627hf" > section in the "devicetree.cb" file layout? > Could someone please explain the devicetree.cb file structure? or point a > way? > > The "lspci -tvnn" output and my modified "devicetree.cb" file are at the > attachment. > > Thanks in advance, > Alp > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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coreboot October 2011