coreboot October 2011

coreboot@coreboot.org

46 participants
501 discussions

New patch to review for coreboot: 210dced I945: replace #ifdef defined by #if
by Sven Schnelle 18 Oct '11

18 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/293 -gerrit commit 210dcedf6e7afd2d46976a21adcfce92747789fe Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Oct 18 07:58:10 2011 +0200 I945: replace #ifdef defined by #if config.h defines also unset config options (as "0") so #ifdef matches both settings, which isn't what we want. Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i945/early_init.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 197c58f..14c66c4 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -91,7 +91,7 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#if CONFIG_NORTHBRIDGE_INTEL_I945GC printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif } @@ -140,7 +140,7 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif }

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Re: [coreboot] how to delete symbol link created at compile time
by Stefan Reinauer 18 Oct '11

18 Oct '11

* Marc Jones <marcj303(a)gmail.com> [111016 10:10]: > >> > I have created 2 devicetree file : > >> > > >> > devicetree_f15.cb for platform with family 15 CPU > >> > > >> > devicetree_f10.cb for platform with family 10 CPU > >> > > >> > > >> > > >> > I changed the makefile to create a symbol link “devicetree.cb” link to > >> > devicetree_f10.cb or devicetree_f15.cb at compile time. > >> > > >> > The problem is that I can’t delete the symbol link when make > >> > clean/distclean. > > > > Please fix the problem by using one device tree for both platforms. > Stefan, > > Can you explain your thoughts on how that would work? Can we put a #if > in the devicetree.cb? It uses the c precompiler? It requires different > CPU files/device locations. We can try it next week. Usually the way this is handled in coreboot is that there is one socket that binds together all CPU types. Then in the device tree only the socket type is specified, and code for both CPUs is pulled in. Maybe we need something like a socket for northbridge code, since the northbridge now lives in the CPU? It seems like a bad idea to have to recompile your BIOS because you change the CPU. We did a lot of nastyness with K8 and Fam10, but we should find a better way to do this for future chipsets/CPUs. Stefan

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Re: [coreboot] RAMINIT_SYSINFO?
by Oskar Enoksson 18 Oct '11

18 Oct '11

On 10/17/2011 04:24 AM, Marc Jones wrote: > On Sun, Oct 16, 2011 at 4:57 AM, Oskar Enoksson<enok(a)lysator.liu.se> wrote: >> Can someone explain what RAMINIT_SYSINFO configuration option does? I >> thought I understood, but I don't. >> >> /Oskar > Hi Oskar, > > RAMINIT_SYSINFO is the config option to create the AMD sysinfo > structure in CAR above the stack. This is a way to get global data in > the romstage (heap like without any management). The space for the > data structure is allocated by the DCACHE_RAM_GLOBAL_VAR_SIZE config > and the pointer is setup in cache_as_ram_main. So setting RAMINIT_SYSINFO enables some functionality that needs that data in the romstage, e.g. optimize_link_incoherent_ht (?) But what would be the reason to NOT use RAMINIT_SYSINFO? To save space in the cache?

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Re: [coreboot] How to make "System Restart after Power Fail" working onSB800?
by Peter Stuge 18 Oct '11

18 Oct '11

mopz0506 mopz0506 wrote: > Yes it works now. > > Even though ASRock put this "Always Power On" feature under > "SouthBridge Configuration" menu item (mislead me very much), > it actually controlled by SIO, NUVOTON NCT5572D. > > I think the E350M1 + coreboot is perfect for me now. so nice to > get a login: in 2 seconds. Please send the patch with your changes. Start with reading http://www.coreboot.org/Git and then ask if you have any questions. //Peter

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Patch merged into coreboot/master: 598a282 Append logical PME/GPIO device. Fix MPU device number.
by gerrit＠coreboot.org 18 Oct '11

18 Oct '11

the following patch was just integrated into master: commit 598a28212e55d056e01381c017b74ef5846da3b6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 16 18:12:59 2011 +0300 Append logical PME/GPIO device. Fix MPU device number. A mainboard may require configuration of the superio pins to fully support some features. Things like A20# gate, leds, fans, infra-red and bootstrap jumpers may be configured and controlled through the logical PME device. Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/289 for details. -gerrit

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Patch merged into coreboot/master: 05e1992 Activate older Xeon P4 microcodes
by gerrit＠coreboot.org 18 Oct '11

18 Oct '11

the following patch was just integrated into master: commit 05e19920831426c5667a1fa3e856034743b1e783 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Oct 17 17:10:03 2011 +0300 Activate older Xeon P4 microcodes As new microcode files were included, the table was not updated with families 0f25 and 0f26. Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/290 for details. -gerrit

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New patch to review for coreboot: 3ef8ba2 i82801dx: Replace romstage printk's
by Kyösti Mälkki 17 Oct '11

17 Oct '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/291 -gerrit commit 3ef8ba2d4d623e812fe8849914ebab2be22c697a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Oct 17 17:37:45 2011 +0300 i82801dx: Replace romstage printk's Patch is required to compile this with romcc. Change-Id: I5c4c0f5b32e5edeb8c48d8455b3493ca79f8b452 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801dx/early_smbus.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index f58cd86..00eaee0 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -41,7 +41,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - printk(BIOS_DEBUG, "SMBus controller enabled\n"); + print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ @@ -117,9 +117,9 @@ static int smbus_read_byte(unsigned device, unsigned address) unsigned char global_status_register; unsigned char byte; - /* printk(BIOS_ERR, "smbus_read_byte\n"); */ + /* print_err("smbus_read_byte\n"); */ if (smbus_wait_until_ready() < 0) { - printk(BIOS_ERR, "SMBUS not ready (%02x)\n", -2); + print_err("SMBUS not ready (-2)\n"); return -2; } @@ -145,13 +145,13 @@ static int smbus_read_byte(unsigned device, unsigned address) SMBUS_IO_BASE + SMBHSTCTL); /* poll for it to start */ if (smbus_wait_until_active() < 0) { - printk(BIOS_ERR, "SMBUS not active (%02x)\n", -4); + print_err("SMBUS not active (-4)\n"); return -4; } /* poll for transaction completion */ if (smbus_wait_until_done() < 0) { - printk(BIOS_ERR, "SMBUS not completed (%02x)\n", -3); + print_err("SMBUS not completed (-3)\n"); return -3; } @@ -161,10 +161,10 @@ static int smbus_read_byte(unsigned device, unsigned address) byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); if (global_status_register != 2) { - //printk(BIOS_SPEW, "%s: no device (%02x, %02x)\n", __func__, device, address); + //print_spew("%s: no device (%02x, %02x)\n", __func__, device, address); return -1; } - //printk(BIOS_DEBUG, "%s: %02x@%02x = %02x\n", __func__, device, address, byte); + //print_debug("%s: %02x@%02x = %02x\n", __func__, device, address, byte); return byte; }

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New patch to review for coreboot: 05e1992 Activate older Xeon P4 microcodes
by Kyösti Mälkki 17 Oct '11

17 Oct '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/290 -gerrit commit 05e19920831426c5667a1fa3e856034743b1e783 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Oct 17 17:10:03 2011 +0300 Activate older Xeon P4 microcodes As new microcode files were included, the table was not updated with families 0f25 and 0f26. Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_f2x/model_f2x_init.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index f7e5f27..c1c2b7c 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -68,9 +68,10 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x0f22 }, { X86_VENDOR_INTEL, 0x0f24 }, + { X86_VENDOR_INTEL, 0x0f25 }, + { X86_VENDOR_INTEL, 0x0f26 }, { X86_VENDOR_INTEL, 0x0f27 }, { X86_VENDOR_INTEL, 0x0f29 }, -// { X86_VENDOR_INTEL, 0x0f25 }, /* I don't have a microcode update for this cpu */ { 0, 0 }, };

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New patch to review for coreboot: 598a282 Append logical PME/GPIO device. Fix MPU device number.
by Kyösti Mälkki 17 Oct '11

17 Oct '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/289 -gerrit commit 598a28212e55d056e01381c017b74ef5846da3b6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 16 18:12:59 2011 +0300 Append logical PME/GPIO device. Fix MPU device number. A mainboard may require configuration of the superio pins to fully support some features. Things like A20# gate, leds, fans, infra-red and bootstrap jumpers may be configured and controlled through the logical PME device. Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/superio/smsc/lpc47m10x/lpc47m10x.h | 2 +- src/superio/smsc/lpc47m10x/superio.c | 1 + 2 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h index 4c78d9e..535a414 100644 --- a/src/superio/smsc/lpc47m10x/lpc47m10x.h +++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h @@ -30,7 +30,7 @@ #define LPC47M10X2_KBC 7 /* Keyboard & Mouse */ #define LPC47M10X2_GAME 9 /* GAME */ #define LPC47M10X2_PME 10 /* PME reg*/ -#define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/ // FIXME +#define LPC47M10X2_MPU 11 /* MPU-401 MIDI */ #define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index 0be8742..3d6a8ed 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -65,6 +65,7 @@ static struct pnp_info pnp_dev_info[] = { { &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, LPC47M10X2_PME, PNP_IO0, { 0x0f80, 0 }, }, }; /**

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Patch set updated for coreboot: 96a5f64 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
by Sven Schnelle 17 Oct '11

17 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/282 -gerrit commit 96a5f648daea651fe427e66c62b31373a3688b38 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sat Oct 15 17:31:01 2011 +0200 T60: Add support for Ultrabay Legacy I/O devices (40Y8122) Those modules have basically the same Super I/O capabilities as the Docking station. Unfortunately, the Super I/O in the module shares the same I/O address as the Docking station, so we're not allowed to connect the LPC Docking Bus if such a module is present. To be able to detect this device and use it as early console for coreboot, we have to initialize the GPIO Controller before, as this device is detected via GPIO06. Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/ec/lenovo/pmh7/pmh7.c | 4 +++ src/mainboard/lenovo/t60/Makefile.inc | 4 +- src/mainboard/lenovo/t60/dock.c | 37 +++++++++++++++++++++-------- src/mainboard/lenovo/t60/dock.h | 3 ++ src/mainboard/lenovo/t60/mainboard.c | 11 +++++++- src/mainboard/lenovo/t60/mainboard_smi.c | 8 +++++- src/mainboard/lenovo/t60/romstage.c | 21 +++++++++++----- 7 files changed, 66 insertions(+), 22 deletions(-) diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 30460c9..844e233 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -91,6 +91,8 @@ void pmh7_register_write(int reg, int val) outb(val, EC_LENOVO_PMH7_DATA); } +#ifndef __PRE_RAM__ +#ifndef __SMM__ static void enable_dev(device_t dev) { struct ec_lenovo_pmh7_config *conf = dev->chip_info; @@ -115,3 +117,5 @@ struct chip_operations ec_lenovo_pmh7_ops = { CHIP_NAME("Lenovo Power Management Hardware Hub 7") .enable_dev = enable_dev, }; +#endif +#endif diff --git a/src/mainboard/lenovo/t60/Makefile.inc b/src/mainboard/lenovo/t60/Makefile.inc index 7515258..f86afd1 100644 --- a/src/mainboard/lenovo/t60/Makefile.inc +++ b/src/mainboard/lenovo/t60/Makefile.inc @@ -17,5 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c dock.c -romstage-y += dock.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c dock.c ../../../ec/lenovo/pmh7/pmh7.c +romstage-y += dock.c ../../../ec/lenovo/pmh7/pmh7.c diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 6642bb3..5cd8997 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -28,8 +28,11 @@ #include "dock.h" #include "superio/nsc/pc87384/pc87384.h" #include "ec/acpi/ec.h" +#include "ec/lenovo/pmh7/pmh7.h" #include "southbridge/intel/i82801gx/i82801gx.h" +#define DLPC_CONTROL 0x164c + static void dlpc_write_register(int reg, int value) { outb(reg, 0x164e); @@ -102,12 +105,15 @@ int dlpc_init(void) /* Select DLPC module */ dlpc_write_register(0x07, 0x19); - /* DLPC Base Address 0x164c */ - dlpc_write_register(0x60, 0x16); - dlpc_write_register(0x61, 0x4c); + /* DLPC Base Address */ + dlpc_write_register(0x60, (DLPC_CONTROL >> 8) & 0xff); + dlpc_write_register(0x61, DLPC_CONTROL & 0xff); /* Activate DLPC */ dlpc_write_register(0x30, 0x01); + /* Reset docking state */ + outb(0x00, DLPC_CONTROL); + dlpc_gpio_init(); return 0; } @@ -127,7 +133,7 @@ static int dock_superio_init(void) /* set GPIO pins to Serial/Parallel Port * functions */ - dock_write_register(0x22, 0xeb); + dock_write_register(0x22, 0xa9); dock_write_register(0x07, PC87384_GPIO); dock_write_register(0x60, 0x16); @@ -179,16 +185,16 @@ int dock_connect(void) { int timeout = 1000; - outb(0x07, 0x164c); + outb(0x07, DLPC_CONTROL); timeout = 1000; - while(!(inb(0x164c) & 8) && timeout--) + while(!(inb(DLPC_CONTROL) & 8) && timeout--) udelay(1000); if (!timeout) { /* docking failed, disable DLPC switch */ - outb(0x00, 0x164c); + outb(0x00, DLPC_CONTROL); dlpc_write_register(0x30, 0x00); return 1; } @@ -206,14 +212,25 @@ int dock_connect(void) void dock_disconnect(void) { /* disconnect LPC bus */ - outb(0x00, 0x164c); + outb(0x00, DLPC_CONTROL); /* Assert PLTRST and DLPCPD */ outb(0xfc, 0x1680); } int dock_present(void) { - outb(0x61, 0x15ec); - return inb(0x15ee) & 1; + return pmh7_register_read(0x61) & 1; +} + +int legacy_io_present(void) +{ + return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40); } +void legacy_io_init(void) +{ + /* Enable Power for Ultrabay slot */ + pmh7_ultrabay_power_enable(1); + udelay(100000); + dock_superio_init(); +} diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h index 9d35d9f..631f007 100644 --- a/src/mainboard/lenovo/t60/dock.h +++ b/src/mainboard/lenovo/t60/dock.h @@ -24,4 +24,7 @@ extern int dock_connect(void); extern void dock_disconnect(void); extern int dock_present(void); extern int dlpc_init(void); + +extern int legacy_io_present(void); +extern void legacy_io_init(void); #endif diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 2b8c5fe..8456992 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -38,6 +38,7 @@ static void mainboard_enable(device_t dev) { + struct southbridge_intel_i82801gx_config *config; device_t dev0, idedev; u8 defaults_loaded = 0; @@ -50,8 +51,14 @@ static void mainboard_enable(device_t dev) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); - if (idedev && idedev->chip_info && h8_ultrabay_device_present()) { - struct southbridge_intel_i82801gx_config *config = idedev->chip_info; + + if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) { + /* legacy I/O connected */ + pmh7_ultrabay_power_enable(1); + ec_write(0x0c, 0x84); + } else if (idedev && idedev->chip_info && + h8_ultrabay_device_present()) { + config = idedev->chip_info; config->ide_enable_primary = 1; pmh7_ultrabay_power_enable(1); ec_write(0x0c, 0x84); diff --git a/src/mainboard/lenovo/t60/mainboard_smi.c b/src/mainboard/lenovo/t60/mainboard_smi.c index 4a0b506..eb28256 100644 --- a/src/mainboard/lenovo/t60/mainboard_smi.c +++ b/src/mainboard/lenovo/t60/mainboard_smi.c @@ -75,7 +75,13 @@ int mainboard_io_trap_handler(int smif) switch (smif) { case SMI_DOCK_CONNECT: - dlpc_init(); + /* If there's an legacy I/O module present, we're not + * allowed to connect the Docking LPC Bus, as both Super I/O + * chips are using 0x2e as base address. + */ + if (legacy_io_present()) + break; + if (!dock_connect()) { /* set dock LED to indicate status */ ec_write(0x0c, 0x08); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 252ae40..7ed7768 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -210,7 +210,7 @@ static void early_ich7_init(void) void main(unsigned long bist) { u32 reg32; - int boot_mode = 0; + int boot_mode = 0, dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; if (bist == 0) @@ -223,15 +223,21 @@ void main(unsigned long bist) ich7_enable_lpc(); + /* We want early GPIO setup, to be able to detect legacy I/O module */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + /* Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + setup_ich7_gpios(); - /* dock_init initializes the DLPC switch on - * thinpad side, so this is required even - * if we're undocked. - */ - if (!dlpc_init() && dock_present()) { + dock_err = dlpc_init(); + + /* We prefer Legacy I/O module over docking */ + if (legacy_io_present()) { + legacy_io_init(); + early_superio_config(); + } else if (!dock_err && dock_present()) { dock_connect(); early_superio_config(); - /* Set up the console */ } #if CONFIG_USBDEBUG @@ -239,6 +245,7 @@ void main(unsigned long bist) early_usbdebug_init(); #endif + /* Setup the console */ console_init(); /* Halt if there was a built in self test failure */

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coreboot October 2011