coreboot October 2011

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Re: [coreboot] Getting serial output from w83627hf?
by Alp Eren Köse 18 Oct '11

18 Oct '11

> Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e > Register dump: > idx 02 20 21 22 23 24 25 26 28 29 2a 2b 2c 2e 2f > val ff 52 41 ff fe c0 00 00 00 00 fe c0 ff 00 ff > def 00 52 NA ff 00 MM 00 00 00 00 7c c0 00 00 00 > > > CR24 (idx 24, in the above output) means control register 24, here is a link to the > superio's datasheet: http://www.itox.com/pages/support/wdt/W83627HF.pdf Ok, I got it, but doesn't CR24 is set inside the w83627hf_set_clksel_48() function.. I still got no output from the serial unfortunately? :( 2011/10/18 Idwer Vollering <vidwer(a)gmail.com> > > > 2011/10/18 Alp Eren Köse <alperenkose(a)buyutech.com.tr> > >> Hi thanks all for your help, >> >> I have arranged the "devicetree.cb" as suggested, you can see it at the >> attachment. >> Put the superio chip under the LPC bridge section, but I didn't get how >> did you know it? >> >> Added those to the romstage.c: >> > #include "superio/winbond/w83627hf/early_serial.c" >> > #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) >> > w83627hf_set_clksel_48(SERIAL_DEV); >> >> main() looks like this now: >> ....... // omitted >> sch_enable_lpc(); >> w83627hf_set_clksel_48(SERIAL_DEV); // NEWLY ADDED >> w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); // NEWLY ADDED >> uart_init(); // NEWLY ADDED >> console_init(); >> printk(BIOS_DEBUG, "\n"); // NEWLY ADDED >> ....... // omitted >> >> >> > The bit that controls the clock speed is in CR24. >> But what about this, I don't know where CR24 is and how to set it? Sorry I >> am just really new in such stuff :s > > > Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e > Register dump: > idx 02 20 21 22 23 24 25 26 28 29 2a 2b 2c 2e 2f > val ff 52 41 ff fe c0 00 00 00 00 fe c0 ff 00 ff > def 00 52 NA ff 00 MM 00 00 00 00 7c c0 00 00 00 > > > CR24 (idx 24, in the above output) means control register 24, here is a > link to the superio's datasheet: > http://www.itox.com/pages/support/wdt/W83627HF.pdf > > >> >> >> > SCH boards don't use the serial port but the EHCI debug port to show >> output on? See src/mainboard >> > /iwave/iWRainbowG6/devicetree.cb, it doesn't have the superio included. >> So does it mean I won't be able to get output from the serial port on this >> device for debugging? >> >> >> > Can you show the output from "superiotool -deV" too? Thanks. >> Sure you can find the output in the attachment. >> >> By the way all I get is \0x00 when I open the board and another \0x00 when >> I close it.. >> >> Thanks in advance, >> Alp >> >> >> >> >> 2011/10/17 Idwer Vollering <vidwer(a)gmail.com> >> >>> Comments inline: >>> >>> 2011/10/17 Idwer Vollering <vidwer(a)gmail.com> >>> >>>> >>>> >>>> 2011/10/17 Alp Eren Köse <alperenkose(a)buyutech.com.tr> >>>> >>>>> Hi all, >>>>> >>>>> I can't get serial output from the board I am trying to put coreboot >>>>> on, so I am not able to go any further to see whats going on.. >>>>> >>>> >>>>> The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e. >>>>> >>>> >>>> It is likely that you need to set the serial port's speed in romstage.c: >>>> >>>> // omitting includes, license header >>>> #include "superio/winbond/w83627hf/early_serial.c" >>>> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) >>>> >>>> Add this line to main(): >>>> w83627hf_set_clksel_48(SERIAL_DEV); >>>> >>> >>> The bit that controls the clock speed is in CR24. >>> >>> >>>> >>>> >>>>> >>>>> I couldn't figure out where to put the "chip superio/winbond/w83627hf" >>>>> section in the "devicetree.cb" file layout? >>>>> >>>> >>>> SCH boards don't use the serial port but the EHCI debug port to show >>>> output on? See src/mainboard/iwave/iWRainbowG6/devicetree.cb, it doesn't >>>> have the superio included. >>>> >>>> What I would do is put it inside the LPC bridge section, note that I >>>> don't know how the superio is actually attached and therefore could be >>>> wrong. >>>> So: >>>> chip southbridge/intel/i82801ex >>>> >>> >>> Replace i82801ex with sch, ofcourse. >>> >>> >>>> device pci 1f.0 on # lpc bridge >>>> chip superio/winbond/w83627hf >>>> end # superio >>>> end # 1f.0 >>>> >>>> >>>> >>>>> Could someone please explain the devicetree.cb file structure? or >>>>> point a way? >>>>> >>>>> The "lspci -tvnn" output and my modified "devicetree.cb" file are at >>>>> the attachment. >>>>> >>>> >>> Can you show the output from "superiotool -deV" too? Thanks. >>> >>> >>>>> Thanks in advance, >>>>> Alp >>>>> >>>>> -- >>>>> coreboot mailing list: coreboot(a)coreboot.org >>>>> http://www.coreboot.org/mailman/listinfo/coreboot >>>>> >>>> >>>> >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >>> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Patch set updated for coreboot: 1415c32 Added RAMINIT_SYSINFO and declared the necessary structs
by Oskar Enoksson 18 Oct '11

18 Oct '11

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/236 -gerrit commit 1415c32a1a36d9646c43816113e14bc115ba0dea Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Oct 4 22:15:51 2011 +0200 Added RAMINIT_SYSINFO and declared the necessary structs Using RAMINIT_SYSINFO should be beneficial for this platform. It is also more clean/safe to put data in struct mb_sysconf_t. It's more consistent with other MB's and I've tested it thoroughly on my DL145. Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be --- src/mainboard/hp/dl145_g1/Kconfig | 1 + src/mainboard/hp/dl145_g1/get_bus_conf.c | 54 +++++++++++++---------------- src/mainboard/hp/dl145_g1/irq_tables.c | 19 +++------- src/mainboard/hp/dl145_g1/mb_sysconf.h | 20 +++++++++++ src/mainboard/hp/dl145_g1/mptable.c | 36 +++++++------------ src/mainboard/hp/dl145_g1/romstage.c | 55 +++++++++++++++++------------- 6 files changed, 95 insertions(+), 90 deletions(-) diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index eb90b07..ebd7ffd 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO # select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index e4721ce..6ea751d 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -10,19 +10,12 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> +#include "mb_sysconf.h" // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables -//busnum is default -unsigned char bus_8131_0 = 1; -unsigned char bus_8131_1 = 2; -unsigned char bus_8131_2 = 3; -unsigned char bus_8111_0 = 1; -unsigned char bus_8111_1 = 4; -unsigned apicid_8111 ; -unsigned apicid_8131_1; -unsigned apicid_8131_2; - -unsigned pci1234x[] = +struct mb_sysconf_t mb_sysconf; + +static unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -34,7 +27,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +static unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, // 0x20202020, @@ -45,8 +38,6 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned sbdn3; - static unsigned get_bus_conf_done = 0; @@ -63,6 +54,9 @@ void get_bus_conf(void) get_bus_conf_done = 1; + sysconf.mb = &mb_sysconf; + struct mb_sysconf_t *m = sysconf.mb; + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; @@ -72,36 +66,36 @@ void get_bus_conf(void) get_sblk_pci1234(); sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; - sbdn3 = sysconf.hcdn[0] & 0xff; + m->sbdn3 = sysconf.hcdn[0] & 0xff; - bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; - bus_8111_0 = bus_8131_0; + m->bus_8131_0 = (sysconf.pci1234[0] >> 16) & 0xff; + m->bus_8111_0 = m->bus_8131_0; /* 8111 */ - dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); + dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { - bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", m->bus_8111_0); } /* 8131-1 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,0)); if (dev) { - bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); + m->bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", m->bus_8131_0); } - /* 8132-2 */ - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0)); + /* 8131-2 */ + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,0)); if (dev) { - bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); + m->bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", m->bus_8131_0); } @@ -111,7 +105,7 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_8111 = apicid_base+0; - apicid_8131_1 = apicid_base+1; - apicid_8131_2 = apicid_base+2; + m->apicid_8111 = apicid_base+0; + m->apicid_8131_1 = apicid_base+1; + m->apicid_8131_2 = apicid_base+2; } diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c index b53a992..9d70a89 100644 --- a/src/mainboard/hp/dl145_g1/irq_tables.c +++ b/src/mainboard/hp/dl145_g1/irq_tables.c @@ -11,6 +11,7 @@ #include <arch/pirq_routing.h> #include <cpu/amd/amdk8_sysconf.h> +#include "mb_sysconf.h" static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, @@ -30,23 +31,13 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev pirq_info->rfu = rfu; } -extern unsigned char bus_8131_0; -extern unsigned char bus_8131_1; -extern unsigned char bus_8131_2; -extern unsigned char bus_8111_0; -extern unsigned char bus_8111_1; - -extern unsigned sbdn3; - - - unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; struct irq_info *pirq_info; unsigned slot_num; uint8_t *v; + struct mb_sysconf_t *m = sysconf.mb; uint8_t sum=0; int i; @@ -66,7 +57,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_8111_0; + pirq->rtr_bus = m->bus_8111_0; pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0; pirq->exclusive_irqs = 0; @@ -81,10 +72,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info = (void *) ( &pirq->checksum + 1); slot_num = 0; //pci bridge - write_pirq_info(pirq_info, bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); + write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; //pcix bridge -// write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); +// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); // pirq_info++; slot_num++; pirq_info++; slot_num++; diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h new file mode 100644 index 0000000..0bceab4 --- /dev/null +++ b/src/mainboard/hp/dl145_g1/mb_sysconf.h @@ -0,0 +1,20 @@ +#ifndef MB_SYSCONF_H + +#define MB_SYSCONF_H + +struct mb_sysconf_t { + unsigned char bus_8131_0; + unsigned char bus_8131_1; + unsigned char bus_8131_2; + unsigned char bus_8111_0; + unsigned char bus_8111_1; + + unsigned apicid_8111; + unsigned apicid_8131_1; + unsigned apicid_8131_2; + + unsigned sbdn3; +}; + +#endif + diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index 010f986..c15dff6 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -5,17 +5,7 @@ #include <string.h> #include <stdint.h> #include <cpu/amd/amdk8_sysconf.h> - -extern unsigned char bus_8131_0; -extern unsigned char bus_8131_1; -extern unsigned char bus_8131_2; -extern unsigned char bus_8111_0; -extern unsigned char bus_8111_1; -extern unsigned apicid_8111; -extern unsigned apicid_8131_1; -extern unsigned apicid_8131_2; - -extern unsigned sbdn3; +#include "mb_sysconf.h" static void *smp_write_config_table(void *v) { @@ -30,31 +20,33 @@ static void *smp_write_config_table(void *v) get_bus_conf(); + struct mb_sysconf_t *m = sysconf.mb; + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ - smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR); + smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR); { device_t dev; struct resource *res; - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base); + smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base); } } - dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); + dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { - smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base); + smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base); } } } - mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0); + mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); // // The commented-out lines are auto-detected on my servers. @@ -66,18 +58,18 @@ static void *smp_write_config_table(void *v) //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); // Integrated AMD USB - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13); // On board ATI Rage XL //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); // On board Broadcom nics - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00); // On board LSI SCSI //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); // PCIX-133 Slot - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index f51b4c4..c0a12d9 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -1,17 +1,17 @@ #include <stdint.h> #include <string.h> #include <device/pci_def.h> +#include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/amdk8.h" #include "southbridge/amd/amd8111/early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/early_serial.c" @@ -55,7 +55,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) do { ret = smbus_write_byte(SMBUS_HUB, 0x01, device); } while ((ret!=0) && (i-->0)); - smbus_write_byte(SMBUS_HUB, 0x03, 0); } @@ -77,6 +76,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -86,8 +86,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#define RC0 ((1<<1)<<8) // Not sure about these values -#define RC1 ((1<<2)<<8) // Not sure about these values +#define RC0 ((1<<1)<<8) +#define RC1 ((1<<2)<<8) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -101,13 +101,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) RC1|DIMM1, RC1|DIMM3, 0, 0, #endif }; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; - unsigned bsp_apicid = 0, nodes; - struct mem_controller ctrl[8]; + int needs_reset = 0; + unsigned bsp_apicid = 0; if (bist == 0) - bsp_apicid = init_cpus(cpu_init_detectedx); + bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -115,47 +116,53 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + setup_dl145g1_resource_map(); //setup_default_resource_map(); - needs_reset = setup_coherent_ht_domain(); - - wait_all_core0_started(); +#if CONFIG_MEM_TRAIN_SEQ == 1 + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram +#endif + setup_coherent_ht_domain(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif - needs_reset |= ht_setup_chains_x(); + ht_setup_chains_x(sysinfo); - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); - } + needs_reset |= optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } enable_smbus(); int i; for(i=0;i<2;i++) { - activate_spd_rom(&ctrl[i]); + activate_spd_rom(&sysinfo->ctrl[i]); } - for(i=2;i<8;i<<=1) { + for(i=RC0;i<=RC1;i<<=1) { change_i2c_mux(i); } - //dump_spd_registers(&ctrl[0]); - //dump_spd_registers(&ctrl[1]); + //dump_spd_registers(&sysinfo->ctrl[0]); + //dump_spd_registers(&sysinfo->ctrl[1]); //dump_smbus_registers(); allow_all_aps_stop(bsp_apicid); - nodes = get_nodes(); //It's the time to set ctrl now; - fill_mem_ctrl(nodes, ctrl, spd_addr); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); - sdram_initialize(nodes, ctrl); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); //dump_pci_devices();

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Patch set updated for coreboot: d3cb685 Add test pattern to assist in DIMM configuration.
by Kyösti Mälkki 18 Oct '11

18 Oct '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/294 -gerrit commit d3cb685e0112b6cf9430255ea7424e1f8d2ff8dc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 18 14:32:10 2011 +0300 Add test pattern to assist in DIMM configuration. This is developer's tool. Output from this "rotate ones" -style pattern helps figure out how DIMM addresses are encoded or routed on a certain mainboard. Change-Id: I533a7a873bcc434f99e7faed9dc9337d9ab64196 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/ramtest.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 72 insertions(+), 0 deletions(-) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 3f4657f..5bd0223 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -47,6 +47,77 @@ static void phys_memory_barrier(void) #endif } +/** + * Simple rotate ones test pattern for 128bit wide memory bus. + * See console debug output for any dislocated bytes. + * + * for (i=0; i<8; i++) + * for (j=0; j<16; j++) + * *(start + i<<4 + j) = 1<<i; + * + * @start System memory offset, aligned to 128bytes + */ +static void ram_bitset(unsigned long start) +{ + unsigned long value, value2; + unsigned long addr; + uint8_t i; + uint8_t verbose = 0; + /* + * Fill. + */ +#if CONFIG_CACHE_AS_RAM + printk(BIOS_DEBUG, "DRAM bitset write: 0x%08lx\n", start); +#else + print_debug("DRAM bitset write: 0x"); + print_debug_hex32(start); + print_debug("\n"); +#endif + value = 0x01010101; + for(addr = start; addr < (start + 0x80) ; addr += 4) { + + if ((addr & 0xf0) && (! (addr & 0x0f))) + value <<= 1; + write_phys(addr, value); + }; + phys_memory_barrier(); +#if CONFIG_CACHE_AS_RAM + printk(BIOS_DEBUG, "DRAM bitset verify: 0x%08lx\n", start); +#else + print_debug("DRAM bitset verify: 0x"); + print_debug_hex32(start); + print_debug("\n"); +#endif + value = 0x01010101; + for(addr = start; addr < (start + 0x80) ; addr += 4) { + + if ((addr & 0xf0) && (! (addr & 0x0f))) + value <<= 1; + + value2 = read_phys(addr); + i = (value2 != value); + + if ( i || verbose ) { +#if CONFIG_CACHE_AS_RAM + printk(BIOS_ERR, "0x%08lx wr: 0x%08lx rd: 0x%08lx\n", + addr, value, value2); +#else + print_err_hex32(addr); + print_err(" wr: 0x"); + print_err_hex32(value); + print_err(" rd: 0x"); + print_err_hex32(value2); +#endif + } + if (i) + print_err(" FAIL\n"); + else if (verbose) + print_err("\n"); + }; + +} + + static void ram_fill(unsigned long start, unsigned long stop) { unsigned long addr; @@ -174,6 +245,7 @@ void ram_check(unsigned long start, unsigned long stop) print_debug_hex32(stop); print_debug("\n"); #endif + ram_bitset(start); ram_fill(start, stop); /* Make sure we don't read before we wrote */ phys_memory_barrier();

1 0

Patch set updated for coreboot: ca2c760 Added smbus block operations for amd8111
by Oskar Enoksson 18 Oct '11

18 Oct '11

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/281 -gerrit commit ca2c760ba546f6c16f0468ca989898d992bc230d Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Fri Oct 14 02:16:48 2011 +0200 Added smbus block operations for amd8111 Also fixed bug in one function prototype: smbus_block_read should pass pointer to block length, not value. At least it makes no sense to me to pass a value(?) Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> Change-Id: I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc --- src/devices/smbus_ops.c | 2 +- src/include/device/smbus.h | 4 +- src/southbridge/amd/amd8111/acpi.c | 25 +++++++ src/southbridge/amd/amd8111/amd8111_smbus.h | 98 +++++++++++++++++++++++++++ src/southbridge/amd/amd8111/early_smbus.c | 9 +++ 5 files changed, 135 insertions(+), 3 deletions(-) diff --git a/src/devices/smbus_ops.c b/src/devices/smbus_ops.c index 75ca42b..d0e226f 100644 --- a/src/devices/smbus_ops.c +++ b/src/devices/smbus_ops.c @@ -124,7 +124,7 @@ int smbus_process_call(device_t dev, u8 cmd, u16 data) return ops_smbus_bus(get_pbus_smbus(dev))->process_call(dev, cmd, data); } -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer) +int smbus_block_read(device_t dev, u8 cmd, u8 *bytes, u8 *buffer) { return ops_smbus_bus(get_pbus_smbus(dev))->block_read(dev, cmd, bytes, buffer); diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index 073d7e2..bd8f8ce 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -17,7 +17,7 @@ struct smbus_bus_operations { int (*read_word) (device_t dev, u8 addr); int (*write_word) (device_t dev, u8 addr, u16 value); int (*process_call)(device_t dev, u8 cmd, u16 data); - int (*block_read) (device_t dev, u8 cmd, u8 bytes, u8 *buffer); + int (*block_read) (device_t dev, u8 cmd, u8 *bytes, u8 *buffer); int (*block_write) (device_t dev, u8 cmd, u8 bytes, const u8 *buffer); }; @@ -44,7 +44,7 @@ int smbus_write_byte(device_t dev, u8 addr, u8 val); int smbus_read_word(device_t dev, u8 addr); int smbus_write_word(device_t dev, u8 addr, u16 val); int smbus_process_call(device_t dev, u8 cmd, u16 data); -int smbus_block_read(device_t dev, u8 cmd, u8 bytes, u8 *buffer); +int smbus_block_read(device_t dev, u8 cmd, u8 *bytes, u8 *buffer); int smbus_block_write(device_t dev, u8 cmd, u8 bytes, const u8 *buffer); #endif /* DEVICE_SMBUS_H */ diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 2ad54b7..0c78b91 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -66,6 +66,29 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) return do_smbus_write_byte(res->base, device, address, val); } +static int lsmbus_block_read(device_t dev, uint8_t cmd, u8 *bytes, u8 *buffer) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_block_read(res->base, device, cmd, bytes, buffer); +} + +static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buffer) +{ + unsigned device; + struct resource *res; + + device = dev->path.i2c.device; + res = find_resource(get_pbus_smbus(dev)->dev, 0x58); + + return do_smbus_block_write(res->base, device, cmd, bytes, buffer); +} + + #if CONFIG_GENERATE_ACPI_TABLES == 1 unsigned pm_base; #endif @@ -191,6 +214,8 @@ static struct smbus_bus_operations lops_smbus_bus = { .send_byte = lsmbus_send_byte, .read_byte = lsmbus_read_byte, .write_byte = lsmbus_write_byte, + .block_read = lsmbus_block_read, + .block_write= lsmbus_block_write, }; static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h index fe9b3bf..f07893d 100644 --- a/src/southbridge/amd/amd8111/amd8111_smbus.h +++ b/src/southbridge/amd/amd8111/amd8111_smbus.h @@ -222,3 +222,101 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned return 0; } +static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned cmd, u8 *bytes, u8 *buf) +{ + unsigned global_status_register; + unsigned i; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + /* set the command/address... */ + outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD); + /* set up for a block data read */ + outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL); + + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); + + /* clear the length word...*/ + outw(0, smbus_io_base + SMBHSTDAT); + + /* start the command */ + outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + + global_status_register = inw(smbus_io_base + SMBGSTATUS); + + /* read results of transaction */ + *bytes = inw(smbus_io_base + SMBHSTDAT) & 0x3f; + + if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { + return SMBUS_ERROR; + } + + /* read data block */ + for(i=0; i<*bytes; i++) { + buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff; + } + + return 0; +} + +static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +{ + unsigned global_status_register; + unsigned i; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + } + + /* setup transaction */ + /* disable interrupts */ + outw(inw(smbus_io_base + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), smbus_io_base + SMBGCTL); + /* set the device I'm talking too */ + outw(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + /* set the command/address... */ + outb(cmd & 0xFF, smbus_io_base + SMBHSTCMD); + /* set up for a block data write */ + outw((inw(smbus_io_base + SMBGCTL) & ~7) | (0x5), smbus_io_base + SMBGCTL); + + /* clear any lingering errors, so the transaction will run */ + /* Do I need to write the bits to a 1 to clear an error? */ + outw(inw(smbus_io_base + SMBGSTATUS), smbus_io_base + SMBGSTATUS); + + /* set the length word...*/ + outw(bytes, smbus_io_base + SMBHSTDAT); + + /* set the data block */ + for(i=0; i<bytes; i++) { + outw(buf[i], smbus_io_base + SMBHSTFIFO); + } + + /* start the command */ + outw((inw(smbus_io_base + SMBGCTL) | (1 << 3)), smbus_io_base + SMBGCTL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + } + global_status_register = inw(smbus_io_base + SMBGSTATUS); + + if ((global_status_register & SMBUS_STATUS_MASK) != (1 << 4)) { + return SMBUS_ERROR; + } + return 0; +} + + diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index e6d7084..9a58a99 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -46,3 +46,12 @@ static inline int smbus_write_byte(unsigned device, unsigned address, unsigned c return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } +static inline int smbus_block_read(unsigned device, unsigned cmd, u8 *bytes, u8 *buf) +{ + return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); +} + +static inline int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +{ + return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); +}

1 0

New patch to review for coreboot: 1680aa2 Add test pattern to assist in DIMM configuration.
by Kyösti Mälkki 18 Oct '11

18 Oct '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/294 -gerrit commit 1680aa2c434c9899c02241b13e8eba54ea724bc7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 18 14:32:10 2011 +0300 Add test pattern to assist in DIMM configuration. This is developer's tool. Output from this "rotate ones" -style pattern helps figure out how DIMM addresses are encoded or routed on a certain mainboard. Change-Id: I533a7a873bcc434f99e7faed9dc9337d9ab64196 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/ramtest.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 57 insertions(+), 0 deletions(-) diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 3f4657f..56ce6ed 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -47,6 +47,62 @@ static void phys_memory_barrier(void) #endif } +static void ram_bitset(unsigned long start) +{ + unsigned long value, value2; + unsigned long addr; + uint8_t i; + uint8_t verbose = 0; + /* + * Fill. + */ +#if CONFIG_CACHE_AS_RAM + printk(BIOS_DEBUG, "DRAM bitset write: 0x%08lx\n", start); +#else + print_debug("DRAM bitset write: 0x"); + print_debug_hex32(start); + print_debug("\n"); +#endif + value = 0x01010101; + for(addr = start; addr < (start + 0x80) ; addr += 4) { + + if ((addr & 0xf0) && (! (addr & 0x0f))) + value <<= 1; + write_phys(addr, value); + }; + phys_memory_barrier(); +#if CONFIG_CACHE_AS_RAM + printk(BIOS_DEBUG, "DRAM bitset verify: 0x%08lx\n", start); +#else + print_debug("DRAM bitset verify: 0x"); + print_debug_hex32(start); + print_debug("\n"); +#endif + value = 0x01010101; + for(addr = start; addr < (start + 0x80) ; addr += 4) { + + if ((addr & 0xf0) && (! (addr & 0x0f))) + value <<= 1; + + value2 = read_phys(addr); + i = (value2 != value); + + if ( i || verbose ) { + print_err_hex32(addr); + print_err(" wr: 0x"); + print_err_hex32(value); + print_err(" rd: 0x"); + print_err_hex32(value2); + } + if (i) + print_err(" FAIL\n"); + else if (verbose) + print_err("\n"); + }; + +} + + static void ram_fill(unsigned long start, unsigned long stop) { unsigned long addr; @@ -174,6 +230,7 @@ void ram_check(unsigned long start, unsigned long stop) print_debug_hex32(stop); print_debug("\n"); #endif + ram_bitset(start); ram_fill(start, stop); /* Make sure we don't read before we wrote */ phys_memory_barrier();

1 0

Re: [coreboot] Getting serial output from w83627hf?
by Idwer Vollering 18 Oct '11

18 Oct '11

2011/10/18 Alp Eren Köse <alperenkose(a)buyutech.com.tr> > Hi thanks all for your help, > > I have arranged the "devicetree.cb" as suggested, you can see it at the > attachment. > Put the superio chip under the LPC bridge section, but I didn't get how did > you know it? > > Added those to the romstage.c: > > #include "superio/winbond/w83627hf/early_serial.c" > > #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) > > w83627hf_set_clksel_48(SERIAL_DEV); > > main() looks like this now: > ....... // omitted > sch_enable_lpc(); > w83627hf_set_clksel_48(SERIAL_DEV); // NEWLY ADDED > w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); // NEWLY ADDED > uart_init(); // NEWLY ADDED > console_init(); > printk(BIOS_DEBUG, "\n"); // NEWLY ADDED > ....... // omitted > > > > The bit that controls the clock speed is in CR24. > But what about this, I don't know where CR24 is and how to set it? Sorry I > am just really new in such stuff :s Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e Register dump: idx 02 20 21 22 23 24 25 26 28 29 2a 2b 2c 2e 2f val ff 52 41 ff fe c0 00 00 00 00 fe c0 ff 00 ff def 00 52 NA ff 00 MM 00 00 00 00 7c c0 00 00 00 CR24 (idx 24, in the above output) means control register 24, here is a link to the superio's datasheet: http://www.itox.com/pages/support/wdt/W83627HF.pdf > > > > SCH boards don't use the serial port but the EHCI debug port to show > output on? See src/mainboard > > /iwave/iWRainbowG6/devicetree.cb, it doesn't have the superio included. > So does it mean I won't be able to get output from the serial port on this > device for debugging? > > > > Can you show the output from "superiotool -deV" too? Thanks. > Sure you can find the output in the attachment. > > By the way all I get is \0x00 when I open the board and another \0x00 when > I close it.. > > Thanks in advance, > Alp > > > > > 2011/10/17 Idwer Vollering <vidwer(a)gmail.com> > >> Comments inline: >> >> 2011/10/17 Idwer Vollering <vidwer(a)gmail.com> >> >>> >>> >>> 2011/10/17 Alp Eren Köse <alperenkose(a)buyutech.com.tr> >>> >>>> Hi all, >>>> >>>> I can't get serial output from the board I am trying to put coreboot on, >>>> so I am not able to go any further to see whats going on.. >>>> >>> >>>> The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e. >>>> >>> >>> It is likely that you need to set the serial port's speed in romstage.c: >>> >>> // omitting includes, license header >>> #include "superio/winbond/w83627hf/early_serial.c" >>> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) >>> >>> Add this line to main(): >>> w83627hf_set_clksel_48(SERIAL_DEV); >>> >> >> The bit that controls the clock speed is in CR24. >> >> >>> >>> >>>> >>>> I couldn't figure out where to put the "chip superio/winbond/w83627hf" >>>> section in the "devicetree.cb" file layout? >>>> >>> >>> SCH boards don't use the serial port but the EHCI debug port to show >>> output on? See src/mainboard/iwave/iWRainbowG6/devicetree.cb, it doesn't >>> have the superio included. >>> >>> What I would do is put it inside the LPC bridge section, note that I >>> don't know how the superio is actually attached and therefore could be >>> wrong. >>> So: >>> chip southbridge/intel/i82801ex >>> >> >> Replace i82801ex with sch, ofcourse. >> >> >>> device pci 1f.0 on # lpc bridge >>> chip superio/winbond/w83627hf >>> end # superio >>> end # 1f.0 >>> >>> >>> >>>> Could someone please explain the devicetree.cb file structure? or point >>>> a way? >>>> >>>> The "lspci -tvnn" output and my modified "devicetree.cb" file are at the >>>> attachment. >>>> >>> >> Can you show the output from "superiotool -deV" too? Thanks. >> >> >>>> Thanks in advance, >>>> Alp >>>> >>>> -- >>>> coreboot mailing list: coreboot(a)coreboot.org >>>> http://www.coreboot.org/mailman/listinfo/coreboot >>>> >>> >>> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Getting serial output from w83627hf?
by Alp Eren Köse 18 Oct '11

18 Oct '11

Hi thanks all for your help, I have arranged the "devicetree.cb" as suggested, you can see it at the attachment. Put the superio chip under the LPC bridge section, but I didn't get how did you know it? Added those to the romstage.c: > #include "superio/winbond/w83627hf/early_serial.c" > #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) > w83627hf_set_clksel_48(SERIAL_DEV); main() looks like this now: ....... // omitted sch_enable_lpc(); w83627hf_set_clksel_48(SERIAL_DEV); // NEWLY ADDED w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); // NEWLY ADDED uart_init(); // NEWLY ADDED console_init(); printk(BIOS_DEBUG, "\n"); // NEWLY ADDED ....... // omitted > The bit that controls the clock speed is in CR24. But what about this, I don't know where CR24 is and how to set it? Sorry I am just really new in such stuff :s > SCH boards don't use the serial port but the EHCI debug port to show output on? See src/mainboard > /iwave/iWRainbowG6/devicetree.cb, it doesn't have the superio included. So does it mean I won't be able to get output from the serial port on this device for debugging? > Can you show the output from "superiotool -deV" too? Thanks. Sure you can find the output in the attachment. By the way all I get is \0x00 when I open the board and another \0x00 when I close it.. Thanks in advance, Alp 2011/10/17 Idwer Vollering <vidwer(a)gmail.com> > Comments inline: > > 2011/10/17 Idwer Vollering <vidwer(a)gmail.com> > >> >> >> 2011/10/17 Alp Eren Köse <alperenkose(a)buyutech.com.tr> >> >>> Hi all, >>> >>> I can't get serial output from the board I am trying to put coreboot on, >>> so I am not able to go any further to see whats going on.. >>> >> >>> The board has a Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e. >>> >> >> It is likely that you need to set the serial port's speed in romstage.c: >> >> // omitting includes, license header >> #include "superio/winbond/w83627hf/early_serial.c" >> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) >> >> Add this line to main(): >> w83627hf_set_clksel_48(SERIAL_DEV); >> > > The bit that controls the clock speed is in CR24. > > >> >> >>> >>> I couldn't figure out where to put the "chip superio/winbond/w83627hf" >>> section in the "devicetree.cb" file layout? >>> >> >> SCH boards don't use the serial port but the EHCI debug port to show >> output on? See src/mainboard/iwave/iWRainbowG6/devicetree.cb, it doesn't >> have the superio included. >> >> What I would do is put it inside the LPC bridge section, note that I don't >> know how the superio is actually attached and therefore could be wrong. >> So: >> chip southbridge/intel/i82801ex >> > > Replace i82801ex with sch, ofcourse. > > >> device pci 1f.0 on # lpc bridge >> chip superio/winbond/w83627hf >> end # superio >> end # 1f.0 >> >> >> >>> Could someone please explain the devicetree.cb file structure? or point >>> a way? >>> >>> The "lspci -tvnn" output and my modified "devicetree.cb" file are at the >>> attachment. >>> >> > Can you show the output from "superiotool -deV" too? Thanks. > > >>> Thanks in advance, >>> Alp >>> >>> -- >>> coreboot mailing list: coreboot(a)coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >>> >> >> > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Patch set updated for coreboot: ec8dd51 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
by Sven Schnelle 18 Oct '11

18 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/282 -gerrit commit ec8dd51ce7df16ddca1d834b97f67be830683ce4 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sat Oct 15 17:31:01 2011 +0200 T60: Add support for Ultrabay Legacy I/O devices (40Y8122) Those modules have basically the same Super I/O capabilities as the Docking station. Unfortunately, the Super I/O in the module shares the same I/O address as the Docking station, so we're not allowed to connect the LPC Docking Bus if such a module is present. To be able to detect this device and use it as early console for coreboot, we have to initialize the GPIO Controller before, as this device is detected via GPIO06. Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/ec/lenovo/pmh7/Makefile.inc | 2 + src/ec/lenovo/pmh7/pmh7.c | 4 +++ src/mainboard/lenovo/t60/dock.c | 37 +++++++++++++++++++++-------- src/mainboard/lenovo/t60/dock.h | 3 ++ src/mainboard/lenovo/t60/mainboard.c | 11 +++++++- src/mainboard/lenovo/t60/mainboard_smi.c | 8 +++++- src/mainboard/lenovo/t60/romstage.c | 21 +++++++++++----- 7 files changed, 66 insertions(+), 20 deletions(-) diff --git a/src/ec/lenovo/pmh7/Makefile.inc b/src/ec/lenovo/pmh7/Makefile.inc index 4c891b2..e441980 100644 --- a/src/ec/lenovo/pmh7/Makefile.inc +++ b/src/ec/lenovo/pmh7/Makefile.inc @@ -1 +1,3 @@ driver-y += pmh7.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += pmh7.c +romstage-y += pmh7.c diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 30460c9..844e233 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -91,6 +91,8 @@ void pmh7_register_write(int reg, int val) outb(val, EC_LENOVO_PMH7_DATA); } +#ifndef __PRE_RAM__ +#ifndef __SMM__ static void enable_dev(device_t dev) { struct ec_lenovo_pmh7_config *conf = dev->chip_info; @@ -115,3 +117,5 @@ struct chip_operations ec_lenovo_pmh7_ops = { CHIP_NAME("Lenovo Power Management Hardware Hub 7") .enable_dev = enable_dev, }; +#endif +#endif diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 6642bb3..5cd8997 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -28,8 +28,11 @@ #include "dock.h" #include "superio/nsc/pc87384/pc87384.h" #include "ec/acpi/ec.h" +#include "ec/lenovo/pmh7/pmh7.h" #include "southbridge/intel/i82801gx/i82801gx.h" +#define DLPC_CONTROL 0x164c + static void dlpc_write_register(int reg, int value) { outb(reg, 0x164e); @@ -102,12 +105,15 @@ int dlpc_init(void) /* Select DLPC module */ dlpc_write_register(0x07, 0x19); - /* DLPC Base Address 0x164c */ - dlpc_write_register(0x60, 0x16); - dlpc_write_register(0x61, 0x4c); + /* DLPC Base Address */ + dlpc_write_register(0x60, (DLPC_CONTROL >> 8) & 0xff); + dlpc_write_register(0x61, DLPC_CONTROL & 0xff); /* Activate DLPC */ dlpc_write_register(0x30, 0x01); + /* Reset docking state */ + outb(0x00, DLPC_CONTROL); + dlpc_gpio_init(); return 0; } @@ -127,7 +133,7 @@ static int dock_superio_init(void) /* set GPIO pins to Serial/Parallel Port * functions */ - dock_write_register(0x22, 0xeb); + dock_write_register(0x22, 0xa9); dock_write_register(0x07, PC87384_GPIO); dock_write_register(0x60, 0x16); @@ -179,16 +185,16 @@ int dock_connect(void) { int timeout = 1000; - outb(0x07, 0x164c); + outb(0x07, DLPC_CONTROL); timeout = 1000; - while(!(inb(0x164c) & 8) && timeout--) + while(!(inb(DLPC_CONTROL) & 8) && timeout--) udelay(1000); if (!timeout) { /* docking failed, disable DLPC switch */ - outb(0x00, 0x164c); + outb(0x00, DLPC_CONTROL); dlpc_write_register(0x30, 0x00); return 1; } @@ -206,14 +212,25 @@ int dock_connect(void) void dock_disconnect(void) { /* disconnect LPC bus */ - outb(0x00, 0x164c); + outb(0x00, DLPC_CONTROL); /* Assert PLTRST and DLPCPD */ outb(0xfc, 0x1680); } int dock_present(void) { - outb(0x61, 0x15ec); - return inb(0x15ee) & 1; + return pmh7_register_read(0x61) & 1; +} + +int legacy_io_present(void) +{ + return !(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40); } +void legacy_io_init(void) +{ + /* Enable Power for Ultrabay slot */ + pmh7_ultrabay_power_enable(1); + udelay(100000); + dock_superio_init(); +} diff --git a/src/mainboard/lenovo/t60/dock.h b/src/mainboard/lenovo/t60/dock.h index 9d35d9f..631f007 100644 --- a/src/mainboard/lenovo/t60/dock.h +++ b/src/mainboard/lenovo/t60/dock.h @@ -24,4 +24,7 @@ extern int dock_connect(void); extern void dock_disconnect(void); extern int dock_present(void); extern int dlpc_init(void); + +extern int legacy_io_present(void); +extern void legacy_io_init(void); #endif diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 2b8c5fe..8456992 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -38,6 +38,7 @@ static void mainboard_enable(device_t dev) { + struct southbridge_intel_i82801gx_config *config; device_t dev0, idedev; u8 defaults_loaded = 0; @@ -50,8 +51,14 @@ static void mainboard_enable(device_t dev) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); - if (idedev && idedev->chip_info && h8_ultrabay_device_present()) { - struct southbridge_intel_i82801gx_config *config = idedev->chip_info; + + if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) { + /* legacy I/O connected */ + pmh7_ultrabay_power_enable(1); + ec_write(0x0c, 0x84); + } else if (idedev && idedev->chip_info && + h8_ultrabay_device_present()) { + config = idedev->chip_info; config->ide_enable_primary = 1; pmh7_ultrabay_power_enable(1); ec_write(0x0c, 0x84); diff --git a/src/mainboard/lenovo/t60/mainboard_smi.c b/src/mainboard/lenovo/t60/mainboard_smi.c index 4a0b506..eb28256 100644 --- a/src/mainboard/lenovo/t60/mainboard_smi.c +++ b/src/mainboard/lenovo/t60/mainboard_smi.c @@ -75,7 +75,13 @@ int mainboard_io_trap_handler(int smif) switch (smif) { case SMI_DOCK_CONNECT: - dlpc_init(); + /* If there's an legacy I/O module present, we're not + * allowed to connect the Docking LPC Bus, as both Super I/O + * chips are using 0x2e as base address. + */ + if (legacy_io_present()) + break; + if (!dock_connect()) { /* set dock LED to indicate status */ ec_write(0x0c, 0x08); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 252ae40..7ed7768 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -210,7 +210,7 @@ static void early_ich7_init(void) void main(unsigned long bist) { u32 reg32; - int boot_mode = 0; + int boot_mode = 0, dock_err; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; if (bist == 0) @@ -223,15 +223,21 @@ void main(unsigned long bist) ich7_enable_lpc(); + /* We want early GPIO setup, to be able to detect legacy I/O module */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + /* Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + setup_ich7_gpios(); - /* dock_init initializes the DLPC switch on - * thinpad side, so this is required even - * if we're undocked. - */ - if (!dlpc_init() && dock_present()) { + dock_err = dlpc_init(); + + /* We prefer Legacy I/O module over docking */ + if (legacy_io_present()) { + legacy_io_init(); + early_superio_config(); + } else if (!dock_err && dock_present()) { dock_connect(); early_superio_config(); - /* Set up the console */ } #if CONFIG_USBDEBUG @@ -239,6 +245,7 @@ void main(unsigned long bist) early_usbdebug_init(); #endif + /* Setup the console */ console_init(); /* Halt if there was a built in self test failure */

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New patch to review for coreboot: f2361f6 asrock/e350m1: Enable the superio ACPI device in devicetree.cb
by Peter Stuge 18 Oct '11

18 Oct '11

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/292 -gerrit commit f2361f668a36b70c449486bfb3dfae74aefbaff7 Author: Peter Stuge <peter(a)stuge.se> Date: Tue Oct 18 05:10:36 2011 +0200 asrock/e350m1: Enable the superio ACPI device in devicetree.cb Change-Id: I96f05f82d7f133b343cf8d4ef09db50a3db7a83d Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/mainboard/asrock/e350m1/devicetree.cb | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index ca5cf2b..a4bdc65 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -90,7 +90,7 @@ chip northbridge/amd/agesa/family14/root_complex end device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI + device pnp 2e.a on end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 irq 0x70 = 5

2 1

Patch set updated for coreboot: d088d0d I945: replace #if defined() by #if
by Sven Schnelle 18 Oct '11

18 Oct '11

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/293 -gerrit commit d088d0d4acbd8e3b0c6c410aed9ed5bde2018cd5 Author: Sven Schnelle <svens(a)stackframe.org> Date: Tue Oct 18 07:58:10 2011 +0200 I945: replace #if defined() by #if config.h defines also unset config options (as "0") so #ifdef matches both settings, which isn't what we want. Change-Id: I694e1b8a8ec4c20225d7af1a13a2a336f900e643 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i945/early_init.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 197c58f..14c66c4 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -91,7 +91,7 @@ static void i945m_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GC) +#if CONFIG_NORTHBRIDGE_INTEL_I945GC printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif } @@ -140,7 +140,7 @@ static void i945_detect_chipset(void) printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8); /* Others reserved. */ } printk(BIOS_DEBUG, "\n"); -#if defined(CONFIG_NORTHBRIDGE_INTEL_I945GM) +#if CONFIG_NORTHBRIDGE_INTEL_I945GM printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n"); #endif }

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coreboot October 2011