coreboot October 2011

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501 discussions

New patch to review for coreboot: 63c55f8 libpayload: fix bulk transfers on OHCI controllers
by Patrick Georgi 21 Oct '11

21 Oct '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/306 -gerrit commit 63c55f820611f3e46f6323d6b22ede3444a6d039 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Oct 21 15:45:09 2011 +0200 libpayload: fix bulk transfers on OHCI controllers Time for the brown paper bag: OHCI controllers are not happy when told to send data, but with obviously wrong addresses. It helps to write the addresses into the data structures. Change-Id: Ic0967dc8939e64af119cfb89400a045a2c077171 Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- payloads/libpayload/drivers/usb/ohci.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 94c1945..290f782 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -384,6 +384,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *data, int finalize) cur->delay_interrupt = 7; cur->condition_code = 0xf; cur->direction = (ep->direction==IN)?OHCI_IN:OHCI_OUT; + cur->current_buffer_pointer = virt_to_phys(data); pages--; if (dalen == 0) { /* magic TD for empty packet transfer */

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Re: [coreboot] Intel SCH CMC(Chipset Microcode) state machine binary?
by Patrick Georgi 21 Oct '11

21 Oct '11

Am 21.10.2011 13:41, schrieb Alp Eren Köse: > But unfortunately I needed a windoz machine to extract the CMC binary, > you can use the CBROM utility like this: > C:\> CBROM32_195.EXE vendor_bios.bin /TOPHOLE:FFFD0000 extract I'd say you can do the same with dd(1), no? > http://www.coreboot.org/pipermail/coreboot/2011-March/064246.html See http://review.coreboot.org/305 Regards, Patrick -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg

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Patch merged into coreboot/master: 699632f Use ntohll where appropriate.
by gerrit＠coreboot.org 21 Oct '11

21 Oct '11

the following patch was just integrated into master: commit 699632f2925fdcb16d4dcdaed99728e29588e083 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Oct 17 09:51:15 2011 -0700 Use ntohll where appropriate. also clean out a local copy of ntohl in yabel. Change-Id: Iffe85a53c9ea25abeb3ac663870eb7eb4874a704 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/288 for details. -gerrit

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Patch merged into coreboot/master: d2708a3 Add macros for 64bit byte order swapping
by gerrit＠coreboot.org 21 Oct '11

21 Oct '11

the following patch was just integrated into master: commit d2708a3116aebba4345189ba5eb94600b7c00720 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Oct 14 15:11:16 2011 -0700 Add macros for 64bit byte order swapping Change-Id: Ic31ccd41ba3e0af7046eafc29221810d4cd196c8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/275 for details. -gerrit

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New patch to review for coreboot: ac37481 sch: strip quotes around cmc.bin filename
by Patrick Georgi 21 Oct '11

21 Oct '11

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/305 -gerrit commit ac37481fcfd03066cce04f08c1d523b923027c67 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Oct 21 13:56:04 2011 +0200 sch: strip quotes around cmc.bin filename This was mentioned several times already, how about we get it in? It avoids cbfstool to fail because path/to/"file" doesn't work. Change-Id: Ia01acbd78f81a5db890fd1573a2f3cbe1450562f Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- src/southbridge/intel/sch/Makefile.inc | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc index 5d829dd..42ff877 100644 --- a/src/southbridge/intel/sch/Makefile.inc +++ b/src/southbridge/intel/sch/Makefile.inc @@ -37,6 +37,6 @@ romstage-$(CONFIG_USBDEBUG) += usb_debug.c # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin -cmc.bin-file := $(CONFIG_CMC_FILE) +cmc.bin-file := $(call strip_quotes,$(CONFIG_CMC_FILE)) cmc.bin-type := 0xaa cmc.bin-position := 0xfffd0000

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Re: [coreboot] Intel SCH CMC(Chipset Microcode) state machine binary?
by Svante Ekholm 21 Oct '11

21 Oct '11

>From what I've read from the Intel SCH specification, the CMC is a binary located at the top of the memory space at locations 0xFFFB0000, 0xFFFC0000, 0xFFFD0000 (default) or 0xFFFE0000. The location is determined by how the hardware sets two of the GPIO pins of the chipset. Of course these locations translate into ROM locations 0xB0000, 0xC0000, ... etc, assuming a 1024 kB BIOS ROM. The binary is likely 0x10000 B or 64 kB in size. Copy the range 0xD0000-0xDFFFF from the vendor BIOS ROM to the coreboot ROM at the exact same range. In a 512 kB ROM, subtract 0x80000 from that range. I'm attempting a Coreboot port to another Poulsbo board (the Kontron nanoETXexpress-SP) at the moment, so I've been following your thread with great interest. So far I've had about as much success as you, though. Svante Ekholm M.Sc. student, Uppsala university, Sweden. Located at CrossControl, Alfta, Sweden. Tel +46 73<tel:%2B46%20271%2075%2076%2084>0733342 From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] On Behalf Of Alp Eren Köse Sent: den 20 oktober 2011 15:28 To: coreboot(a)coreboot.org Subject: [coreboot] Intel SCH CMC(Chipset Microcode) state machine binary? Hi all, I am sorry that this could look like a double post which I asked under the "Getting serial output from w83627hf?" topic but couldn't get any reply. So I thought it is better to ask it in a separate mail, being really a different matter. Well, I need the Intel System Controller Hub(SCH), Chipset Microcode(CMC) state machine binary as it is stated in the src/southbridge/inte/sch/Makefile.inc file as: #We don't ship that, but booting without it is bound to fail So how can I get this binary? Does it lay in the proprietary bios that I can extract from maybe? There is something I didn't get as well, is it the same thing with the CPU Microcode? (I have Atom Z510 processor) I did lots of googling but couldn't find it:( would be grateful if someone can help on this. Thanks in advance, Alp

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New patch to review for coreboot: 6b91039 Add bootstrap to select loaded ramstage
by Kyösti Mälkki 20 Oct '11

20 Oct '11

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/304 -gerrit commit 6b910392411668b395536da4646d620f3efd2fc7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 20 21:06:14 2011 +0300 Add bootstrap to select loaded ramstage Just before loading ramstage, read the console serial port pin (DCD). If it is high, select alternative prefix for ramstage. Suggested use: During ramstage development, never overwrite a stable combination of romstage, ramstage and payload on a flash device. Instead, place the ramstage to test under the alternative prefix. Change-Id: Ib8b6984ddd886cd21638880c6f43dd90d078c844 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 13 +++++++++++++ src/arch/x86/lib/cbfs_and_run.c | 14 ++++++++++++++ src/arch/x86/lib/romstage_console.c | 7 +++++++ src/console/Kconfig | 9 +++++++++ src/include/console/console.h | 1 + src/include/uart8250.h | 1 + src/lib/uart8250.c | 5 +++++ 7 files changed, 50 insertions(+), 0 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 525d452..a224cdf 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -46,6 +46,19 @@ config CBFS_PREFIX Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative. +config DUAL_RAMSTAGE + bool + default y if TTYS0_DCD_HOOK + default n + +config CBFS_ALT_PREFIX + string "Alternative CBFS prefix to use" + depends on DUAL_RAMSTAGE + default "normal" + help + Select the prefix for an alternative coreboot RAM stage. + You need some hardware bootstrap to make this choice at boottime. + choice prompt "Compiler" default COMPILER_GCC diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index ad36ddc..b4e6883 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -40,11 +40,25 @@ static void cbfs_and_run_core(const char *filename, unsigned ebp) void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset) { +#if CONFIG_DUAL_RAMSTAGE + int bootstrap = 0; +#endif // FIXME fix input parameters instead normalizing them here. if (cpu_reset == 1) cpu_reset = -1; else cpu_reset = 0; + /* Go altenative way, if any bootstrap returns non-zero */ +#if CONFIG_TTYS0_DCD_HOOK + bootstrap += !!console_dcd(); +#endif +#if CONFIG_DUAL_RAMSTAGE + if (! bootstrap) + cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset); + else + cbfs_and_run_core(CONFIG_CBFS_ALT_PREFIX "/coreboot_ram", cpu_reset); +#else cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset); +#endif } #if CONFIG_AP_CODE_IN_CAR == 1 diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 8adb3ba..587e331 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -61,6 +61,13 @@ static void console_tx_flush(void) #endif } +#if CONFIG_TTYS0_DCD_HOOK +int console_dcd(void) +{ + return uart8250_dcd(CONFIG_TTYS0_BASE); +} +#endif + int do_printk(int msg_level, const char *fmt, ...) { va_list args; diff --git a/src/console/Kconfig b/src/console/Kconfig index 02244d7..ea16c0c 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -91,6 +91,15 @@ config TTYS0_LCS default 3 depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM +config TTYS0_DCD_HOOK + bool "DCD line is bootstrap to alternative ramstage" + default n + depends on CONSOLE_SERIAL8250 + help + Status of DCD line on the selected serial debug console + port is read at boot-time, and is used to choose from + two ramstage prefixes. + # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. config HAVE_USBDEBUG def_bool n diff --git a/src/include/console/console.h b/src/include/console/console.h index 8283f66..f37e7b5 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -62,6 +62,7 @@ extern int console_loglevel; #ifndef __ROMCC__ void console_init(void); +int console_dcd(void); void post_code(u8 value); void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 4a02179..fe49161 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -138,6 +138,7 @@ void uart8250_tx_flush(unsigned base_port); */ void uart8250_init(unsigned base_port, unsigned divisor); void uart_init(void); +int uart8250_dcd(unsigned base_port); /* and the same for memory mapped uarts */ unsigned char uart8250_mem_rx_byte(unsigned base_port); diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index b224671..3221a94 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -62,6 +62,11 @@ int uart8250_can_rx_byte(unsigned base_port) return inb(base_port + UART_LSR) & UART_LSR_DR; } +int uart8250_dcd(unsigned base_port) +{ + return inb(base_port + UART_MSR) & UART_MSR_DCD; +} + unsigned char uart8250_rx_byte(unsigned base_port) { while(!uart8250_can_rx_byte(base_port))

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Patch merged into coreboot/master: ec8dd51 T60: Add support for Ultrabay Legacy I/O devices (40Y8122)
by gerrit＠coreboot.org 20 Oct '11

20 Oct '11

the following patch was just integrated into master: commit ec8dd51ce7df16ddca1d834b97f67be830683ce4 Author: Sven Schnelle <svens(a)stackframe.org> Date: Sat Oct 15 17:31:01 2011 +0200 T60: Add support for Ultrabay Legacy I/O devices (40Y8122) Those modules have basically the same Super I/O capabilities as the Docking station. Unfortunately, the Super I/O in the module shares the same I/O address as the Docking station, so we're not allowed to connect the LPC Docking Bus if such a module is present. To be able to detect this device and use it as early console for coreboot, we have to initialize the GPIO Controller before, as this device is detected via GPIO06. Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb Signed-off-by: Sven Schnelle <svens(a)stackframe.org> See http://review.coreboot.org/282 for details. -gerrit

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Intel SCH CMC(Chipset Microcode) state machine binary?
by Alp Eren Köse 20 Oct '11

20 Oct '11

Hi all, I am sorry that this could look like a double post which I asked under the "Getting serial output from w83627hf?" topic but couldn't get any reply. So I thought it is better to ask it in a separate mail, being really a different matter. Well, I need the Intel System Controller Hub(SCH), Chipset Microcode(CMC) state machine binary as it is stated in the src/southbridge/inte/sch/Makefile.inc file as: #We don't ship that, but booting without it is bound to fail So how can I get this binary? Does it lay in the proprietary bios that I can extract from maybe? There is something I didn't get as well, is it the same thing with the CPU Microcode? (I have Atom Z510 processor) I did lots of googling but couldn't find it:( would be grateful if someone can help on this. Thanks in advance, Alp

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New patch to review for coreboot: 6a22d1c w83627hf: correct typo in ASL include, correct indexed registers and remove unneccesary _PR0 defs
by Christoph Grenz 20 Oct '11

20 Oct '11

Christoph Grenz (christophg+cb(a)grenz-bonn.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/296 -gerrit commit 6a22d1c7e41a6ee47d32572afebc035c114390a3 Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de> Date: Wed Oct 19 02:24:23 2011 +0200 w83627hf: correct typo in ASL include, correct indexed registers and remove unneccesary _PR0 defs Correct a typo in devtree.asl which causes AML processors to fail executing the DSDT with AE_NO_MEMORY or (in case of acpiexec) Divide By Zero. Also removes an superfluous item in the register IndexField and removes unneccessary _PR0 definitions which could confuse AML processors. Change-Id: I02cb9ce4e8f2101cfff8cec4abba7e070fd66364 Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de> --- src/superio/winbond/w83627hf/devtree.asl | 11 ++--------- 1 files changed, 2 insertions(+), 9 deletions(-) diff --git a/src/superio/winbond/w83627hf/devtree.asl b/src/superio/winbond/w83627hf/devtree.asl index fa78845..cbc132d 100644 --- a/src/superio/winbond/w83627hf/devtree.asl +++ b/src/superio/winbond/w83627hf/devtree.asl @@ -74,7 +74,7 @@ Scope (\_SB) ADDR, 8, DATA, 8 } - IndexField (CREG, DATA, ByteAcc, NoLock, Preserve) + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) { Offset (0x02), RST, 1, /* Soft reset */ @@ -84,7 +84,6 @@ Scope (\_SB) Offset (0x20), DID, 8, /* Device ID */ DREV, 8, /* Device Revision */ - POWC, 8, FDPW, 1, /* FDC Power Down */ , 2, PRPW, 1, /* PRT Power Down */ @@ -258,7 +257,6 @@ Scope (\_SB) Store (One, FDPW) EXCM () } - Name (_PR0, Package () { ^^ }) Method (_DIS) { @@ -470,7 +468,6 @@ Scope (\_SB) Store (One, PRPW) EXCM () } - Name (_PR0, Package () { ^^ }) Method (_DIS) { ENCM () @@ -650,7 +647,6 @@ Scope (\_SB) Store (One, UAPW) EXCM () } - Name (_PR0, Package () { ^^ }) Method (_DIS) { @@ -783,7 +779,6 @@ Scope (\_SB) Store (One, UBPW) EXCM () } - Name (_PR0, Package () { ^^ }) Method (_DIS) { @@ -916,7 +911,6 @@ Scope (\_SB) Store (One, UBPW) EXCM () } - Name (_PR0, Package () { ^^ }) Method (_DIS) { @@ -1479,7 +1473,6 @@ Scope (\_SB) Store (One, HWPW) EXCM () } - Name (_PR0, Package () { ^^ }) Method (_CRS) { @@ -1511,4 +1504,4 @@ Scope (\_SB) } #endif } -} \ No newline at end of file +}

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coreboot October 2011