coreboot November 2007

coreboot@coreboot.org

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397 discussions

[LinuxBIOS] [PATCH v3] v2, v3: Bug? in CAR setup with CacheSize!={4k, 8k, 16k}

by Carl-Daniel Hailfinger

Hi, v2 and v3 have almost identical CAR setup code with identical bugs for CAR sizes != {4k,8k,16k}. In v3, the erroneous code paths are not triggered and the bug is latent, but we have at a few boards in v2 which trigger these bugs, resulting in holes and/or smaller size of the CAR area. Let's look at the v3 code: > #ifndef CONFIG_CARSIZE > #define CacheSize 4096 > #else > #define CacheSize CONFIG_CARSIZE > #endif v2 uses DCACHE_RAM_SIZE instead of CONFIG_CARSIZE [...] > clear_fixed_var_mtrr_out: > > #if CacheSize == 0x10000 > /* enable caching for 64K using fixed mtrr */ > movl $0x268, %ecx /* fix4k_c0000*/ > movl $0x06060606, %eax /* WB IO type */ > movl %eax, %edx > wrmsr > movl $0x269, %ecx > wrmsr > #endif OK, 64k are working. > #if CacheSize == 0x8000 > /* enable caching for 32K using fixed mtrr */ > movl $0x269, %ecx /* fix4k_c8000*/ > movl $0x06060606, %eax /* WB IO type */ > movl %eax, %edx > wrmsr > #endif OK, 32k are working. > /* enable caching for 16K/8K/4K using fixed mtrr */ > movl $0x269, %ecx /* fix4k_cc000*/ > #if CacheSize == 0x4000 > movl $0x06060606, %edx /* WB IO type */ > #endif > #if CacheSize == 0x2000 > movl $0x06060000, %edx /* WB IO type */ > #endif > #if CacheSize == 0x1000 > movl $0x06000000, %edx /* WB IO type */ > #endif > xorl %eax, %eax > wrmsr Disable CAR between 16k and 32k unconditionally. Even if CacheSize is 32k or 64k. Not nice. This affects the following boards: ./src/mainboard/amd/db800/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/amd/norwich/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/amd/serengeti_cheetah/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/msi/ms7260/Options.lb:default DCACHE_RAM_SIZE = 0x08000 ./src/mainboard/asus/a8n_e/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/tyan/s2912/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/artecgroup/dbe61/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/supermicro/h8dmr/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/pcengines/alix1c/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/nvidia/l1_2pvv/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/digitallogic/msm800sev/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/gigabyte/ga_2761gxdk/Options.lb:default DCACHE_RAM_SIZE=0x08000 ./src/mainboard/gigabyte/m57sli/Options.lb:default DCACHE_RAM_SIZE=0x08000 If CacheSize is not one of 4k,8k,16k,32k,64k, we will not set up CAR at all. This affects the following board: ./src/mainboard/iwill/dk8_htx/Options.lb:default DCACHE_RAM_SIZE=0x0c000 --------------------------------------------------------------------------------------------- Clean up handling different CAR sizes and round down CAR size to the nearest power of two. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> --- Index: LinuxBIOSv3-CAR/arch/x86/stage0_i586.S =================================================================== --- LinuxBIOSv3-CAR/arch/x86/stage0_i586.S (Revision 510) +++ LinuxBIOSv3-CAR/arch/x86/stage0_i586.S (Arbeitskopie) @@ -301,37 +301,36 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out: -#if CacheSize == 0x10000 - /* enable caching for 64K using fixed mtrr */ - movl $0x268, %ecx /* fix4k_c0000*/ - movl $0x06060606, %eax /* WB IO type */ - movl %eax, %edx - wrmsr - movl $0x269, %ecx - wrmsr -#endif + /* We round down CAR size to the next power of 2 */ + movl $0x269, %ecx /* fix4k_c8000*/ -#if CacheSize == 0x8000 +#if CacheSize >= 0x8000 /* enable caching for 32K using fixed mtrr */ - movl $0x269, %ecx /* fix4k_c8000*/ movl $0x06060606, %eax /* WB IO type */ movl %eax, %edx wrmsr #endif +#if CacheSize => 0x10000 + /* enable caching for 32K-64K using fixed mtrr */ + movl $0x268, %ecx /* fix4k_c0000*/ + wrmsr +#endif + +#if CacheSize < 0x10000 /* enable caching for 16K/8K/4K using fixed mtrr */ - movl $0x269, %ecx /* fix4k_cc000*/ -#if CacheSize == 0x4000 +#if CacheSize >= 0x4000 movl $0x06060606, %edx /* WB IO type */ -#endif -#if CacheSize == 0x2000 +#elif CacheSize >= 0x2000 movl $0x06060000, %edx /* WB IO type */ -#endif -#if CacheSize == 0x1000 +#elif CacheSize >= 0x1000 movl $0x06000000, %edx /* WB IO type */ +#else +#error Invalid CAR size, must be at least 4k. #endif xorl %eax, %eax wrmsr +#endif #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* enable write base caching so we can do execute in place

12 years, 9 months

[LinuxBIOS] r69 - buildrom-devel/packages/filo/conf

by svn＠openbios.org

Author: ward Date: 2007-11-30 21:27:25 +0100 (Fri, 30 Nov 2007) New Revision: 69 Added: buildrom-devel/packages/filo/conf/tyan-s2882-Config Log: The FILO config file for the Tyan s2882 was simply missing (it was overlooked in a previous commit). This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Added: buildrom-devel/packages/filo/conf/tyan-s2882-Config =================================================================== --- buildrom-devel/packages/filo/conf/tyan-s2882-Config (rev 0) +++ buildrom-devel/packages/filo/conf/tyan-s2882-Config 2007-11-30 20:27:25 UTC (rev 69) @@ -0,0 +1,50 @@ +# Use grub instead of autoboot? +USE_GRUB = 1 +# Grub menu.lst path +MENULST_FILE = "hda1:/boot/grub/menu.lst" +# Driver for hard disk, CompactFlash, and CD-ROM on IDE bus +IDE_DISK = 1 +# Add a short delay when polling status registers +# (required on some broken SATA controllers) +IDE_DISK_POLL_DELAY = 1 +# Driver for USB Storage +USB_DISK = 1 +# VGA text console +VGA_CONSOLE = 1 +PC_KEYBOARD = 1 +# Enable the serial console +SERIAL_CONSOLE = 1 +# Serial console; real external serial port +SERIAL_IOBASE = 0x3f8 +SERIAL_SPEED = 115200 +# Filesystems +FSYS_EXT2FS = 1 +FSYS_ISO9660 = 1 +# Support for boot disk image in bootable CD-ROM (El Torito) +ELTORITO = 1 +# PCI support +SUPPORT_PCI = 1 +# Enable this to scan PCI busses above bus 0 +# AMD64 based boards do need this. +PCI_BRUTE_SCAN = 1 +# Loader for standard Linux kernel image, a.k.a. /vmlinuz +LINUX_LOADER = 1 + +# Debugging +#DEBUG_ALL = 1 +#DEBUG_ELFBOOT = 1 +#DEBUG_ELFNOTE = 1 +#DEBUG_LINUXBIOS = 1 +#DEBUG_MALLOC = 1 +#DEBUG_MULTIBOOT = 1 +#DEBUG_SEGMENT = 1 +#DEBUG_SYS_INFO = 1 +#DEBUG_TIMER = 1 +#DEBUG_BLOCKDEV = 1 +#DEBUG_PCI = 1 +#DEBUG_VIA_SOUND = 1 +#DEBUG_LINUXLOAD = 1 +#DEBUG_IDE = 1 +#DEBUG_USB = 1 +#DEBUG_ELTORITO = 1 +

12 years, 9 months

[LinuxBIOS] [PATCH] add support the IEI PCISA-LX

by Nikolay Petukhov

This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX) is based on amd-lx800/cs5536, so most of the on-board hardware is work normally. Signed-off-by: Nikolay Petukhov <nikolay.petukhov(a)gmail.com> -- Nikolay

12 years, 9 months

[LinuxBIOS] Interesting.

by Feng, Libo

Hi, all, In our board, we found the trace is sent out: "Issuing SOFT_RESET…" from the function init_cpus in the file init_cpus.c. But when the function runs, the serial port is still far to be initialized, how dose the trace is sent out? Best Regards 丰立波 Feng Libo @ AMD Ext: 20906 Mobile Phone: 13683249071 Office Phone: 0086-010-62801406

12 years, 9 months

[LinuxBIOS] r2994 - trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb

by svn＠openbios.org

Author: uwe Date: 2007-11-30 03:08:26 +0100 (Fri, 30 Nov 2007) New Revision: 2994 Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_isa.c trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_reset.c trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_usb.c Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/Config.lb trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/chip.h trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_ide.c trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c Log: Improve support for the Intel 82371FB/SB/AB/EB/MB southbridge(s): - Implement ISA related support: - Initialize the RTC - Enable access to all BIOS regions (but _not_ write access to ROM) - Enable ISA (not EIO) support - Without the *_isa.c file, the Super I/O init is never performed - Improve IDE support: - Add config option to enable Ultra DMA/33 for each disk - Add config option to enable legacy IDE port access - Implement hard reset support - Implement USB controller support - Various code cleanups and improvements The code partially supports southbridges other than the 82371EB (but which are very similar), more complete support will follow. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/Config.lb =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/Config.lb 2007-11-29 15:01:53 UTC (rev 2993) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/Config.lb 2007-11-30 02:08:26 UTC (rev 2994) @@ -19,8 +19,9 @@ ## config chip.h - driver i82371eb.o +driver i82371eb_isa.o +driver i82371eb_ide.o +driver i82371eb_usb.o driver i82371eb_smbus.o -driver i82371eb_ide.o - +driver i82371eb_reset.o Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/chip.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/chip.h 2007-11-29 15:01:53 UTC (rev 2993) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/chip.h 2007-11-30 02:08:26 UTC (rev 2994) @@ -23,12 +23,17 @@ #include <device/device.h> -extern struct chip_operations southbridge_intel_i82371eb_ops; +extern const struct chip_operations southbridge_intel_i82371eb_ops; struct southbridge_intel_i82371eb_config { int ide0_enable:1; + int ide0_drive0_udma33_enable:1; + int ide0_drive1_udma33_enable:1; int ide1_enable:1; + int ide1_drive0_udma33_enable:1; + int ide1_drive1_udma33_enable:1; + int ide_legacy_enable:1; int usb_enable:1; }; -#endif /* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */ +#endif /* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */ Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c 2007-11-29 15:01:53 UTC (rev 2993) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.c 2007-11-30 02:08:26 UTC (rev 2994) @@ -18,46 +18,47 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Datasheet: +/* Note: This code supports the 82371FB/SB/MX/AB/EB/MB and 82437MX. */ + +/* Datasheets: + * - Name: 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR + * - URL: http://www.intel.com/design/intarch/datashts/290550.htm + * - PDF: http://download.intel.com/design/intarch/datashts/29055002.pdf + * - Date: April 1997 + * - Order Number: 290550-002 + * + * - Name: 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerator + * Specification Update + * - URL: http://www.intel.com/design/chipsets/specupdt/297658.htm + * - PDF: http://download.intel.com/design/chipsets/specupdt/29765801.pdf + * - Date: March 1998 + * - Order Number: 297658-004 + * * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) + * (applies to 82371AB/EB/MB, a.k.a. PIIX4/PIIX4E/PIIX4M) * - URL: http://www.intel.com/design/intarch/datashts/290562.htm * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf + * - Date: April 1997 * - Order Number: 290562-001 + * + * - Name: 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) Specification Update + * - URL: http://www.intel.com/design/chipsets/specupdt/297738.htm + * - PDF: http://www.intel.com/design/chipsets/specupdt/29773817.pdf + * - Date: January 2002 + * - Order Number: 297738-017 */ -#include <console/console.h> +/* TODO: List the other datasheets. */ + #include <device/device.h> -#include <device/pci.h> #include "i82371eb.h" -/** - * Enable access to all BIOS regions. Do not enable write access to the ROM. - * - * XBCS register bits: - * - Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to - * FFF00000-FFF7FFFF are forwarded to ISA). - * - Set bit 7: Extended BIOS Enable (PCI master accesses to - * FFF80000-FFFDFFFF are forwarded to ISA). - * - Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to - * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top - * of 1 Mbyte, or the aliases at the top of 4 Gbyte - * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. - * - Bit 2: BIOSCS# Write Enable (1=enable, 0=disable). - * - * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. - * - * @param dev The device to use. - */ -void i82371eb_enable(device_t dev) +void i82371eb_enable(struct device *dev) { - uint16_t reg; - - reg = pci_read_config16(dev, XBCS); - reg |= 0x2c0; - pci_write_config16(dev, XBCS, reg); + /* TODO: Nothing to do? */ } -struct chip_operations southbridge_intel_i82371eb_ops = { - CHIP_NAME("Intel 82371EB Southbridge") +const struct chip_operations southbridge_intel_i82371eb_ops = { + CHIP_NAME("Intel 82371FB/SB/MX/AB/EB/MB Southbridge") .enable_dev = i82371eb_enable, }; Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h 2007-11-29 15:01:53 UTC (rev 2993) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb.h 2007-11-30 02:08:26 UTC (rev 2994) @@ -18,27 +18,58 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SOUTHBRIDGE_INTEL_I82371EB_H -#define SOUTHBRIDGE_INTEL_I82371EB_H +#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H +#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H #ifndef __ROMCC__ #include "chip.h" void i82371eb_enable(device_t dev); #endif -#define XBCS 0x4e /* X-Bus Chip Select register */ +/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the + * 'reg' variable, otherwise it clears those bits. + * + * Examples: + * reg16 = ONOFF(conf->ide0_enable, reg16, (1 << 5)); + * reg16 = ONOFF(conf->ide0_enable, reg16, (FOO | BAR)); + */ +/* TODO: Move into some global header file? */ +#define ONOFF(cond,reg,bits) ((cond) ? ((reg) | (bits)) : ((reg) & ~(bits))) -/* SMBus */ -#define SMBBA 0x90 /* SMBus Base Address */ -#define SMBHSTCFG 0xd2 /* SMBus Host Configuration */ +#define XBCS 0x4e /* X-Bus chip select register */ +#define GENCFG 0xb0 /* General configuration register */ +#define RC 0xcf9 /* Reset control register */ /* IDE */ #define IDETIM_PRI 0x40 /* IDE timing register, primary channel */ #define IDETIM_SEC 0x42 /* IDE timing register, secondary channel */ +#define UDMACTL 0x48 /* Ultra DMA/33 control register */ +#define UDMATIM 0x4a /* Ultra DMA/33 timing register */ +/* SMBus */ +#define SMBBA 0x90 /* SMBus base address */ +#define SMBHSTCFG 0xd2 /* SMBus host configuration */ + +/* Power management (ACPI) */ +#define PMBA 0x40 /* Power management base address */ +#define PMREGMISC 0x80 /* Miscellaneous power management */ + /* Bit definitions */ -#define IOSE (1 << 0) /* I/O Space Enable */ -#define SMB_HST_EN (1 << 0) /* Host Interface Enable */ -#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */ +#define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ +#define EXT_BIOS_ENABLE (1 << 7) /* Extended BIOS Enable */ +#define LOWER_BIOS_ENABLE (1 << 6) /* Lower BIOS Enable */ +#define WRITE_PROTECT_ENABLE (1 << 2) /* Write Protect Enable */ +#define SRST (1 << 1) /* System Reset */ +#define RCPU (1 << 2) /* Reset CPU */ +#define SMB_HST_EN (1 << 0) /* Host Interface Enable */ +#define IDE_DECODE_ENABLE (1 << 15) /* IDE Decode Enable */ +#define DTE0 (1 << 3) /* DMA Timing Enable Only, drive 0 */ +#define DTE1 (1 << 7) /* DMA Timing Enable Only, drive 1 */ +#define PSDE0 (1 << 0) /* Primary Drive 0 UDMA/33 */ +#define PSDE1 (1 << 1) /* Primary Drive 1 UDMA/33 */ +#define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */ +#define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */ +#define ISA (1 << 0) /* Select ISA */ +#define EIO (0 << 0) /* Select EIO */ -#endif /* SOUTHBRIDGE_INTEL_I82371EB_H */ +#endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c 2007-11-29 15:01:53 UTC (rev 2993) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c 2007-11-30 02:08:26 UTC (rev 2994) @@ -20,6 +20,7 @@ /* TODO: Implement smbus_write_byte(), smbus_recv_byte(), smbus_send_byte(). */ +#include <stdint.h> #include <device/pci_ids.h> #include "i82371eb.h" #include "i82371eb_smbus.h" @@ -29,35 +30,36 @@ static void enable_smbus(void) { device_t dev; - uint8_t reg8; - uint16_t reg16; + u8 reg8; + u16 reg16; + /* Check for SMBus device PCI ID on the 82371AB/EB/MB. */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); - if (dev == PCI_DEV_INVALID) { + if (dev == PCI_DEV_INVALID) die("SMBus controller not found\r\n"); - } + print_spew("SMBus controller enabled\r\n"); /* Set the SMBus I/O base. */ pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1); - /* Enable the SMBus Controller Host Interface. */ + /* Enable the SMBus controller host interface. */ reg8 = pci_read_config8(dev, SMBHSTCFG); reg8 |= SMB_HST_EN; pci_write_config8(dev, SMBHSTCFG, reg8); /* Enable access to the SMBus I/O space. */ reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 |= IOSE; + reg16 |= PCI_COMMAND_IO; pci_write_config16(dev, PCI_COMMAND, reg16); /* Clear any lingering errors, so the transaction will run. */ outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS); } -static int smbus_read_byte(unsigned int device, unsigned int address) +static int smbus_read_byte(u8 device, u8 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_ide.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_ide.c 2007-11-29 15:01:53 UTC (rev 2993) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_ide.c 2007-11-30 02:08:26 UTC (rev 2994) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* TODO: Check if this really works for all of the southbridges. */ + +#include <stdint.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -28,49 +31,171 @@ * Initialize the IDE controller. * * Depending on the configuration variables 'ide0_enable' and 'ide1_enable' - * we enable or disable the primary and secondary IDE interface, respectively. + * enable or disable the primary and secondary IDE interface, respectively. * + * Depending on the configuration variable 'ide_legacy_enable' enable or + * disable access to the legacy IDE ports and the PCI Bus Master IDE I/O + * registers (this is required for e.g. FILO). + * * @param dev The device to use. */ -static void ide_init(struct device *dev) +static void ide_init_enable(struct device *dev) { - uint16_t reg; + u16 reg16; struct southbridge_intel_i82371eb_config *conf = dev->chip_info; /* Enable/disable the primary IDE interface. */ - reg = pci_read_config16(dev, IDETIM_PRI); + reg16 = pci_read_config16(dev, IDETIM_PRI); + reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDETIM_PRI, reg16); + printk_debug("IDE: %s: %s\n", "Primary IDE interface", + conf->ide0_enable ? "on" : "off"); + + /* Enable/disable the secondary IDE interface. */ + reg16 = pci_read_config16(dev, IDETIM_SEC); + reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDETIM_SEC, reg16); + printk_debug("IDE: %s: %s\n", "Secondary IDE interface", + conf->ide1_enable ? "on" : "off"); + + /* Enable access to the legacy IDE ports (both primary and secondary), + * and the PCI Bus Master IDE I/O registers. + * Only do this if at least one IDE interface is enabled. + */ + if (conf->ide0_enable || conf->ide1_enable) { + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 = ONOFF(conf->ide_legacy_enable, reg16, + (PCI_COMMAND_IO | PCI_COMMAND_MASTER)); + pci_write_config16(dev, PCI_COMMAND, reg16); + printk_debug("IDE: Access to legacy IDE ports: %s\n", + conf->ide_legacy_enable ? "on" : "off"); + } +} + +/** + * Initialize the Ultra DMA/33 support of the IDE controller. + * + * Depending on the configuration variables 'ide0_drive0_udma33_enable', + * 'ide0_drive1_udma33_enable', 'ide1_drive0_udma33_enable', and + * 'ide1_drive1_udma33_enable' enable or disable Ultra DMA/33 support for + * the respective IDE controller and drive. + * + * Only do that if the respective controller is actually enabled, of course. + * + * @param dev The device to use. + */ +static void ide_init_udma33(struct device *dev) +{ + u8 reg8; + struct southbridge_intel_i82371eb_config *conf = dev->chip_info; + + /* Enable/disable UDMA/33 operation (primary IDE interface). */ if (conf->ide0_enable) { - reg |= IDE_DECODE_ENABLE; - print_info("Primary IDE interface enabled\n"); - } else { - reg &= ~(IDE_DECODE_ENABLE); - print_info("Primary IDE interface disabled\n"); + reg8 = pci_read_config8(dev, UDMACTL); + reg8 = ONOFF(conf->ide0_drive0_udma33_enable, reg8, PSDE0); + reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1); + pci_write_config8(dev, UDMACTL, reg8); + + printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", + "Primary IDE interface", 0, + conf->ide0_drive0_udma33_enable ? "on" : "off"); + printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", + "Primary IDE interface", 1, + conf->ide0_drive1_udma33_enable ? "on" : "off"); } - pci_write_config16(dev, IDETIM_PRI, reg); - /* Enable/disable the secondary IDE interface. */ - reg = pci_read_config16(dev, IDETIM_SEC); + /* Enable/disable Ultra DMA/33 operation (secondary IDE interface). */ if (conf->ide1_enable) { - reg |= IDE_DECODE_ENABLE; - print_info("Secondary IDE interface enabled\n"); - } else { - reg &= ~(IDE_DECODE_ENABLE); - print_info("Secondary IDE interface disabled\n"); + reg8 = pci_read_config8(dev, UDMACTL); + reg8 = ONOFF(conf->ide1_drive0_udma33_enable, reg8, SSDE0); + reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1); + pci_write_config8(dev, UDMACTL, reg8); + + printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", + "Secondary IDE interface", 0, + conf->ide1_drive0_udma33_enable ? "on" : "off"); + printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", + "Secondary IDE interface", 1, + conf->ide1_drive1_udma33_enable ? "on" : "off"); } - pci_write_config16(dev, IDETIM_SEC, reg); } -static struct device_operations ide_ops = { +/** + * IDE init for the Intel 82371FB/SB IDE controller. + * + * These devices do not support UDMA/33, so don't attempt to enable it. + * + * @param dev The device to use. + */ +static void ide_init_i82371fb_sb(struct device *dev) +{ + ide_init_enable(dev); +} + +/** + * IDE init for the Intel 82371AB/EB/MB IDE controller. + * + * @param dev The device to use. + */ +static void ide_init_i82371ab_eb_mb(struct device *dev) +{ + ide_init_enable(dev); + ide_init_udma33(dev); +} + +/* Intel 82371FB/SB */ +static const struct device_operations ide_ops_fb_sb = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = ide_init, + .init = ide_init_i82371fb_sb, .scan_bus = 0, - .ops_pci = 0, /* No subsystem IDs on 82371EB! */ + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ }; -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, +/* Intel 82371AB/EB/MB */ +static const struct device_operations ide_ops_ab_eb_mb = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ide_init_i82371ab_eb_mb, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371XX! */ +}; + +/* Intel 82371FB (PIIX) */ +static const struct pci_driver ide_driver_fb __pci_driver = { + .ops = &ide_ops_fb_sb, .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371FB_IDE, +}; + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver ide_driver_sb __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_IDE, +}; + +/* Intel 82371MX (MPIIX) */ +static const struct pci_driver ide_driver_mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371MX_ISA_IDE, +}; + +/* Intel 82437MX (part of the 430MX chipset) */ +static const struct pci_driver ide_driver_82437mx __pci_driver = { + .ops = &ide_ops_fb_sb, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82437MX_ISA_IDE, +}; + +/* Intel 82371AB/EB/MB */ +static const struct pci_driver ide_driver_ab_eb_mb __pci_driver = { + .ops = &ide_ops_ab_eb_mb, + .vendor = PCI_VENDOR_ID_INTEL, .device = PCI_DEVICE_ID_INTEL_82371AB_IDE, }; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_isa.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_isa.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_isa.c 2007-11-30 02:08:26 UTC (rev 2994) @@ -0,0 +1,72 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/isa-dma.h> +#include <pc80/mc146818rtc.h> +#include "i82371eb.h" + +static void isa_init(struct device *dev) +{ + u16 reg16; + u32 reg32; + + /* Initialize the real time clock (RTC). */ + rtc_init(0); + + /* Enable access to all BIOS regions. */ + reg16 = pci_read_config16(dev, XBCS); + reg16 |= LOWER_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE; + reg16 |= EXT_BIOS_ENABLE_1MB; + reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ + pci_write_config16(dev, XBCS, reg16); + + /* + * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) + * bus, which is a subset of ISA. We select the full ISA bus here. + */ + reg32 = pci_read_config32(dev, GENCFG); + reg32 |= ISA; /* Select ISA, not EIO. */ + pci_write_config16(dev, GENCFG, reg32); + + /* Initialize ISA DMA. */ + isa_dma_init(); +} + +static const struct device_operations isa_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = isa_init, + .scan_bus = scan_static_bus, /* TODO: Needed? */ + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371EB! */ +}; + +static const struct pci_driver isa_driver __pci_driver = { + .ops = &isa_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371AB_ISA, +}; Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_reset.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_reset.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_reset.c 2007-11-30 02:08:26 UTC (rev 2994) @@ -0,0 +1,30 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include "i82371eb.h" + +/** + * Initiate a hard reset. + */ +void i82371eb_hard_reset(void) +{ + outb(SRST | RCPU, RC); +} Modified: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c 2007-11-29 15:01:53 UTC (rev 2993) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_smbus.c 2007-11-30 02:08:26 UTC (rev 2994) @@ -18,26 +18,31 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/smbus.h> #include "i82371eb.h" -static struct smbus_bus_operations lops_smbus_bus = { +/* TODO: Needed later? */ +static const struct smbus_bus_operations lops_smbus_bus = { }; -static struct device_operations smbus_ops = { +static const struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = scan_static_bus, - // .enable = i82371eb_enable, // TODO: Needed? + .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ .ops_smbus_bus = &lops_smbus_bus, }; +/* Note: There's no SMBus on 82371FB/SB/MX and 82437MX. */ + +/* Intel 82371AB/EB/MB */ static const struct pci_driver smbus_driver __pci_driver = { .ops = &smbus_ops, .vendor = PCI_VENDOR_ID_INTEL, Added: trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_usb.c =================================================================== --- trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_usb.c (rev 0) +++ trunk/LinuxBIOSv2/src/southbridge/intel/i82371eb/i82371eb_usb.c 2007-11-30 02:08:26 UTC (rev 2994) @@ -0,0 +1,66 @@ +/* + * This file is part of the LinuxBIOS project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "i82371eb.h" + +/** + * Initialize the USB (UHCI) controller. + * + * Depending on the configuration variable 'usb_enable', enable or + * disable the USB (UHCI) controller. + * + * @param dev The device to use. + */ +static void usb_init(struct device *dev) +{ + /* TODO: No special init needed? */ +} + +static const struct device_operations usb_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = usb_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = 0, /* No subsystem IDs on 82371EB! */ +}; + +/* Note: No USB on 82371FB/MX (PIIX/MPIIX) and 82437MX. */ + +/* Intel 82371SB (PIIX3) */ +static const struct pci_driver usb_driver_sb __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371SB_USB, +}; + +/* Intel 82371AB/EB/MB (PIIX4/PIIX4E/PIIX4M) */ +/* The 440MX (82443MX) consists of 82443BX + 82371EB (uses same PCI IDs). */ +static const struct pci_driver usb_driver_ab_eb_mb __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_82371AB_USB, +};

12 years, 9 months

[LinuxBIOS] Can't compile flashrom

by Shocky

Hi, I'm new to LinuxBios, and just looking for a way to flash the bios on an HP laptop without installing Windoze. None of the tricks I've found through Google have worked for me so far, including HP's own utility for making bootable usb keys. I'm trying to compile just the flashrom component of LinuxBios from svn, but make gives me an error telling me that I need to install pciutils-devel and zlib-devel. The problem is these packages are already installed. I extracted the little .test.c program from the Makefile, and determined that the linker is unable to resolve the call to pci_alloc. The problem is I don't know why. The header is there in /usr/include/pci/pci.h, and /usr/lib/libpci.a is there (but I don't know how to tell what symbols the library provides; reached the limit of my expertise there). This happens on two different machines, one running Mandriva 2008.0 (the laptop in question), and the other Mandriva 2007.0 (my desktop pc). Any ideas what's going on and how to resolve it? Shocky -- These are my opinions. Get your own.

12 years, 9 months

[LinuxBIOS] Multi-TB fileserver

by Richard Smith

I've had a couple of questions on what I'm doing and if this multi-TB server is a commercial product... So I'm posting the response to the list. I'm still working hard at OLPC. My @laptop.org address isn't on the linuxbios list. The fileserver project is personal. - I've got a large amount of old LP albums that I'm going to digitize to 96k 24-bit, do scratch removal, and then encode to flac, mp3, and ogg. - I've got a whole butload of stuff on old hard drives and sorts of different media and no longer a big 3000 sqft home to store it all in. (Moving to Boston really showed me how much crap I had). I tire of having to find a machine or a USB->IDE dongle to prowl whats on the old HD. - A few big ass boxes of CD's that need ripped. - Interest in setting up a some nodes of some of the distributed peer-to-per cluster type storage stuff I see. For save it to the mesh and it never goes away type thing. Basically to start heading toward some sort of setup where I can archive/cache all my data in one place and then index it. Rather than your average NAS plus a server to drive it I was thinking I would use LB and a SATA mother board to roll it all together. So searching for motherboards that have >= 4 SATA ports and LinuxBios support I was quite happy to find the GA-M57LSI. Working with current 1TB disks and soft-RAID5 I should be able to scale this up to 5 TB. -- Richard A. Smith smithbone(a)gmail.com

12 years, 9 months

[LinuxBIOS] [PATCH] v3: big arch/x86/stage1.c and lib/lar.c cleanup

by Carl-Daniel Hailfinger

Consolidate all multiple segment handling into lib/lar.c:load_file_segments() and greatly simplify arch/x86/stage1.c code as a result. While I'm at it, improve the LAR segmentation abstraction. Stage 1 code should not have to care about internal representation of segments, that knowledge belongs into lib/lar.c. Constification of most function parameters in lib/lar.c led to a few other now obvious code removals. Build tested and runtime tested in Qemu. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-betterlarsegments/include/lar.h =================================================================== --- LinuxBIOSv3-betterlarsegments/include/lar.h (Revision 529) +++ LinuxBIOSv3-betterlarsegments/include/lar.h (Arbeitskopie) @@ -82,10 +82,11 @@ }; /* Prototypes. */ -int find_file(struct mem_file *archive, const char *filename, struct mem_file *result); -int copy_file(struct mem_file *archive, const char *filename, void *where); -int run_file(struct mem_file *archive, const char *filename, void *where); -int execute_in_place(struct mem_file *archive, const char *filename); +int find_file(const struct mem_file *archive, const char *filename, struct mem_file *result); +int copy_file(const struct mem_file *archive, const char *filename, void *where); +int run_file(const struct mem_file *archive, const char *filename, void *where); +int execute_in_place(const struct mem_file *archive, const char *filename); int run_address(void *f); -void *load_file(struct mem_file *archive, const char *filename); +void *load_file(const struct mem_file *archive, const char *filename); +void *load_file_segments(const struct mem_file *archive, const char *filename); #endif /* LAR_H */ Index: LinuxBIOSv3-betterlarsegments/lib/lar.c =================================================================== --- LinuxBIOSv3-betterlarsegments/lib/lar.c (Revision 529) +++ LinuxBIOSv3-betterlarsegments/lib/lar.c (Arbeitskopie) @@ -56,7 +56,7 @@ * returns 0 on success, -1 otherwise */ -int find_file(struct mem_file *archive, const char *filename, struct mem_file *result) +int find_file(const struct mem_file *archive, const char *filename, struct mem_file *result) { char *walk, *fullname; struct lar_header *header; @@ -145,7 +145,7 @@ return 1; } -static int process_file(struct mem_file *archive, void *where) +static int process_file(const struct mem_file *archive, void *where) { printk(BIOS_SPEW, "LAR: Compression algorithm #%i used\n", archive->compression); /* no compression */ @@ -175,6 +175,37 @@ } /** + * Given a file name, search the LAR for all segments of it, and load them + * into memory, using the loadaddress pointer in the mem_file struct. + * @param archive A descriptor for current archive. + * @param filename filename to find + * returns entry on success, (void*)-1 otherwise + * FIXME: Look for a cmdline as well. + */ +void *load_file_segments(const struct mem_file *archive, const char *filename) +{ + void *entry = NULL; + void *newentry; + int i; + char tmpname[64]; + + for(i = 0, entry = (void *)0; ;i++) { + sprintf(tmpname, "%s/segment%d", filename, i); + newentry = load_file(archive, tmpname); + if (newentry == (void *)-1) + break; + if (!entry) + entry = newentry; + } + if (!entry) { + printk(BIOS_INFO, "LAR: load_file_segments: Failed for %s\n", filename); + return (void *)-1; + } + printk(BIOS_SPEW, "LAR: load_file_segments: All loaded, entry %p\n", entry); + return entry; +} + +/** * Given a file name in the LAR , search for it, and load it into memory, using * the loadaddress pointer in the mem_file struct. * @param archive A descriptor for current archive. @@ -182,7 +213,7 @@ * returns entry on success, (void*)-1 otherwise */ -void *load_file(struct mem_file *archive, const char *filename) +void *load_file(const struct mem_file *archive, const char *filename) { int ret; struct mem_file result; @@ -212,7 +243,7 @@ * @param where pointer to where to load the data * returns 0 on success, -1 otherwise */ -int copy_file(struct mem_file *archive, const char *filename, void *where) +int copy_file(const struct mem_file *archive, const char *filename, void *where) { int ret; struct mem_file result; @@ -229,55 +260,30 @@ /** - * Given a file name in the LAR , search for it, and load it into memory, - * using the passed-in pointer as the address; jump to the file. - * If the passed-in pointer is (void *)-1, then execute the file in place. + * Given a file name in the LAR , search for it, and execute it in place. * @param archive A descriptor for current archive. * @param filename filename to find - * @param where pointer to where to load the data * returns 0 on success, -1 otherwise */ -int run_file(struct mem_file *archive, const char *filename, void *where) +int execute_in_place(const struct mem_file *archive, const char *filename) { struct mem_file result; int ret; + void *where; - if ((u32) where != 0xFFFFFFFF) { - if (copy_file(archive, filename, where)) { - printk(BIOS_INFO, - "LAR: Run file %s failed: No such file.\n", - filename); - return 1; - } - } else { /* XIP */ - if (find_file(archive, filename, &result)) { - printk(BIOS_INFO, - "LAR: Run file %s failed: No such file.\n", - filename); - return 1; - } - if (result.compression != 0) { - printk(BIOS_INFO, - "LAR: Run file %s failed: Compressed file" - " not supported for in-place execution\n", - filename); - return 1; - } - where = result.start + (u32)result.entry; + if (find_file(archive, filename, &result)) { + printk(BIOS_INFO, "LAR: Run file %s failed: No such file.\n", + filename); + return 1; } + if (result.compression != 0) { + printk(BIOS_INFO, "LAR: Run file %s failed: Compressed file" + " not supported for in-place execution\n", filename); + return 1; + } + where = result.start + (u32)result.entry; printk(BIOS_SPEW, "Entry point is %p\n", where); ret = run_address(where); printk(BIOS_SPEW, "run_file returns with %d\n", ret); return ret; } - -/** - * Given a file name in the LAR , search for it, and execute it in place. - * @param archive A descriptor for current archive. - * @param filename filename to find - * returns 0 on success, -1 otherwise - */ -int execute_in_place(struct mem_file *archive, const char *filename) -{ - return run_file(archive, filename, (void *) 0xFFFFFFFF); -} Index: LinuxBIOSv3-betterlarsegments/arch/x86/stage1.c =================================================================== --- LinuxBIOSv3-betterlarsegments/arch/x86/stage1.c (Revision 529) +++ LinuxBIOSv3-betterlarsegments/arch/x86/stage1.c (Arbeitskopie) @@ -77,7 +77,6 @@ struct mem_file archive, result; int elfboot_mem(struct lb_memory *mem, void *where, int size); void *entry; - int i; /* we can't statically init this hack. */ unsigned char faker[64]; @@ -161,11 +160,9 @@ /* Turn off Cache-As-Ram */ disable_car(); - entry = load_file(&archive, "normal/stage2.o/segment0"); + entry = load_file_segments(&archive, "normal/stage2.o"); if (entry == (void *)-1) - die("FATAL: Failed loading stage2 segment0."); - if (load_file(&archive, "normal/stage2.o/segment1") == (void *)-1) - die("FATAL: Failed loading stage2 segment1."); + die("FATAL: Failed loading stage2."); ret = run_address(entry); if (ret) die("FATAL: Failed in stage2 code."); @@ -176,26 +173,8 @@ if (! ret) legacy(&archive, "normal/payload", (void *)UNCOMPRESS_AREA, mem); - - /* new style lar boot. Install all the files in memory. - * By convention we take the entry point from the first - * one. Look for a cmdline as well. - */ - for(i = 0, entry = (void *)0; ;i++) { - char filename[64]; - void *newentry; - sprintf(filename, "normal/payload/segment%d", i); - archive.len = *(u32 *)0xfffffff4; - archive.start =(void *)(0UL-archive.len); - newentry = load_file(&archive, filename); - printk(BIOS_SPEW, "newentry is %p\n", newentry); - if (newentry == (void *)-1) - break; - if (! entry) - entry = newentry; - } - printk(BIOS_SPEW, "all loaded, entry %p\n", entry); - if (entry) + entry = load_file_segments(&archive, "normal/payload"); + if (entry != (void*)-1) run_address(entry); die("FATAL: No usable payload found.\n");

12 years, 9 months

[LinuxBIOS] License header missing in util/flashrom/layout.c

by Alex Beregszaszi

Hi, the subject says it all. The missing header in udelay.c was added a few days ago, this should not be missed. -- Alex

12 years, 9 months

[LinuxBIOS] [BUILDROM] Download and prepend the VGA VBIOS for the ga-2761gxdk

by Jordan Crouse

This one is the most exciting - finally add support for automagically downloading and pre-pending the VGA VBIOS for the ga-2761gxdk. This should be a framework for future optionroms to be downloaded and used from linxubios.org. I'm not super happy with how congested packages/linuxbios is getting - I think there is definitely some room for consolidation and improvement, but we are hobbled by v2 in many regards. v3 will make this stuff so much better. -- Jordan Crouse Systems Software Development Engineer Advanced Micro Devices, Inc. [BUILDROM] Download and prepend the VGA VBIOS for the ga-2761gxdk First try at downloading and prepending the VGA VBIOS for the ga-2761gxdk board stored on linuxbios.org. This should be generic enough to extend to other platforms when the time comes. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Index: buildrom-devel/packages/linuxbios/generic-linuxbios.mk =================================================================== --- buildrom-devel.orig/packages/linuxbios/generic-linuxbios.mk +++ buildrom-devel/packages/linuxbios/generic-linuxbios.mk @@ -12,8 +12,20 @@ LINUXBIOS_TARBALL=linuxbios-svn-$(LINUXB LINUXBIOS_PAYLOAD_TARGET=$(LINUXBIOS_BUILD_DIR)/payload.elf TARGET_ROM = $(LINUXBIOS_VENDOR)-$(LINUXBIOS_BOARD).rom +# This is the list of components that comprise the ROM (excluding the payload) +LINUXBIOS_COMPONENTS = $(LINUXBIOS_OUTPUT) + include $(PACKAGE_DIR)/linuxbios/linuxbios.inc +# If an optionrom was specified in the configuration, then use it + +ifneq($(OPTIONROM_ID),) +include $(PACKAGE_DIR)/linuxbios/optionroms.inc + +# Add it to the front of the list so it is prepended to the LinuxBIOS output +LINUXBIOS_COMPONENTS = $(SOURCE_DIR)/$(OPTIONROM_ID).rom $(LINUXBIOS_COMPONENTS) +endif + $(SOURCE_DIR)/$(LINUXBIOS_TARBALL): @ echo "Fetching the LinuxBIOS code..." @ mkdir -p $(SOURCE_DIR)/linuxbios @@ -21,9 +33,9 @@ $(SOURCE_DIR)/$(LINUXBIOS_TARBALL): $(LINUXBIOS_TAG) $(SOURCE_DIR)/$(LINUXBIOS_TARBALL) \ > $(LINUXBIOS_FETCH_LOG) 2>&1 -$(OUTPUT_DIR)/$(TARGET_ROM): $(LINUXBIOS_OUTPUT) +$(OUTPUT_DIR)/$(TARGET_ROM): $(LINUXBIOS_COMPONENTS) @ mkdir -p $(OUTPUT_DIR) - @ cp $< $@ + @ cat $(LINUXBIOS_COMPONENTS) > $@ linuxbios: $(OUTPUT_DIR)/$(TARGET_ROM) linuxbios-clean: generic-linuxbios-clean Index: buildrom-devel/packages/linuxbios/optionroms.inc =================================================================== --- /dev/null +++ buildrom-devel/packages/linuxbios/optionroms.inc @@ -0,0 +1,12 @@ +# Rules to download option roms from the LinuxBIOS option rom +# repository + +OPTIONROMURL=http://www.linuxbios.org/data/optionroms/ + +$(OUTPUT_DIR)/$(OPTIONROM_ID).license: + @ mkdir -p $(OUTPUT_DIR) + @ wget -P $(OUTPUT_DIR) $(OPTIONROMURL)/$(OPTIONROM_ID).license -O $@ + +$(SOURCE_DIR)/$(OPTIONROM_ID).rom: $(OUTPUT_DIR)/$(OPTIONROM_ID).license + @ mkdir -p $(SOURCE_DIR) + @ wget -P $(SOURCE_DIR) $(OPTIONROMURL)/$(OPTIONROM_ID).rom -O $@ Index: buildrom-devel/packages/linuxbios/ga-2761gxdk-linuxbios.mk =================================================================== --- buildrom-devel.orig/packages/linuxbios/ga-2761gxdk-linuxbios.mk +++ buildrom-devel/packages/linuxbios/ga-2761gxdk-linuxbios.mk @@ -16,6 +16,12 @@ TARGET_ROM = $(LINUXBIOS_VENDOR)-$(LINUX include $(PACKAGE_DIR)/linuxbios/linuxbios.inc +# This matches the base name of the ROM on +# http://www.linuxbios.org/data/optionroms/ + +OPTIONROM_ID = pci1039,6330 +include $(PACKAGE_DIR)/linuxbios/optionroms.inc + $(SOURCE_DIR)/$(LINUXBIOS_TARBALL): @ echo "Fetching the LinuxBIOS code..." @ mkdir -p $(SOURCE_DIR)/linuxbios @@ -23,9 +29,9 @@ $(SOURCE_DIR)/$(LINUXBIOS_TARBALL): $(LINUXBIOS_TAG) $(SOURCE_DIR)/$(LINUXBIOS_TARBALL) \ > $(LINUXBIOS_FETCH_LOG) 2>&1 -$(OUTPUT_DIR)/$(TARGET_ROM): $(LINUXBIOS_OUTPUT) +$(OUTPUT_DIR)/$(TARGET_ROM): $(LINUXBIOS_OUTPUT) $(SOURCE_DIR)/$(OPTIONROM_ID).rom @ mkdir -p $(OUTPUT_DIR) - @ cat $(LINUXBIOS_OUTPUT) > $@ + @ cat $(SOURCE_DIR)/$(OPTIONROM_ID).rom $(LINUXBIOS_OUTPUT) > $@ linuxbios: $(OUTPUT_DIR)/$(TARGET_ROM) linuxbios-clean: generic-linuxbios-clean

12 years, 9 months

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coreboot November 2007